Testing of logic operation

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CPC
G01R31/3177

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/3177Testing of logic operation

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Data gating using scan enable pin
- Patent number 12,287,370
- Issue date Apr 29, 2025
- Apple Inc.
- FNU Rajeev Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Mechanism capable of performing on-chip test and verification
- Patent number 12,253,564
- Issue date Mar 18, 2025
- Silicon Motion, Inc.
- Tse-Yen Liu
- G01 - MEASURING TESTING
Information Patent Grant
Debug trace microsectors
- Patent number 12,248,021
- Issue date Mar 11, 2025
- Altera Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting defective logic devices
- Patent number 12,248,022
- Issue date Mar 11, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chi-Che Wu
- G01 - MEASURING TESTING
Information Patent Grant
System and method for fault sequence recording
- Patent number 12,235,319
- Issue date Feb 25, 2025
- Texas Instruments Incorporated
- Abhinay Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant synchronizer
- Patent number 12,222,390
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Denis Roland Beaudoin
- G01 - MEASURING TESTING
Information Patent Grant
Performing scan data transfer inside multi-die package with serdes...
- Patent number 12,216,162
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock shaper circuit for transition fault testing
- Patent number 12,216,160
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 12,203,984
- Issue date Jan 21, 2025
- STMicroelectronics S.r.l.
- Marco Casarsa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Signal test
- Patent number 12,196,803
- Issue date Jan 14, 2025
- Infineon Technologies AG
- Muhammad Hassan
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for validation of operation of a logic module i...
- Patent number 12,174,252
- Issue date Dec 24, 2024
- STMicroelectronics S.r.l.
- Diego Alagna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Bi-directional scan flip-flop circuit and method
- Patent number 12,166,487
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect acquisition of a signal from a device under test
- Patent number 12,135,353
- Issue date Nov 5, 2024
- Tektronix, Inc.
- Sam J. Strickling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus to implement a boundary scan for shared analo...
- Patent number 12,130,329
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit including constant-0 flip flops reconfigured to...
- Patent number 12,130,330
- Issue date Oct 29, 2024
- QUALCOMM Incorporated
- Paul Policke
- G01 - MEASURING TESTING
Information Patent Grant
Loopback testing of integrated circuits
- Patent number 12,123,908
- Issue date Oct 22, 2024
- PROTEANTECS LTD.
- Eyal Fayneh
- G01 - MEASURING TESTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 12,117,490
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Multiple clock and clock cycle selection for x-tolerant logic built...
- Patent number 12,117,488
- Issue date Oct 15, 2024
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test in a single-wire bus circuit
- Patent number 12,092,689
- Issue date Sep 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to identify faults in processors
- Patent number 12,085,610
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Applications of adaptive microelectronic circuits that are designed...
- Patent number 12,085,611
- Issue date Sep 10, 2024
- Minima Processor Oy
- Lauri Koskinen
- G01 - MEASURING TESTING
Information Patent Grant
Measuring input receiver thresholds using automated test equipment...
- Patent number 12,078,677
- Issue date Sep 3, 2024
- Amazon Technologies, Inc.
- Brendan Tully
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20250130278
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Boundary Scan Power Up Voltage Level Configuration
- Publication number 20250123328
- Publication date Apr 17, 2025
- Ching Sia Lim
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT CONVERSION METHOD, LATCH CIRCUIT, AND C-ELEMENT CIRCUIT
- Publication number 20250102572
- Publication date Mar 27, 2025
- Sony Semiconductor Solutions Corporation
- Yuji Kaba
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN...
- Publication number 20250093414
- Publication date Mar 20, 2025
- Advantest Corporation
- Michael BRAUN
- G01 - MEASURING TESTING
Information Patent Application
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
- Publication number 20250096783
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20250085343
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPERCONDUCTIVE INTEGRATED CIRCUIT DEVICES WITH ON-CHIP TESTING
- Publication number 20250067802
- Publication date Feb 27, 2025
- Synopsys, Inc.
- Abdelrahman G. QOUTB
- G01 - MEASURING TESTING
Information Patent Application
PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION
- Publication number 20250067803
- Publication date Feb 27, 2025
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
TEST APPARATUS AND TEST METHOD FOR DETECTING DEFECTS OF ELEMENTS IN...
- Publication number 20250062752
- Publication date Feb 20, 2025
- Samsung Electronics Co., Ltd.
- Seonghoon Park
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS
- Publication number 20250052813
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
CLOCK CONTROL CIRCUIT AND METHOD
- Publication number 20250035702
- Publication date Jan 30, 2025
- REALTEK SEMICONDUCTOR CORPORATION
- Yu-Ting LI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...
- Publication number 20250027993
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Paul POLICKE
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250020719
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDING
- Publication number 20240393392
- Publication date Nov 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhinay Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS
- Publication number 20240345160
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT
- Publication number 20240345162
- Publication date Oct 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
- Publication number 20240337691
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE TESTING DEVICE FOR TESTING A STORAGE SYSTEM
- Publication number 20240329137
- Publication date Oct 3, 2024
- International Business Machines Corporation
- Brent William YARDLEY
- G01 - MEASURING TESTING
Information Patent Application
Fault Protected Signal Splitter Apparatus
- Publication number 20240332775
- Publication date Oct 3, 2024
- Nanotronics Imaging, Inc.
- John B. Putman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20240333265
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION...
- Publication number 20240319270
- Publication date Sep 26, 2024
- STMicroelectronics International N.V.
- Shikhar MAKKAR
- G01 - MEASURING TESTING
Information Patent Application
MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION
- Publication number 20240310436
- Publication date Sep 19, 2024
- SILICON MOTION, INC.
- Tse-Yen Liu
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT, MEMORY DEVICE INCLUDING THE INTEGRATED CIRCUIT,...
- Publication number 20240310437
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME
- Publication number 20240295603
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-En Huang
- H03 - BASIC ELECTRONIC CIRCUITRY

Testing of logic operation

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Data gating using scan enable pin

Mechanism capable of performing on-chip test and verification

Debug trace microsectors

Method and apparatus for detecting defective logic devices

System and method for fault sequence recording

Fault tolerant synchronizer

Performing scan data transfer inside multi-die package with serdes...

Clock shaper circuit for transition fault testing

Device access port selection

Scan chain circuit and corresponding method

Signal test

Test access port with address and command capability

At-speed test access port operations

Circuit arrangement for validation of operation of a logic module i...

3D tap and scan port architectures

Bi-directional scan flip-flop circuit and method

Commanded JTAG test access port operations

Selectable JTAG or trace access with data store and output

Indirect acquisition of a signal from a device under test

Interface to full and reduced pin JTAG devices

Methods and apparatus to implement a boundary scan for shared analo...

Integrated circuit including constant-0 flip flops reconfigured to...

Loopback testing of integrated circuits

Scan frame based test access mechanisms

Multiple clock and clock cycle selection for x-tolerant logic built...

Selectable JTAG or trace access with data store and output

Scan test in a single-wire bus circuit

Methods and apparatus to identify faults in processors

Applications of adaptive microelectronic circuits that are designed...

Measuring input receiver thresholds using automated test equipment...

Patents Applicationslast 30 patents

AT-SPEED TEST ACCESS PORT OPERATIONS

Boundary Scan Power Up Voltage Level Configuration

CIRCUIT CONVERSION METHOD, LATCH CIRCUIT, AND C-ELEMENT CIRCUIT

3D TAP & SCAN PORT ARCHITECTURES

APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN...

BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

SUPERCONDUCTIVE INTEGRATED CIRCUIT DEVICES WITH ON-CHIP TESTING

PARTIAL CHAIN RECONFIGURATION FOR TEST TIME REDUCTION

TEST APPARATUS AND TEST METHOD FOR DETECTING DEFECTS OF ELEMENTS IN...

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS

CLOCK CONTROL CIRCUIT AND METHOD

INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDING

ADDRESSABLE TEST ACCESS PORT

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

STORAGE TESTING DEVICE FOR TESTING A STORAGE SYSTEM

Fault Protected Signal Splitter Apparatus

Low Hold Multi-Bit Flip-Flop

3D STACKED DIE TEST ARCHITECTURE

RESET FOR SCAN MODE EXIT FOR DEVICES WITH POWER-ON RESET GENERATION...

MECHANISM CAPABLE OF PERFORMING ON-CHIP TEST AND VERIFICATION

INTEGRATED CIRCUIT, MEMORY DEVICE INCLUDING THE INTEGRATED CIRCUIT,...

DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME