Patent Application
20240072057
The present technology is directed to apparatuses, such as semiconductor devices including memory and processors, and several embodiments are directed to semiconductor devices that include adjusted n-wells.
The current trend in semiconductor fabrication is to manufacture smaller and faster devices with a higher density of components for computers, cell phones, pagers, personal digital assistants, and many other products. However, decrease in circuit size can lead to other unanticipated issues. For example, decreasing the footprint of each transistor (e.g., the distances between the components therein) and/or decreasing the distance between transistors often increases noise levels and unintended current flows within or across the components/circuits.
In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
Several embodiments of semiconductor devices, packages, and/or assemblies in accordance with the present technology can include circuits (e.g., transistors) including one or more adjusted (bottom) wells. The transistors can be configured according to a triple-well (TW) structure that includes the adjusted wells (e.g., deep N-wells) embedded in a doped substrate (e.g., a P-substrate). The adjusted wells can be integral with or connected to complementary wells (e.g., N-wells complementing the P-substrate) that correspond to source and drain portions of the transistors. The complementary wells can be opposite or surround a gate portion of each transistor. The adjusted wells can be below the complementary wells and extend laterally between the complementary wells. Accordingly, the adjusted wells and the complementary wells can surround or define an isolated well (e.g., an isolated P-well) that matches the doping type of the substrate and/or complements that of the adjusted well.
The adjusted wells can be formed by implanting the doping material through patterned masks (e.g., oxide nitride masks) instead of implanting before the masking step. In other words, a manufacturing process for the transistors can include forming the patterned masks over the doped substrate, and then subsequently forming the adjusted wells. The resulting transistors/adjusted wells can have physical characteristics that are unique or byproducts of the manufacturing process. For example, the adjusted wells can have a depression that is defined by depth transition portion(s). Outer portions of the adjusted wells (e.g., portions near the complementary wells), corresponding to portions under the patterned masks, can have a first depth. Inner portions of the adjusted wells, corresponding to portions under the openings in the masks and/or the gate portions, can have a second depth greater than the first depth. The depression of the adjusted well can have a width that is greater than a gate interface width. In some embodiments, the depression can be configured such that the depth transition portion is laterally separated from the gate portion by an adjusted separation distance that is equal to or greater than the second depth.
Accordingly, the manufacturing process and the resulting physical characteristics can provide improved features of the TW structure while reducing/eliminating weaknesses thereof. For example, the adjusted wells can provide reduced noise levels and accurate state transitions in comparison to conventional transistors. Further, in comparison to conventional TW structures, the adjusted wells of the described embodiments can provide (1) improved connections or hook-up strength with the complementary wells by maintaining a relatively low first depth while (2) reducing/eliminating portions at risk of causing punch-through failures (e.g., in high-voltage Field Effect Transistor (FET) applications) by maintaining the second depth across the adjusted separation distance. Additionally, the manufacturing process can leverage existing process steps, thereby minimizing the adjustments, complexities, errors, and costs associated with the updates or adjustments in comparison to the conventional manufacturing process/sequence.
The first device 100 can include a substrate 102, such as a P-type semiconductor material, with a first bottom well 104 embedded therein. The bottom well 104 can have a type or doping (e.g., N-type) that is different from or complements the substrate 102. The bottom well 104 can correspond to the deep well or the third well of the TW structure.
The bottom well 104 can be connected to or integral with complementary wells 106 through implant portions 108. The complementary wells 106 can include portions having a type or doping matching the bottom well 104 and different than/complementary to that of the substrate 102. The complementary wells 106 can be adjacent to or surround source and drain portions of the first device 100. The implant portions 108 can correspond to vertical extensions having the same doping type as the wells 104 and 106. Accordingly, the implant portions 108 can effectively tie or integrate the wells 104 and 106 together and serve as sidewalls. In doing so, the combination of the wells 104 and 106 and the implant portions 108 can surround and/or define an isolated well 110 (e.g., an isolated P-well). The isolated well 110 can extend laterally between the complementary wells and upward from the bottom well 104 toward the top portion of the substrate 102/device 100.
The first device 100 can include a gate portion 112 above the bottom well 104 and between (e.g., along a lateral direction) the complementary wells 106. The gate portion 112 can be configured to control a current between the source and the drain (e.g., portions of the isolated well 110 and/or layers under corresponding source/drain contacts). The gate portion 112 can include a gate oxide 114 that is disposed between a contact or an external interface and the isolated well 110. In some embodiments, the gate oxide 114 can directly contact the external interface and the isolated well 110 or an open portion thereof (e.g., a gate interface portion 116). The gate interface portion 116 of the isolated well 110 and/or the gate oxide 114 can have a dimension (e.g., a gate interface width 118) measured along a lateral direction.
The bottom well 104 can have a dimension that is measured along the lateral direction and is greater than the gate interface width 118. For example, the bottom well 104 can have a generally planar shape/surface extending laterally between the complementary wells 106. The laterally extending portion of the bottom well 104 can have the dimension/width that is greater than the gate interface width 118.
The planar shape/surface can correspond to a generally constant thickness (e.g., a depth for the bottom well 104) for the isolated well 110 between the complementary wells 106. In other words, the bottom well 104 can have a generally constant depth for the portion(s) thereof extending between the complementary wells 106. The depth for the bottom well 104 can be controlled/configured to prevent current breaches or punch-through failures. In other words, the implant portions 108 can be used to control and increase a vertical distance or depth between the bottom well 104 and the gate portion 112 or a corresponding top surface of the substrate 102.
Similar to the first device 100,
The second device 150 can include a second bottom well 154 and a second implant portion 158 that surrounds/defines an isolated well 166 (e.g., P-well) that respectively correspond to but different from the first bottom well 104, the first implant portion 108, and the isolated well 110. For example, the second implant portions 158 can have a dimension (e.g., a height measured along a vertical direction) that is less than that of the first implant portions 108. Also, the second bottom well 154 can have a bottom well depression 160 having a lower/deeper depth than other portions (e.g., portions closer to the implant portions 158. The bottom well depression 160 can have a dimension (e.g., a depression width 162) measured along a lateral direction. As such, the bottom well depression 160 can have edges that are surrounded/defined by depth transitions portions.
The bottom well depression 160 can be directly under and overlapped by the gate portion 112. Accordingly, the bottom well depression 160 can have the edges or peripheral portions aligned with those of the gate portion 112. The depression width 162 can generally match the gate oxide width 118. In some embodiments, the dimensions and the shape of the bottom well depression 160 can correspond to forming the second bottom well 154 or the bottom well depression 160 thereof based on the gate oxide 114, such as implanting through the corresponding/shaped nitride layer.
Based on the bottom well depression 160, the isolated well 166 can have corresponding shape that deviates from a planar bottom portion of the isolated well 110 of
Further, the device 200 can include a gate portion 212. The gate portion 212 can include a gate oxide 214 disposed between a gate contact or other externally interfacing structure and a gate interface portion 216 of the isolated well 210. The gate interface portion 216 can have a dimension (e.g., a gate interface width 218) measured along a lateral direction. Unlike the devices 100 and 150, the gate oxide 214 can have a dimension (e.g., an oxide width 215) that is different from or greater than the gate interface width 218.
The adjusted bottom well 204 can have a shape that is different from that of the devices 100 of
The difference in the shapes of the adjusted bottom well 204, along with the corresponding difference in shape for the isolated well 210, can correspond to an adjusted well depression 260 (e.g., a portion of the adjusted bottom well 204 having maximum depth or distance away from a top portion of the substrate 202). The adjusted bottom well 204 can include the adjusted well depression 260 having a generally planar shape or planar top surface and an adjusted width 262 between depth transition portions 270. The adjusted width 262 can be greater than the gate interface width 218. Additionally, the adjusted width can generally match the oxide width 215. The adjusted bottom well 204 can have a first depth 272 between the complementary wells 206 and the depth transition portions 270. Opposite the depth transition portions 270 and in the adjusted well depression 260, the adjusted bottom well 204 can have a second depth 274 that is greater than the first depth 272.
Based on the shape of the adjusted well depression 260, the adjusted bottom well 204 can have an adjusted separation distance 276 (measured along a lateral direction) between the gate portion 212 and/or the gate interface portion 216 and the depth transition portions 270. In other words, the adjusted bottom well 204 can have or maintain the second depth 274 across the adjusted separation distance 276 or along the portions of the adjusted bottom well 204 and/or the adjusted well depression 260 between peripheral portions/edges of the gate interface portion 216 and the depth transition portions 270. In some embodiments, the adjusted separation distance 276 can be equal to or greater than the second depth 274. Accordingly, the device 200 can maintain sufficient separation between the gate portion 212 and the adjusted bottom well 204, thereby effectively reducing/eliminating the risk zones 170 of
Additionally, the device 200 can use the adjusted bottom well 204 and the corresponding manufacturing process to establish the second depth 274 and the adjusted separation distance 276 using the shorter implant portions 208 instead of the elongated implant portions 108 of
As described above, one or more the physical characteristics of the semiconductor device 200 of
The phase 400 can further correspond to forming the adjusted bottom well 204, such as by depositing doping (e.g., N-type) implants into the substrate 202. Instead of depositing the dopants directly to the substrate (at, e.g., the phase 300 of
By forming the adjusted bottom well 204 after forming the nitride oxides, the manufacturing process can form/shape the adjusted bottom well 204 and the adjusted well depression 260 thereof according to targeted shapes and dimensions. As described above, the resulting adjusted bottom well 204 can increase the hook-up strength while minimizing/eliminating the risk zones 170 of
The complementary wells 206 can be formed by depositing dopants (e.g., N-type). The dopants can be deposited to at least the first depth 272 of
At block 704, patterned mask layer (e.g., the patterned mask layer 402 of
At block 706, a deep/adjusted well (e.g., the adjusted bottom well 204 of
The patterned mask layer and the opening 404 can be formed such that the resulting adjusted well depression 260 extends for the adjusted separation distance 276 of
At block 708, an oxide layer (e.g., corresponding to the gate oxide 214) can be formed on/over the semiconductor substrate using or according to the patterned mask layer. For example, the oxide layer 502 of
At block 710, the patterned mask layer can be removed, such as by chemical/mechanical etching. The removal of the patterned mask layer can correspond to a portion of the phase 600 of
At block 712, complementary wells (e.g., the complementary wells 206 of
The implanting process can form the complementary wells that directly connect to the deep well or the implant portion 208 that connect the complementary wells to the deep well. Accordingly, the method 700 can include connecting the deep and complementary wells as illustrated at block 714. For example, the complementary wells and/or the implant portion 208 can have a length/height that is equal to or greater than the first depth 272. Accordingly, given the overlap, the complementary wells can be connected to the deep well.
Connecting the wells can correspond to or include forming an isolated well (e.g., the isolated well 210 of
At block 718, the method 700 can include forming a gate portion (e.g., the gate portion 212) over the semiconductor substrate and between the complementary wells. The gate portion 212 can be formed on/over the gate oxide 214. The gate portion 212 can be configured to provide controls for the current flow between the terminals. The gate portion 212 can correspond to the gate interface width 218 that is less than the adjusted width 262 of the adjusted well depression 260. The gate portion 212 can be located at the above described location such that the second depth 274 is maintained for the adjusted separation distance 276 along a lateral direction from its peripheral edges.
This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein, and the invention is not limited except as by the appended claims.
Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms “comprising,” “including,” and “having” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “an embodiment,” “some embodiments” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.
