Patent Application
20080307208
The present invention relates to application specific processors, and in particular, to an application specific processor adapted to switch between multiple contexts for performing various tasks.
Application specific processors (ASPs) are often employed in hard disk controllers (HDC) of data storage systems for performing specific tasks such as controlling a buffer or a disk formatter, for example. The ASPs may also enable transmission of data to and from a host device connected to the HDC. Typically, one ASP is provided for operating a particular application. For example, some host devices have redundant ports for transmitting and receiving data to and from the HDC. Each of these ports will have an ASP for transmitting data and another ASP for receiving data (see
Using one dedicated ASP for each application or task, at times, is disadvantageous. This is because the ASPs normally operate so fast that they often start a task and sit idle while waiting for the task to be completed. As such, the ASPs are under utilized, which unnecessarily increases the cost of the final system.
The present invention is directed to an application specific processor for executing multiple dedicated applications in a system having a main control processor for controlling the operation of the system. The application specific processor includes a first context for executing a corresponding first application and a second context for executing a corresponding second application. An instruction memory outputs instructions for executing the first and second applications, and a context switch instruction for switching from one context to the other context. Context is switched in response to the context switch instruction while executing the first or second application.
Turning to
It should be understood that while the ASP 10 of the present invention is described herein with respect to a data storage system, its use is not confined or limited to this environment. The ASP 10 of the present invention can be used in any environment, such as a network processor or a USB hub, for example, where two or more dedicated applications or tasks can be operated by a single ASP.
Referring to
The first context 20 includes a memory 26 for storage of permanent and temporary variables used in the operation associated with the first context, a number of registers 28 for configuration and control and a program counter 30 used to address or track instructions in the instruction RAM 24. The second context 22 also includes a memory 32, a number of registers 34 and a program counter 36, which perform the same functions as the components of the first context 20, but with respect the application corresponding to the second context 22. The memories 26 and 32 are preferably in the form of a RAM.
The instruction RAM 24 includes instruction sequences for enabling the contexts 20, 22 to carry out their intended functions. In the embodiment in which the ASPs 10 perform data transmission for ports 0 and 1, as shown in
It should be understood that while the registers 28 and 34 are shown as physically residing in the ASP 10, they may be located remotely outside the ASP. For example, if the ASPs 10 are provided in the HIF 14, as in the embodiment shown in
In
As in the embodiment of the ASP 10 having two contexts 20, 22, the four registers of the contexts 1-4 may be located remotely outside the ASP, and the memories of the contexts 1-4 may be provided on a single RAM which is divided into four parts, thereby saving space on the chip on which the ASP is fabricated.
Turning now to
The next context (which becomes the current context) then begins executing instructions associated with the corresponding application (block 46) until a context switch instruction is encountered by this context during a polling or idle loop, or times of inactivity or while waiting for an event to occur during the operation of the application (block 48). This causes the ASP 10 to switch to the next context indicated in the context switch instruction (block 50), which may or may not be the same first context in which the ASP 10 began the initial operation.
If the next context is the same as the one in which the ASP 10 began its operation, it then resumes executing instructions associated with the first application from where it left off when it previously encountered the context switch instruction (block 40). If not, the next current context will begin executing instructions associated with its corresponding application (block 40) until a context switch instruction is encountered during a polling or idle loop, or times of inactivity or while waiting for an event to occur during the operation of the application (block 42), and the process repeats as described above.
Moreover, the case where the ASP 10 is employed to switch context between the same type of application (for example, redundant ports to transmit or receive data), the instruction sequence stored in the instruction RAM 24 may be identical, and the pointers from the program counters may be pointing to the same place in the instruction RAM 24. If however, the contexts are configured to operate different applications, the pointers in the program counters would start at different locations in the instruction RAM 24.
The embodiments and examples set forth herein were presented in order to best explain the present invention and its practical application and to thereby enable those skilled in the art to make and use the invention. Those skilled in the art will recognize that the foregoing description and examples have been presented for the purposes of illustration and example only. The description as set forth is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching without departing from the spirit and scope of the forthcoming claims.
Various features of the invention are set forth in the appended claims.
