Patent Application
20160078939
Nonvolatile memory devices such as NAND flash modules come in a variety of standard form factors having standard connectors and connector pins. As more and more storage is provided for a NAND flash module, designers have considered stacking the NAND cells to allow for greater storage capacities without increasing the footprint of the resulting memory array. Such greater sized memory arrays contain an increasing number of NAND structures formed on dies within a given target or volume. With the increasing number of dice in a memory array, each die is mapped into the volume or target through pads bonding which results in the need to add more pads a the die level and more pins at the package level in order to increase stacking parallelism. With such arrangements, volumes may be coupled together, but there is no way to appoint individual dice across multiple volumes, and initialization is only able to be performed at the target level.
Claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, such subject matter may be understood by reference to the following detailed description when read with the accompanying drawings in which:
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
In the following detailed description, numerous specific details are set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components and/or circuits have not been described in detail.
In the following description and/or claims, the terms coupled and/or connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical and/or electrical contact with each other. Coupled may mean that two or more elements are in direct physical and/or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate and/or interact with each other. For example, “coupled” may mean that two or more elements do not contact each other but are indirectly joined together via another element or intermediate elements. Finally, the terms “on,” “overlying,” and “over” may be used in the following description and claims. “On,” “overlying,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. However, “over” may also mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is above another element but not contact each other and may have another element or elements in between the two elements. Furthermore, the term “and/or” may mean “and”, it may mean “or”, it may mean “exclusive-or”, it may mean “one”, it may mean “some, but not all”, it may mean “neither”, and/or it may mean “both”, although the scope of claimed subject matter is not limited in this respect. In the following description and/or claims, the terms “comprise” and “include,” along with their derivatives, may be used and are intended as synonyms for each other.
Referring now to
In one or more embodiments, processor 112 may be coupled to memory device 110 with control lines and data lines via host interface 118. In some embodiments data and control may utilize the same lines, and the scope of the claimed subject matter is not limited in this respect. Processor 112 may be an external microprocessor, microcontroller, or some other type of external controlling circuitry. In some embodiments, processor 112 may be integrated in the same package or on the same die as the memory device 110. In some embodiments, processor 112 may be integrated with control logic 120, allowing some of the same circuitry to be used for both functions. Processor 112 may have external memory, such as RAM and/or ROM, used for program storage and/or intermediate data, and/or processor 112 may have internal RAM or ROM. In some embodiments, processor 112 may use memory device 110 for program and/or data storage. A program running on processor 112 may implement various functions including, but not limited to, a standard file system, a flash file system, write leveling, bad cell or block mapping, network communication stacks, and/or error management, and the scope of the claimed subject matter is not limited in these respects.
In some embodiments, processor 112 may communicate to external devices from which processor 112 may receive write commands and write data and store the write data in memory device 110. Processor 112 may also receive read commands from the external devices, retrieve read data from memory device 110, and send the read data to the external devices. In one embodiment wherein the electronic system 100 comprises a storage system, an external device may be provided with non-volatile storage via electronic device 100. Electronic device 100 may be a solid-state drive (SSD), a Universal Serial Bus (USB) thumb drive, or any other type of storage system. In some embodiments, processor 112 may connect to a computer or other intelligent device such as a cellular telephone, smart phone, tablet, digital camera, or the like, using a standard or a proprietary communication protocol Examples of computer communication protocols that the external connection may be compatible with include, but are not limited to, any version of the following protocols: Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Small Computer System Interconnect (SCSI), Fibre Channel, Parallel Advanced Technology Attachment (PATA), Integrated Drive Electronics (IDE), Ethernet, IEEE-1394, Secure Digital Card interface (SD Card), Compact Flash interface, Memory Stick interface, Peripheral Component Interconnect (PCI) or PCI Express. These are merely example types of communication protocols that may be utilized by electronic device 100, and the scope of the claimed subject matter is not limited in these respects.
In one or more embodiments, electronic system 100 may comprise a computing system or information handling system, such as a mobile telephone, a tablet, a notebook computer, a set-top box, or some other type of computing system, the external connection 402 may be a network connection such as, but not limited to, any version of the following protocols: Institute of Electrical and Electronic Engineers (IEEE) 802.3, IEEE 802.11, Data Over Cable Service Interface Specification (DOCSIS), digital television standards such as Digital Video Broadcasting (DVB)—Terrestrial, DVB-Cable, and Advanced Television Committee Standard (ATSC), and mobile telephone communication protocols such as Global System for Mobile Communication (GSM), protocols based on code division multiple access (CDMA) such as CDMA2000, Long Term Evolution (LTE), or Third Generation Partnership Project (3GPP). These are merely example types of communication protocols and/or standards that may be utilized by electronic device 100, and the scope of the claimed subject matter is not limited in these respects.
In one or more embodiments, memory device 110 includes a memory array 116 comprising an array of semiconductor dice having memory circuits stored therein and stacked in an arrangement as shown in and described with respect to
Memory device 110 may read data in memory array 116 by sensing voltage or current changes in memory array columns using sense amplifier circuitry. The sense amplifier circuitry, in one embodiment, may be coupled to read and latch a row of data from memory array 116 and communicate with read buffer 128 which may hold data read from memory array 116 until data can be sent out through data lines. Write buffer 126 may be utilized in some embodiments to accumulate data until a write can be performed and the data communicated to memory array 116. I/O circuit 124 routes the data through I/O pins of memory device 116. In some embodiments, write buffer 126 and/or read buffer 128 may be included on memory array 116.
In one or more embodiments, control logic 120 may decode commands provided on control lines from processor 112. These commands are used to control the operations on memory array 116, including data read, data write (program), and/or erase operations. Control logic 120 may comprise a state machine, a sequencer, a processor, or some other type of control logic to generate the voltage waveforms necessary to control memory array 116. Control logic 120 communicates with the other blocks in memory device 110 but those connections may not be shown. Control logic 120 may have numerous interconnections with the other blocks of memory device 110 in order to control their respective functions. The memory circuits of memory array 116 may be arranged in a stacking configuration and connected together in an arrangement that is conducive to stacking as shown in and described with respect to
Referring now to
In one or more embodiments, the targets and the dice within the targets are arranged in a daisy chain configuration as shown wherein each of the targets are connected in a daisy chain such that an output 232 of one target is coupled to an input 230 of the next target. Likewise, each of the dice within a target are connected in a daisy chain such that an output (OUT) of one die is coupled to an input (IN) of the next die within the target as shown. Such an arrangement of the targets and the dice may allow for a flexible method to access the dice within a given target, and a mechanism to appoint the dice within the target or volume, to allow a new command or a new feature or sub-feature to configure the dice. As a result, stacking parallelism may be increased without the need to add more pads at die level and/or more pins at the package level. The arrangement shown in
Referring now to
Referring now to
Appoint a first target (Target 0) 210 and LUN0,1,2,3 within Target 0:
Appoint a second target (Target 1) and LUN0,1,2,3 within Target 1:
Although the claimed subject matter has been described with a certain degree of particularity, it should be recognized that elements thereof may be altered by persons skilled in the art without departing from the spirit and/or scope of claimed subject matter. It is believed that the subject matter pertaining to appointing semiconductor dice to enable high stacking capability and many of its attendant utilities will be understood by the forgoing description, and it will be apparent that various changes may be made in the form, construction and/or arrangement of the components thereof without departing from the scope and/or spirit of the claimed subject matter or without sacrificing all of its material advantages, the form herein before described being merely an explanatory embodiment thereof, and/or further without providing substantial change thereto. It is the intention of the claims to encompass and/or include such changes.
