Patent Application
20150294694
1. Field
The present disclosure relates generally to a layout construction, and more particularly, to an area efficient layout with partial transistors.
2. Background
A bit cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of bit cells. Reducing a size/area footprint of ASICs is beneficial. Accordingly, there is a need for reducing the size/area footprint of bit cells.
In an aspect of the disclosure, a complementary metal oxide semiconductor (CMOS) apparatus includes a first transistor having a first transistor gate, a second transistor having a second transistor gate, and a partial transistor having a gate and only one of a drain or a source. The CMOS apparatus further includes a gate interconnect connecting the first transistor gate to the second transistor gate through the gate of the partial transistor. The apparatus may be a bit cell. A write word enable line may include the gate interconnect, and the first and second transistors may enable write bit lines to the bit cell. The CMOS apparatus may further include a first inverter having a first inverter output and a first inverter input, and a second inverter having a second inverter input and a second inverter output. The first inverter output may be connected to the second inverter input. The first inverter input may be connected to the second inverter output. The first inverter output and the second inverter input may be connected to the one of the drain or the source of the partial transistor.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.
As shown in
In an exemplary layout of the CMOS apparatus, in order to reduce routing within the bit cell and a size/area footprint of the bit cell, the gates of the transistors 102 and 114 may be connected together through the gate interconnect 130 via the gate 122′ without the cuts 144 in the gate interconnect 130, which also forms the gates of the transistors 102 and 114 and the partial transistor 122. Connecting the gates of the transistors 102 and 114 together through the gate interconnect 130 via the gate 122′ of the partial transistor 122 introduces a coupling capacitance to the gate interconnect 130. The coupling capacitance slows down signals on the gate interconnect 130. However, in some applications the introduction of such coupling capacitance may be tolerated.
Referring again to
When the first write word enable line 252 is enabled (with a high voltage), the first write bit line 254 inputs a bit (0 or 1) to the second inverter 272 and the first write inverted bit line 256 inputs the inverted bit to the first inverter 270. The first and second inverters 270, 272 store the inputted bit. Similarly, when the second write word enable line 262 is enabled (with a high voltage), the second write bit line 264 inputs a bit (0 or 1) to the second inverter 272 and the second write inverted bit line 266 inputs the inverted bit to the first inverter 270. The first and second inverters 270, 272 store the inputted bit.
Referring again to
The CMOS apparatus further includes transistors 304, 306, 308, 312, 316, 318, and 320. The transistors 304, 306, 308, 316, 318, and 320 may be nMOS transistors and the transistor 312 may be a pMOS transistor. The transistors 304, 306, 308, 312, 316, 318, and 320 have gates 304′, 306′, 308′, 312′, 316′, 318′, and 320′, respectively. The nMOS transistor 306 may be biased off (e.g., by connecting Vss to the gate 306′ of the transistor 306) in order to isolate the nMOS transistors 304 and 308 from each other. In addition, the nMOS transistor 316 may be biased off (e.g., by connecting Vss to the gate 316′ of the transistor 316) in order to isolate the nMOS transistors 314 and 318 from each other. Gate interconnects 334 and 336 extend (vertically as illustrated) across the bit cell. An active region 342 of the transistor 312 extends under the gate interconnect 336. In particular, a drain 348′ of the transistor 312 extends under the gate interconnect 336. A partial transistor 324 (also referred to as a “half transistor”) is formed where the active region 342 of the transistor 312 extends under the gate interconnect 336. The partial transistor 324 has only one of a drain or a source 348. (The p-type region 348 adjacent the gate 324′ of the partial transistor 324 may be considered a drain or a source.) The drain/source 348 of the partial transistor 324 is the same region as the drain 348′ of the transistor 312. The gates 308′ and 320′ of the transistors 308 and 320, respectively, are connected together via the gate 324′ through the gate interconnect 336, which also forms the gates of the transistors 308 and 320 and the partial transistor 324. Accordingly, the gates 308′ and 320′ are connected to the gate 324′ of the partial transistor 324 by the gate interconnect 336. As discussed supra, connecting the transistors 308 and 320 together through the gate interconnect 336 via the gate 324′ of the partial transistor 324 introduces a coupling capacitance to the gate interconnect 336 (which slows down signals on the gate interconnect 336), but in some applications the coupling capacitance may be tolerated.
When the first write word enable line 352 is enabled (with a high voltage), the first write bit line 354 inputs a bit (0 or 1) to the second inverter 372 and the first write inverted bit line 356 inputs the inverted bit to the first inverter 370. The first and second inverters 370, 372 store the inputted bit. Similarly, when the second write word enable line 362 is enabled (with a high voltage), the second write bit line 364 inputs a bit (0 or 1) to the second inverter 372 and the second write inverted bit line 366 inputs the inverted bit to the first inverter 370. The first and second inverters 370, 372 store the inputted bit. The partial transistors 322, 324 introduce a coupling capacitance to the gate interconnects 330, 336, respectively. However, the negative effects of the coupling capacitance may be tolerated within the illustrated multiport bit cell in order to obtain the benefits of reduced routing within the bit cell and a reduced size/area footprint of the bit cell as a result of the reduced routing.
Referring again to
The apparatus may further include a first inverter 370 having a first inverter output (node A) and a first inverter input (node B). The apparatus may further include a second inverter 372 having a second inverter input (node A) and a second inverter output (node B). The first inverter output (node A) may be connected to the second inverter input (node A). The first inverter input (node B) may be connected to the second inverter output (node B). The first inverter output (node A) and the second inverter input (node A) may be connected to the drain/source 346 of the partial transistor 322.
In one configuration, the first inverter 370 includes a third transistor 310 and a fourth transistor 304. The third transistor 310 has a third transistor gate 310′, a third transistor drain 346′, and a third transistor source. The fourth transistor 304 has a fourth transistor gate 304′, a fourth transistor drain, and a fourth transistor source. The third transistor gate 310′ is connected to the fourth transistor gate 304′. The third transistor drain 346′ is connected to the fourth transistor drain. The first inverter input (node B) is at the third transistor gate 310′ and the fourth transistor gate 304′. The first inverter output (node A) is at the third transistor drain 346′ and the fourth transistor drain. The third transistor drain 346′ is the drain/source 346 of the partial transistor 322.
In one configuration, the third transistor 310 is a pMOS transistor, the fourth transistor 304 is an nMOS transistor, and the drain/source 346 of the partial transistor 322 is a p-type region. In one configuration, the apparatus further includes a fifth transistor 308 having a fifth transistor gate 308′, a sixth transistor 320 having a sixth transistor gate 320′, and a second partial transistor 324 having a gate 324′ and only one of a drain or a source 348. The apparatus further includes a second gate interconnect 336 connecting the fifth transistor gate 308′ to the sixth transistor gate 320′ through the gate 324′ of the second partial transistor 324. The apparatus may be a bit cell. A write word enable line 362 or a portion of the write word enable line 362 may be the second gate interconnect 336. Accordingly, the write word enable line 362 may include the second gate interconnect 336. The fifth and sixth transistors 308, 320 may enable write bit lines 364 and 366, respectively, to the bit cell. The first inverter input (node B) and the second inverter output (node B) may be connected to the drain/source 348 of the second partial transistor 324.
In one configuration, the second inverter 372 includes a seventh transistor 312 and an eighth transistor 318. The seventh transistor 312 has a seventh transistor gate 312′, a seventh transistor drain 348′, and a seventh transistor source. The eighth transistor 318 has an eighth transistor gate 318′, an eighth transistor drain, and an eighth transistor source. The seventh transistor gate 312′ is connected to the eighth transistor gate 318′. The seventh transistor drain 348′ is connected to the eighth transistor drain. The third transistor source is coupled to the seventh transistor source, both of which may be coupled to Vdd. The fourth transistor source is coupled to the eighth transistor source, both of which may be coupled to Vss. The second inverter input (node A) is at the seventh transistor gate 312′ and the eighth transistor gate 318′. The second inverter output (node B) is at the seventh transistor drain 348′ and the eighth transistor drain. The seventh transistor drain 348′ is the drain/source 348 of the second partial transistor 324. In one configuration, the seventh transistor 312 is a pMOS transistor, the eighth transistor 318 is an nMOS transistor, and the drain/source 348 of the second partial transistor 324 is a p-type region.
In one configuration, the apparatus is a bit cell, a write word enable line includes the gate interconnect, and the first and second transistors enable write bit lines to the bit cell when the first and second transistors are turned on. In one configuration, the apparatus includes a first inverter and a second inverter. The first inverter has a first inverter output and a first inverter input. The second inverter has a second inverter input and a second inverter output. The first inverter output is connected to the second inverter input. The first inverter input is connected to the second inverter output. The first inverter output and the second inverter input are connected to the one of the drain or the source of the partial transistor. In one configuration, the first inverter includes a third transistor and a fourth transistor; the third transistor has a third transistor gate, a third transistor drain, and a third transistor source; the fourth transistor has a fourth transistor gate, a fourth transistor drain, and a fourth transistor source; the third transistor gate is connected to the fourth transistor gate; the third transistor drain is connected to the fourth transistor drain; the first inverter input is at the third transistor gate and the fourth transistor gate; the first inverter output is at the third transistor drain and the fourth transistor drain; and the third transistor drain is the one of the drain or the source of the partial transistor. In one configuration, the third transistor is a pMOS transistor, the fourth transistor is an nMOS transistor, and the one of the drain or the source of the partial transistor is a p-type region.
In one configuration, a CMOS apparatus includes means for applying a voltage through a gate interconnect to a first transistor, a second transistor, and a partial transistor. The apparatus further includes means for turning on the first transistor and the second transistor through the gate interconnect based on the applied voltage. The first transistor has a first transistor gate. The second transistor has a second transistor gate. The gate interconnect connects the first transistor gate to the second transistor gate through a gate of the partial transistor. The partial transistor has said gate and only one of a drain or a source. The voltage is applied to the gate of the partial transistor through the gate interconnect. The means for applying a voltage through a gate interconnect to a first transistor, a second transistor, and a partial transistor includes the gate interconnect that connects gates of the first transistor, second transistor, and partial transistor together. The means for applying a voltage through a gate interconnect to a first transistor, a second transistor, and a partial transistor further includes the first transistor, the second transistor, and the partial transistor. The means for turning on the first transistor and the second transistor through the gate interconnect based on the applied voltage includes the gate interconnect, the first transistor, and the second transistor. As discussed supra, the first transistor has a first transistor gate, the second transistor has a second transistor gate, and the partial transistor has a gate and only one of a drain or a source. The gate interconnect connects the first transistor gate to the second transistor gate through the gate of the partial transistor.
As provided supra, a gate interconnect may extend to connect and to form the gates of two transistors and a partial transistor. The partial transistor introduces a coupling capacitance in the path for turning on the two transistors. However, the negative effects of the coupling capacitance may be tolerated in some applications, such as for example, in the write word enable lines of the provided multiport bit cell, in order to obtain benefits of reduced routing and a reduced size/area footprint.
It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.” Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
