Input/output (I/0) data interface arrangements

Industry

CPC
G11C7/10

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/10Input/output (I/0) data interface arrangements

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Multi-protocol analog front end circuit
- Patent number 12,249,394
- Issue date Mar 11, 2025
- Synopsys, Inc.
- G11 - INFORMATION STORAGE
Information Patent Grant
Folding ordering scheme for improved throughput in non-volatile memory
- Patent number 12,249,396
- Issue date Mar 11, 2025
- SanDisk Technologies, Inc.
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic way-based variable pipeline architecture for on-chip memory
- Patent number 12,249,400
- Issue date Mar 11, 2025
- ARM Limited
- G11 - INFORMATION STORAGE
Information Patent Grant
Superconducting distributed bidirectional current driver system
- Patent number 12,249,393
- Issue date Mar 11, 2025
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory, memory system and operation method of memory system
- Patent number 12,249,386
- Issue date Mar 11, 2025
- SK Hynix Inc.
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for calibrating adjustable impedances of a...
- Patent number 12,249,969
- Issue date Mar 11, 2025
- G11 - INFORMATION STORAGE
Information Patent Grant
System on chip for reducing wake-up time, method of operating same,...
- Patent number 12,248,355
- Issue date Mar 11, 2025
- Samsung Electronics Co., Ltd.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for organizing data in a memory device
- Patent number 12,249,377
- Issue date Mar 11, 2025
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with staggered request signal output
- Patent number 12,249,392
- Issue date Mar 11, 2025
- RAMBUS INC.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device supporting in-memory MAC operation between ternary in...
- Patent number 12,249,395
- Issue date Mar 11, 2025
- Korea University Research and Business Foundation
- G11 - INFORMATION STORAGE
Information Patent Grant
Single ended sense amplifier with current pulse circuit
- Patent number 12,243,614
- Issue date Mar 4, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Siva Kumar Chinthu
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibration circuit and method with reference voltage generator and...
- Patent number 12,243,615
- Issue date Mar 4, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Siman Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for supporting stable data transfer and memory system...
- Patent number 12,243,616
- Issue date Mar 4, 2025
- SK hynix Inc.
- Hyeon Uk Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device including nonvolatile memory device and controller,...
- Patent number 12,242,761
- Issue date Mar 4, 2025
- Samsung Electronics Co., Ltd.
- Jesuk Yeon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One time programmable memory
- Patent number 12,243,592
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Der Chih
- G11 - INFORMATION STORAGE
Information Patent Grant
Indicating a status of a memory built-in self-test
- Patent number 12,243,607
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with parallel main and test interfaces
- Patent number 12,243,610
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Loopback circuit for low-power memory devices
- Patent number 12,243,617
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yoshihito Morishita
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer control of multiple memory banks
- Patent number 12,243,621
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shih-Lien Linus Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Impedance calibration circuit and method
- Patent number 12,244,282
- Issue date Mar 4, 2025
- M31 Technology Corporation
- Ming-Yen Tsai
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reading memory
- Patent number 12,243,586
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yuhsiang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of manufacturing semiconductor device
- Patent number 12,243,618
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array structure
- Patent number 12,243,619
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hung-Li Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Output driver level-shifting latch circuit for dual-rail memory
- Patent number 12,243,581
- Issue date Mar 4, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Impedance calibration circuit, memory controller including the impe...
- Patent number 12,237,044
- Issue date Feb 25, 2025
- SK hynix Inc.
- In Soo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus having selectively-activated termination circuitry
- Patent number 12,235,760
- Issue date Feb 25, 2025
- Lodestar Licensing Group LLC
- Terry Grunzke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device ID setting method and electronic device applying the device...
- Patent number 12,237,039
- Issue date Feb 25, 2025
- PixArt Imaging Inc.
- En-Feng Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, memory system having the same, and method of operati...
- Patent number 12,237,048
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Hijung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Compute-in-memory macro device and electronic device
- Patent number 12,236,332
- Issue date Feb 25, 2025
- Novatek Microelectronics Corp.
- Chien Te Tung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level signaling in memory with wide system interface
- Patent number 12,237,953
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Timothy M. Hollis
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE
- Publication number 20250078885
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- He-Zhou WAN
- G11 - INFORMATION STORAGE
Information Patent Application
EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA
- Publication number 20250078886
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Patrick Michael Sheridan
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR INITIALIZING MEMORY ERROR CORRECTION
- Publication number 20250078948
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ZQ CALIBRATION OF MEMORY INTERFACE DRIVING...
- Publication number 20250078880
- Publication date Mar 6, 2025
- ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Min Hyung CHO
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR OPERATING IN-MEMORY COMPUTING ARCHITECTURE...
- Publication number 20250078881
- Publication date Mar 6, 2025
- PEKING UNIVERSITY
- Peng HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN SITU DELAY MEASUREMENTS ON INTEGRATED CIRCUITS USING LIVE DATA A...
- Publication number 20250078882
- Publication date Mar 6, 2025
- Synopsys, Inc.
- Karen Darbinyan
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SY...
- Publication number 20250078888
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS
- Publication number 20250077754
- Publication date Mar 6, 2025
- iCometrue Company Ltd.
- Mou-Shiung LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
- Publication number 20250078878
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Sheng WANG
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
- Publication number 20250078879
- Publication date Mar 6, 2025
- SK HYNIX INC.
- In Seok KONG
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A...
- Publication number 20250078884
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Sujeet V. Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20250078883
- Publication date Mar 6, 2025
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGEMENT OF DATA TRANSFER FOR NETWORK OPERATION
- Publication number 20250071037
- Publication date Feb 27, 2025
- Intel Corporation
- Daniel Biederman
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESSING IN MEMORY REGISTERS
- Publication number 20250069629
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Dmitri Yudanov
- G11 - INFORMATION STORAGE
Information Patent Application
DATA ALIGNMENT FOR MEMORY
- Publication number 20250069631
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Martin Bach
- G11 - INFORMATION STORAGE
Information Patent Application
CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALING
- Publication number 20250069632
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Leon Zlotnik
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Usage Configurations for Integrated Circuit Devices having A...
- Publication number 20250071445
- Publication date Feb 27, 2025
- Micron Technology, Inc.
- Poorna Kale
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE CONFIGURED TO STORE PARITY DATA AND METHOD OF...
- Publication number 20250069628
- Publication date Feb 27, 2025
- SK HYNIX INC.
- Byoung Sung YOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20250069644
- Publication date Feb 27, 2025
- Rambus Inc.
- Jared L. ZERBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Truncated Resolution for Time Sliced Computation of Multiplication...
- Publication number 20250061930
- Publication date Feb 20, 2025
- Micron Technology, Inc.
- Hernan Castro
- G11 - INFORMATION STORAGE
Information Patent Application
OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD
- Publication number 20250061928
- Publication date Feb 20, 2025
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Controlling Power Management Operations in...
- Publication number 20250061929
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WRITE SCHEME FOR MEMORY DEVICES
- Publication number 20250061926
- Publication date Feb 20, 2025
- Xilinx, Inc.
- Santosh YACHARENI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY
- Publication number 20250061927
- Publication date Feb 20, 2025
- CXMT CORPORATION
- Jia WANG
- G11 - INFORMATION STORAGE
Information Patent Application
ONE-TIME PROGRAMMABLE MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE...
- Publication number 20250054558
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Yeongmuk Cho
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO
- Publication number 20250054525
- Publication date Feb 13, 2025
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS
- Publication number 20250054860
- Publication date Feb 13, 2025
- iCometrue Company Ltd.
- Jin-Yuan Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE, AND OPERATION METHOD OF I...
- Publication number 20250055459
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Moon-Chul Choi
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
- Publication number 20250054526
- Publication date Feb 13, 2025
- SK HYNIX INC.
- Chan Keun KWON
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES
- Publication number 20250054563
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Sehwan Park
- G11 - INFORMATION STORAGE

Input/output (I/0) data interface arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multi-protocol analog front end circuit

Folding ordering scheme for improved throughput in non-volatile memory

Dynamic way-based variable pipeline architecture for on-chip memory

Superconducting distributed bidirectional current driver system

Memory, memory system and operation method of memory system

Apparatuses and methods for calibrating adjustable impedances of a...

System on chip for reducing wake-up time, method of operating same,...

Apparatuses and methods for organizing data in a memory device

Memory controller with staggered request signal output

Memory device supporting in-memory MAC operation between ternary in...

Single ended sense amplifier with current pulse circuit

Calibration circuit and method with reference voltage generator and...

Memory device for supporting stable data transfer and memory system...

Storage device including nonvolatile memory device and controller,...

One time programmable memory

Indicating a status of a memory built-in self-test

Memory with parallel main and test interfaces

Loopback circuit for low-power memory devices

Buffer control of multiple memory banks

Impedance calibration circuit and method

Method for reading memory

Method of manufacturing semiconductor device

Memory array structure

Output driver level-shifting latch circuit for dual-rail memory

Impedance calibration circuit, memory controller including the impe...

Apparatus having selectively-activated termination circuitry

Device ID setting method and electronic device applying the device...

Memory device, memory system having the same, and method of operati...

Compute-in-memory macro device and electronic device

Multi-level signaling in memory with wide system interface

Patents Applicationslast 30 patents

MEMORY DEVICE

EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA

TECHNIQUES FOR INITIALIZING MEMORY ERROR CORRECTION

METHOD AND APPARATUS FOR ZQ CALIBRATION OF MEMORY INTERFACE DRIVING...

METHOD AND APPARATUS FOR OPERATING IN-MEMORY COMPUTING ARCHITECTURE...

IN SITU DELAY MEASUREMENTS ON INTEGRATED CIRCUITS USING LIVE DATA A...

MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SY...

LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS

MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A...

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

MANAGEMENT OF DATA TRANSFER FOR NETWORK OPERATION

PROCESSING IN MEMORY REGISTERS

DATA ALIGNMENT FOR MEMORY

CRITICAL TIMING DRIVEN ADAPTIVE VOLTAGE FREQUENCY SCALING

Memory Usage Configurations for Integrated Circuit Devices having A...

SEMICONDUCTOR DEVICE CONFIGURED TO STORE PARITY DATA AND METHOD OF...

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

Truncated Resolution for Time Sliced Computation of Multiplication...

OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD

Systems and Methods for Controlling Power Management Operations in...

ADAPTIVE WRITE SCHEME FOR MEMORY DEVICES

MEMORY

ONE-TIME PROGRAMMABLE MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE...

MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO

VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS

MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE, AND OPERATION METHOD OF I...

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

GENERATION OF SOFT DECISION DATA FOR MEMORY DEVICES