Input/output (I/0) data interface arrangements

Industry

CPC
G11C7/10

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/10Input/output (I/0) data interface arrangements

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Test circuit and receiving circuit having test function
- Patent number 12,288,589
- Issue date Apr 29, 2025
- SK hynix Inc.
- Gi Moon Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage devices and methods of operating storage devices
- Patent number 12,288,590
- Issue date Apr 29, 2025
- Samsung Electronics Co., Ltd.
- Eun Chu Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage device and non-volatile memory control method
- Patent number 12,287,988
- Issue date Apr 29, 2025
- Silicon Motion, Inc.
- Hsu-Ping Ou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor system
- Patent number 12,287,743
- Issue date Apr 29, 2025
- Samsung Electronics Co., Ltd.
- Hyun Jun Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and operating method for target refresh operation bas...
- Patent number 12,288,580
- Issue date Apr 29, 2025
- SK Hynix Inc.
- Woongrae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
IMS memory cell, IMS method and IMS memory device
- Patent number 12,283,343
- Issue date Apr 22, 2025
- Macronix International Co., Ltd.
- Yun-Yuan Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device with buffered operation engine and method for per...
- Patent number 12,283,344
- Issue date Apr 22, 2025
- XCENA Inc.
- Ji Hun Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Data transmission circuit and memory device
- Patent number 12,283,339
- Issue date Apr 22, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Xianjun Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for controlling sense amplifier and control device using the...
- Patent number 12,283,340
- Issue date Apr 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse generator, error check and scrub (ECS) circuit and memory
- Patent number 12,283,345
- Issue date Apr 22, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power static random access memory
- Patent number 12,283,313
- Issue date Apr 22, 2025
- UNTETHER AI CORPORATION
- Katsuyuki Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for input buffer data feedback equalization...
- Patent number 12,283,342
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Kohei Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit, signal transmission system and signal transmission...
- Patent number 12,283,302
- Issue date Apr 22, 2025
- NANYA TECHNOLOGY CORPORATION
- Shun-Ke Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Global data line of multi-array synchronous random access memory (S...
- Patent number 12,283,338
- Issue date Apr 22, 2025
- Samsung Electronics Co., Ltd.
- Hee Choul Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic clock mask based on read data for power saving
- Patent number 12,283,341
- Issue date Apr 22, 2025
- SanDisk Technologies LLC
- Tianyu Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer circuit and memory device including the same
- Patent number 12,277,995
- Issue date Apr 15, 2025
- Samsung Electronics Co., Ltd.
- Jin-Young Chun
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reset voltage control
- Patent number 12,277,991
- Issue date Apr 15, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ali Taghvaei
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay circuit and memory
- Patent number 12,278,629
- Issue date Apr 15, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Tianchen Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Auto-referenced memory cell read techniques
- Patent number 12,277,969
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Graziano Mirichigni
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory
- Patent number 12,277,994
- Issue date Apr 15, 2025
- Rohm Co., Ltd.
- Seiji Takenaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and ZQ calibration method
- Patent number 12,277,992
- Issue date Apr 15, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kai Tian
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer circuits in three-dimensional memory devices
- Patent number 12,277,993
- Issue date Apr 15, 2025
- Yangtze Memory Technologies Co., Ltd.
- Teng Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,277,990
- Issue date Apr 15, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Meng-Sheng Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor devices
- Patent number 12,271,263
- Issue date Apr 8, 2025
- SK hynix Inc.
- Sang Sic Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Series of parallel sensing operations for multi-level cells
- Patent number 12,272,420
- Issue date Apr 8, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Qing Dong
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensation for conductance drift in analog memory in crossbar array
- Patent number 12,272,422
- Issue date Apr 8, 2025
- International Business Machines Corporation
- Charles Mackin
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of operating a near memory processing-dual in-line memory m...
- Patent number 12,272,423
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Sachin Suresh Upadhya
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing spurious write operations in a memory device
- Patent number 12,272,424
- Issue date Apr 8, 2025
- Synopsys, Inc.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller performing training to improve communication and...
- Patent number 12,272,425
- Issue date Apr 8, 2025
- SK Hynix Inc.
- Nam Hyeok Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 12,272,416
- Issue date Apr 8, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SHARED DECODER CIRCUIT AND METHOD
- Publication number 20250140294
- Publication date May 1, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- XiuLi YANG
- G11 - INFORMATION STORAGE
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD
- Publication number 20250139026
- Publication date May 1, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CALIBRATING ADJUSTABLE IMPEDANCES OF A...
- Publication number 20250141432
- Publication date May 1, 2025
- Lodestar Licensing Group LLC
- Dean Gans
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTING CIRCUIT
- Publication number 20250141451
- Publication date May 1, 2025
- STMicroelectronics International N.V.
- Thomas Pierre Georges Jouanneau
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED CHIP SELECT SIGNAL TRAINING
- Publication number 20250138571
- Publication date May 1, 2025
- QUALCOMM Incorporated
- Farrukh AQUIL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...
- Publication number 20250131953
- Publication date Apr 24, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE
- Publication number 20250130724
- Publication date Apr 24, 2025
- KIOXIA Corporation
- Tsuyoshi ATSUMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...
- Publication number 20250131947
- Publication date Apr 24, 2025
- TACHYUM LTD.
- Radoslav DANILAK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS
- Publication number 20250131950
- Publication date Apr 24, 2025
- Yangtze Memory Technologies Co., Ltd.
- Guangyu Bai
- G11 - INFORMATION STORAGE
Information Patent Application
THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20250124956
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing company Ltd.
- MURAT KEREM AKARVARDAR
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING DEVICE, MEMORY CONTROLLER, AND METHOD FOR PERFORMING AN I...
- Publication number 20250124958
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- YU-DER CHIH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING PIPE LATCH
- Publication number 20250124957
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Young Seung YOO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250124959
- Publication date Apr 17, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...
- Publication number 20250124997
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Katherine H. CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WOR...
- Publication number 20250123758
- Publication date Apr 17, 2025
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE...
- Publication number 20250118362
- Publication date Apr 10, 2025
- International Business Machines Corporation
- Wolfgang Penth
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR IN-NAND PATTERN SEARCH
- Publication number 20250118368
- Publication date Apr 10, 2025
- SK HYNIX INC.
- Pengfei HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CI...
- Publication number 20250118386
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Shadden Kerstetter
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DATA TRANSFERS IN SEMICONDUCTOR DEVICES
- Publication number 20250119142
- Publication date Apr 10, 2025
- Macronix International Co., Ltd.
- Yi-Fan Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
- Publication number 20250118345
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Win-San KHWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON A...
- Publication number 20250118348
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Leon Zlotnik
- G11 - INFORMATION STORAGE
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPEDANCE CALIBRATION CIRCUIT AND METHOD
- Publication number 20250119121
- Publication date Apr 10, 2025
- M31 TECHNOLOGY CORPORATION
- MING-YEN TSAI
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE
- Publication number 20250118346
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xiu-Li YANG
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NE...
- Publication number 20250117642
- Publication date Apr 10, 2025
- Taiwan Semiconductor Manufacturing Co., LTD
- Win-San KHWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME
- Publication number 20250119149
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS
- Publication number 20250118343
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES
- Publication number 20250118344
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Stephen Hanna
- G11 - INFORMATION STORAGE

Input/output (I/0) data interface arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Test circuit and receiving circuit having test function

Storage devices and methods of operating storage devices

Data storage device and non-volatile memory control method

Semiconductor system

Memory device and operating method for target refresh operation bas...

IMS memory cell, IMS method and IMS memory device

Electronic device with buffered operation engine and method for per...

Data transmission circuit and memory device

Method for controlling sense amplifier and control device using the...

Pulse generator, error check and scrub (ECS) circuit and memory

Low-power static random access memory

Apparatuses and methods for input buffer data feedback equalization...

Memory circuit, signal transmission system and signal transmission...

Global data line of multi-array synchronous random access memory (S...

Dynamic clock mask based on read data for power saving

Page buffer circuit and memory device including the same

Memory device with reset voltage control

Delay circuit and memory

Auto-referenced memory cell read techniques

Non-volatile memory

Memory device and ZQ calibration method

Page buffer circuits in three-dimensional memory devices

Memory device and method of operating the same

Semiconductor devices

Series of parallel sensing operations for multi-level cells

Compensation for conductance drift in analog memory in crossbar array

Methods of operating a near memory processing-dual in-line memory m...

Reducing spurious write operations in a memory device

Memory controller performing training to improve communication and...

ATPG testing method for latch based memories, for area reduction

Patents Applicationslast 30 patents

SHARED DECODER CIRCUIT AND METHOD

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD

APPARATUSES AND METHODS FOR CALIBRATING ADJUSTABLE IMPEDANCES OF A...

LEVEL SHIFTING CIRCUIT

ENHANCED CHIP SELECT SIGNAL TRAINING

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...

MEMORY DEVICES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

COMPUTING DEVICE, MEMORY CONTROLLER, AND METHOD FOR PERFORMING AN I...

MEMORY DEVICE INCLUDING PIPE LATCH

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...

MODULAR MEMORY ARCHITECTURE WITH MORE SIGNIFICANT BIT SUB-ARRAY WOR...

BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE...

SYSTEM AND METHOD FOR IN-NAND PATTERN SEARCH

SEMICONDUCTOR MEMORY DEVICE WITH PROCESSING-IN-MEMORY USING TEST CI...

MANAGING DATA TRANSFERS IN SEMICONDUCTOR DEVICES

MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM

CRITICAL TIMING DRIVEN DYNAMIC VOLTAGE FREQUENCY SCALING BASED ON A...

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

IMPEDANCE CALIBRATION CIRCUIT AND METHOD

SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE

METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NE...

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME

METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS

SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES