Patent Application
20080168335
1. Technical Field of the Invention
The invention relates generally to decoders; and, more particularly, it relates to decoders that are operable to decode Reed-Solomon (RS) coded signals including those that can be implemented within various hard disk drive (HDD) applications.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs iterative error correction codes. One type of communication system that has received interest in recent years has been one which employs Reed-Solomon (RS) codes (one type of iterative error correcting code). Communications systems with iterative codes are often able to achieve lower bit error rates (BER) than alternative codes for a given signal to noise ratio (SNR).
A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
There are a wide variety of applications in which RS codes can be employed to attempt to effectuate (ideally) error free transmission and receipt of information. In the context of communication systems having a communication channel over which coded signals are communicated, RS codes can be employed to attempt to effectuate (ideally) error free transmission from a communication device and/or (ideally) error free receipt of information to a communication device. In the context of hard disk drive (HDD) applications, RS codes can be employed to attempt to effectuate (ideally) error free write and/or read of information to and from storage media. With respect to HDD applications, as is known, many varieties of memory storage devices (e.g. disk drives), such as magnetic disk drives are used to provide data storage for a host device, either directly, or through a network such as a storage area network (SAN) or network attached storage (NAS). Typical host devices include stand alone computer systems such as a desktop or laptop computer, enterprise storage devices such as servers, storage arrays such as a redundant array of independent disks (RAID) arrays, storage routers, storage switches and storage directors, and other consumer devices such as video game systems and digital video recorders. These devices provide high storage capacity in a cost effective manner.
One of the operations performed in decoding a RS coded signal is the generation of an error location polynomial. Generally, prior art approaches require 3 or more banks of registers (or 3 or more memory devices) to store the various coefficients that are calculated and employed to generate this error location polynomial.
The present invention is directed to apparatus and methods of operation that are further described in the following Brief Description of the Several Views of the Drawings, the Detailed Description of the Invention, and the claims. Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.
Disk drive unit 100 further includes one or more read/write heads 104 that are coupled to arm 106 that is moved by actuator 108 over the surface of the disk 102 either by translation, rotation or both. A disk controller 130 is included for controlling the read and write operations to and from the drive, for controlling the speed of the servo motor and the motion of actuator 108, and for providing an interface to and from the host device.
Disk controller 130 further includes a processing module 132 and memory module 134. Processing module 132 can be implemented using one or more microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or any devices that manipulates signal (analog and/or digital) based on operational instructions that are stored in memory module 134. When processing module 132 is implemented with two or more devices, each device can perform the same steps, processes or functions in order to provide fault tolerance or redundancy. Alternatively, the function, steps and processes performed by processing module 132 can be split between different devices to provide greater computational speed and/or efficiency.
Memory module 134 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, and/or any device that stores digital information. Note that when the processing module 132 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory module 134 storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Further note that, the memory module 134 stores, and the processing module 132 executes, operational instructions that can correspond to one or more of the steps or a process, method and/or function illustrated herein.
Disk controller 130 includes a plurality of modules, in particular, device controllers 105, processing module 132, memory module 134, read/write channel 140, disk formatter 125, and servo formatter 120 that are interconnected via bus 136 and bus 137. The host interface 150 can be connected to only the bus 137 and communicates with the host device 50. Each of these modules can be implemented in hardware, firmware, software or a combination thereof, in accordance with the broad scope of the present invention. While a particular bus architecture is shown in
In one possible embodiment, one or more modules of disk controller 130 are implemented as part of a system on a chip (SoC) integrated circuit. In an embodiment, this SoC integrated circuit includes a digital portion that can include additional modules such as protocol converters, linear block code encoding and decoding modules, etc., and an analog portion that includes device controllers 105 and optionally additional modules, such as a power supply, etc. In a further embodiment, the various functions and features of disk controller 130 are implemented in a plurality of integrated circuit devices that communicate and combine to perform the functionality of disk controller 130.
When the drive unit 100 is manufactured, disk formatter 125 writes a plurality of servo wedges along with a corresponding plurality of servo address marks at equal radial distance along the disk 102. The servo address marks are used by the timing generator for triggering the “start time” for various events employed when accessing the media of the disk 102 through read/write heads 104.
In a possible embodiment, wireless communication device 53 is capable of communicating via a wireless telephone network such as a cellular, personal communications service (PCS), general packet radio service (GPRS), global system for mobile communications (GSM), and integrated digital enhanced network (iDEN) or other wireless communications network capable of sending and receiving telephone calls. Further, wireless communication device 53 is capable of communicating via the Internet to access email, download content, access websites, and provide steaming audio and/or video programming. In this fashion, wireless communication device 53 can place and receive telephone calls, text messages such as emails, short message service (SMS) messages, pages and other data messages that can include attachments such as documents, audio files, video files, images and other graphics.
Referring to
The signals employed within this embodiment of a communication system 400 can be Reed-Solomon (RS) coded signals. Any of a very wide variety of applications that employ RS coding can benefit from various aspects of the invention, including any of those types of communication systems depicted in
A corresponding RS encoder (not shown in this particular embodiment) takes data (e.g., a block of digital data) and adds redundancy or parity bits thereto thereby generating a codeword (e.g., a codeword to be written, transmitted, and/or launched into a communication channel). This redundancy is generated as a function of the particular RS code employed. Therefore, when the data (after undergoing RS encoding) is provided to some storage media (and/or transmitted via a communication channel and/or launched into a communication channel), and after it is read there from (or received there from), in the undesirable event that any errors occurred during either of these processes (write and/or read or transmit and/or receive), hopefully the number of errors incurred is less than the error correcting capability of the RS code. The number and types of errors that can be corrected depends on the particular characteristics of the RS code employed.
Looking at
A syndrome calculation module 510 then processes the received codeword 591 to generate syndromes 592. The operation of the syndrome calculation module 510 is analogous and similar to the calculation of the redundancy or parity bits within the RS encoding processing. As a function of the RS code employed, a RS codeword has a predetermined number of syndromes that depend only on errors (i.e., not on the actually written or transmitted codeword). The syndromes can be calculated by substituting a predetermined number of roots (as determined by the RS code) of the generator polynomial (employed within RS encoding) into the received codeword 591.
An error locator polynomial generation module 520 then receives these calculated syndromes 592. The syndromes 592 are also passed to an error magnitude calculation module 540. The error locator polynomial generation module 520 can generate the error locator polynomial 593 using various means, two of which can include the Berlekamp-Massey method 522 or Euclid method 524.
The error locator polynomial 593 is provided to an error correction module 550. The error locator polynomial 593 is also provided to an error location search module 530 that is operable to solve for the roots of the error locator polynomial 593. One approach is to employ the Chien search function 532.
Once the error locations 594 have been found within the error location search module 530 (i.e., using the Chien search function 532), then the error locations 594 are provided to the error magnitude calculation module 540 as well as to the error correction module 550. The error magnitude calculation module 540 finds the symbol error values, and it can employ a known approach such as the Forney method 542. Once the error locations 594 and the error magnitudes 595 are known, then the error correction module 550 corrects for them and outputs an estimated codeword 596.
With respect to the various processing modules depicted in this diagram as well as others, it is noted that any such processing module may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions. Any such processing module can also be coupled to a memory. Such a memory may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when such a processing module implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the, corresponding operational instructions is embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. The memory stores, and the processing module executes, operational instructions corresponding to at least some of the steps and/or functions illustrated herein. Alternatively, it is noted that such a processing module may include an embedded memory (or memories) that is operable to assist in the operations analogous to an external memory as described above.
Various embodiments of the invention include components of an error correction code (ECC) architecture that is operable to share two banks of registers. As discussed above, the prior art approaches necessitate 3 banks of registers. In certain embodiments, the number of registers in each bank is t (where t is the symbol correction capability of the RS code). For example, within the prior art, it is asserted that a 12-bit ECC with t=120 would consume approximately 500 k gates. This is supposedly for both the syndrome/symbol computer and the Reed-Solomon ECC decoder.
In accordance with various aspects of the invention, these 2 banks of registers can be employed to perform all ELP (error location polynomial) computations, EVP (error value (or magnitude) polynomial) computation, as well as the error location search operations (e.g., Chien search operations in one embodiment). This ECC Reed-Solomon ECC decoder architecture produces very efficient results with respect to silicon area consumption when compared to the prior art approaches. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Again, others within the prior art assert that a comparable ECC system would consume approximately 500 k gates.
Various embodiments of the invention employ an architecture for a Reed-Solomon ECC decoder that is very efficient with respect to silicon area and power consumption. The area savings are especially evident with large scale ECC decoder designs.
A decoder that performs the error location polynomial generation 600 can employ the Berlekamp-Massey decoding processing when decoding a RS coded signal. As can be seen, no more than a first plurality of registers 640 and a second plurality of registers 650 are required for use in storing error location polynomial coefficients that are employed during the generation of the error location polynomial. For example, the error locator polynomial generation module 620 is operable to generate the error location polynomial that is based on a discrepancy that is based on syndromes that correspond to a received codeword of a RS coded signal that is being decoded. As can also be seen, the first plurality of registers 640 includes a number of registers as depicted by register 641, register 642, . . . , and a register 643. Similarly, the second plurality of registers 650 includes a number of registers as depicted by register 651, register 652, . . . , and a register 653. In some desired embodiments, each of the first plurality of registers 640 and a second plurality of registers 650 includes a same number of registers; each has the same number of registers.
The coefficients of the error location polynomial can generally be referred to as σ. To update the error location polynomial coefficients in the generation of the error location polynomial, there are the previous error location polynomial coefficients (σp) [which can be stored in a first plurality of registers or “source” registers], the current error location polynomial coefficients (σc) [which can be stored in a second plurality of registers or “destination” registers], and the new error location polynomial coefficients (which then is the “current error location polynomial coefficients (σc)” for the next iteration, and which gets stored in the first plurality of registers or “source” registers). In using the Berlekamp-Massey processing, one of two operations is performed on the first plurality of registers or “source” registers. The first plurality of registers or “source” registers takes on one of two possible values during each iteration: [1] it retains the values of the previous error location polynomial coefficients (σp) after having undergone shifting or [2] it takes on the values of the current error location polynomial coefficients (σc) after having undergone shifting.
In both cases, the purpose for shifting the first plurality of registers or “source” registers in this Berlekamp-Massey variant is to account for the Xc-p product in the classical σc computation (e.g., where c is the iteration counter that corresponds to the current iteration, and p corresponds to the previous iteration). When using this variant of Berlekamp-Massey processing, care must be now taken to ensure that σp is only shifted after iterations with non-zero discrepancies. And, when (one or more) intermediate zero discrepancies, is discovered followed by a non-zero discrepancy, multiple shifts in σp must be performed at that time to account for the intermediate zero discrepancies that occurred.
More details of this Berlekamp-Massey variant are provided below.
Afterwards, in a decision block 708, it is determined if the previous degree (degree(p)) is greater than the current degree (degree(c)). If yes in decision block 708, then a number of registers are set. For example, the next degree (degree(next)) is set to the value of the previous degree (degree(p)) in a block 710. The previous degree (degree(p)) is set to the value of the current degree (degree(c)) in a block 712. The current degree (degree(c)) is set to the value of the next degree (degree(next)) in a block 714. In an actual implementation, the operations of the blocks 710, 712, and 714 merely can involves swapping the values of the current degree (degree(c)) with the value of the previous degree (degree(p)).
The inverse value of Δp is set to the inverse value of the discrepancy (Δc) in a block 716. The previous values of the error location polynomial coefficients (σp(x)) are set to the current values of the error location polynomial coefficients (σc(x)) in a block 718. Then, the next values of the error location polynomial coefficients (σnext(x)) are then set to the current values of the error location polynomial coefficients (σc(x)) in a block 720.
Referring back to the decision block 708: if no in decision block 708, then this variant of Berlekamp-Massey decoding processing continues directly to block 720, and then to the block 722 where the discrepancy (Δc) is computed.
This variant of Berlekamp-Massey decoding processing then continues to decision block 724 where it is determined if the current iteration is the 2Tth iteration (e.g., it is determined if this is within the correction power of the code by determining if c=2T). If no in decision block 724, then a number of other register values are updated. The previous error location polynomial coefficients (σp(x)) are set to a value of the previous error location polynomial coefficients (σp(x)) times “x” (e.g., σp(x)=x×σp(x)). The discrepancy ratio (Δc/Δp) is then computed in a block 730. The inverse of the discrepancy (Δc) (e.g., 1/Δc) is begun to be computed in a block 732 (e.g., (1/Δc)*). Then, the iteration is incremented (e.g., c=c+1) in a block 734. in memory/register use savings because of these known constant values, in that, these constant values need not be stored to perform the decoding processing.
For all other values if i, the values of the current error location polynomial coefficients (σc(i)) and the values of the previous error location polynomial coefficients (σp(i)), are all set to 0 (e.g., σc(i)=σp(i)=0). Because the initial values of the 0th iteration are known beforehand, then the current degree (degree(c)) is initially set to 1, and the discrepancy (Δc) as well as the discrepancy ratio (Δc/Δp) are both set to the value of the 0th syndrome (e.g., the least significant syndrome) that corresponds to the codeword of a received signal.
Then, in a decision block 704, it is determined if the discrepancy (Δc) is 0. If yes in decision block 704, then this variant of Berlekamp-Massey decoding processing continues to block 722 where the discrepancy (Δc) is computed. The discrepancy (Δc) is computed as follows:
Δc=Sc+Σ(σc(j)×Sj); for j≦N.
If no in decision block 704, then this variant of Berlekamp-Massey decoding processing continues to block 706 where sigma (σ) calculation is performed. The sigma (σ) value calculation can be performed as follows:
σnext(x)=σc(x)+(Δc/Δp)×σp(x).
It is noted that, in some embodiments that employ 1 or more arithmetic logic units (ALUs), those ALUs can be employed to perform the calculations in the blocks 722 and 706.
The next values of the error location polynomial coefficients (σnext(x)) are calculated using the current error location polynomial coefficients (σc(x)), the previous error location polynomial coefficients (σp(x)), and the discrepancy ratio (Δc/Δp) as follows:
σnext(x)=Δc(x)+(Δc/Δp)×σp(x).
It is noted that the previous error location polynomial coefficients (σp(x)) is in fact a working variable that includes information corresponding not only to a previous Subsequently, the previous degree is updated if needed in a block 736 (e.g., previous degree (degree(p)=degree(p)+1), and this variant of Berlekamp-Massey decoding processing continues back to the decision block 704.
Referring back to the decision block 724: if yes in decision block 724, then this variant of Berlekamp-Massey decoding processing continues to a decision block 726 where it is determined if both the discrepancy (Δc) is equal to zero and if the current degree(c) is less than or equal to T. If yes in decision block 726, then this variant of Berlekamp-Massey decoding processing determines that any errors in the RS coded signal are correctable. If no in decision block 726, then this variant of Berlekamp-Massey decoding processing determines that any errors in the RS coded signal are not correctable (e.g., uncorrectable).
From certain perspectives, it can be noted that there are three separate states that operate in accordance with this variant of Berlekamp-Massey decoding processing: a loop state, a discrepancy state, and a sigma calculation state. From this perspective, the loop state includes at least the operations in the blocks 724, 728, 730, 732, 734, and 736; the discrepancy state includes the operation in the block 722; and the sigma calculation state includes at least states 706, 708, 710, 712, 714, 716, 718, and 720.
In certain embodiments, it is also noted that operations of the blocks 706, 720 and 718 can all be performed as a single operation with the use of at least one flag and a pair of register banks (e.g., source and destination register banks).
Continuing on with RS decoding, there are numerous means by which the error values can be calculated (e.g., error magnitude calculation). One means is using the Forney approach, and another involves the approach as described in the following reference [1].
[1] R. Koetter, “On the determination of error values for codes from a class of maximal curves,” Proceedings Allerton Conference on Communication, Control, and Computing, University of Illinois at Urbana-Champaign, 1997.
During each iteration of a plurality of iterations employed to generate the error location polynomial, the error locator polynomial generation module 620 is operable to perform the following functions: retrieve a previous plurality of error location polynomial coefficients from the first plurality of registers 640, retrieve a current plurality of error location polynomial coefficients from the second plurality of registers 650, employ the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients, and store the new plurality of error location polynomial coefficients in the second plurality of registers 650. Such a decoder is operable to employ the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal.
In this embodiment, an error locator polynomial generation module 820 is operable to generate the error location polynomial, and an error location search module 830 is operable to solve for the roots of the error locator polynomial in accordance with RS decoding. The error locator polynomial generation module 820 can be coupled to a memory 821 to assist in the operations required to perform its particular functions as described above with respect to other embodiments. Similarly, the error location search module 830 can be coupled to a memory 831 to assist in the operations required to perform its particular functions as described above with respect to other embodiments. The operations of the error location search module 830 can employ the Chien search approach 832, if desired in a particular embodiment.
A decoder that performs the error location polynomial generation and error location searching 800 can employ Berlekamp-Massey processing, Euclid processing, or another means when generating the error location polynomial and can also employ a variety of means for error location searching (including Chien searching) in accordance with decoding of a RS coded signal. As can be seen, no more than a first plurality of registers 840 and a second plurality of registers 850 are required for use in storing error location polynomial coefficients that are employed during the generation of the error location polynomial, and then these same first plurality of registers 840 and second plurality of registers 850 are employed again for performing the error location search operations, which can be performed using the Chien search approach 832, if desired.
For example, the error locator polynomial generation module 820 is operable to generate the error location polynomial that is based on a discrepancy that is based on syndromes that correspond to a received codeword of a RS coded signal that is being decoded. As can also be seen, the first plurality of registers 840 includes a number of registers as depicted by register 841, register 842, . . . , and a register 843. Similarly, the second plurality of registers 850 includes a number of registers as depicted by register 851, register 852, . . . , and a register 853. In some desired embodiments, each of the first plurality of registers 840 and a second plurality of registers 850 includes a same number of registers; each has the same number of registers.
Then, during the error location search operations, the error location search module 830 is operable to process the error location polynomial to locate an error within the RS coded signal. The error location search module 830 is operable to employ at least one of the first plurality of registers 840 and the second plurality of registers 850 to store a plurality of evaluated coefficients corresponding to an error location when processing the error location polynomial. If desired, the error location search module 830 is operable to perform Chien searching (e.g., reference numeral 832) to process the error location polynomial to locate the error within the RS coded signal.
A plurality of arithmetic logic units (ALUs) 960 as depicted by ALU(1), ALU(2), . . . , ALU(n) is operable to perform certain of the calculations required in performing both the error location polynomial generation and error value computation. One of the operations the plurality of ALUs 960 performs is the calculation of the values of sigma (σ) (which is based on the values in the first plurality of registers 940, the second plurality of registers 950, and the discrepancy ratio); another one of the operations the plurality of ALUs 960 performs is calculation of the discrepancy (which is based on the current sigma iteration and a selected set of syndromes). The discrepancy is generated using a summation of selected syndromes multiplied by corresponding sigma (σ) coefficients.
While a plurality of ALUs 960 is depicted here, it is noted that as few as a single ALU could be employed sequentially to perform the calculations for each of the corresponding registers. Alternatively, as many as one ALU could be employed for each to perform the calculations for each of the corresponding registers in a fully parallel implementation. Moreover, other number of ALUs can also be employed thereby giving a designer the ability to consider various cost performance trade-offs (e.g., various degrees of parallelism).
When performing the division operations in accordance with generating the error location polynomial, a divider 930 employs an inverter and a multiplier. This implementation of division is much cheaper than a single-cycle implemented divider in hardware. One of the reasons that such a divider 930 (inverter and multiplier) can be employed herein because of the pipelined arrangement of the decoding processing. For example, the division processing can be afforded slightly more time herein when compared to prior art approaches. This allows for the use of multiple clock cycles to perform the inversion processing, and inversion is much cheaper to implement than a single-cycle implemented divider in hardware. A state machine 920 is also employed to coordinate and govern the operations within the decoding processing.
As can be seen, the total number of registers required is slightly more than 4n, where n is the hardware correction power and n≦t; it is noted that t is the ECC software correction power. It is noted that this diagram corresponds to the ECC decoder and does not include the symbol/syndrome computer module. When also including the symbol/syndrome computer module, then total number of registers required would be slightly more than 6n.
In accordance with certain embodiments of decoding of a RS coded signal, it may be required to compute the error value polynomial, which is also referred to as the error magnitude polynomial. If this is a requirement, the value in the DEST register bank (reference numeral 950) may be moved into the SRC register bank (reference numeral 940) so that the error value polynomial can be computed and stored in the DEST register bank. However, some implementations may not require generation of the error value polynomial at all.
The next step is to evaluate the error location polynomial in order to determine the locations of all errors (i.e., perform the error location search operations). This can be performed using a Chien search operation in some embodiments. As mentioned above, the error location search operations (e.g., the Chien search) can be performed using the existing SRC (first plurality of registers 940) and DEST (second plurality of registers 950) register banks. In one embodiment of a HDD application, it is noted that this re-using of the same register banks can be performed provided that an entire ECC correction can be completed within the worst-case sector transfer time.
Again, such an implementation of division is much cheaper than a single-cycle implemented divider in hardware, and the pipelined arrangement of the decoding processing allows for the use of such a divider 1030 (inverter and multiplier). In this embodiment, Chien searching is performed, and a Chien search state machine 1020 is employed to coordinate and govern the operations of the error location search operation within the decoding processing.
The error location search operations employ a first plurality of registers 1040 and a second plurality of registers 1050 that are employed within the error location polynomial generation operations. The first plurality of registers 1040 is operable to store a first plurality of evaluated coefficients (e.g., a previous group) corresponding to each error location when processing the error location polynomial (σp(x)), shown as σp(1), σp(2), . . . , σp(n-1), and σp(n). The second plurality of registers 1050 is operable to store a second plurality of evaluated coefficients corresponding to each error location when processing the error location polynomial (e.g., a current group) (σc(x)), shown as σc(1), σc(2), . . . , σc(n-1), and σc(n).
The additional hardware required to perform a Chien search and compute error values (reference numeral 1031) includes constant (α) multipliers (shown as ×α), XOR trees and control logic. The divider and registers can be shared with the error location polynomial generation operations (e.g., the compute ELP function).
It is noted that various degrees of parallelism can be employed when doing error location searching (e.g., when doing Chien searching) in order to reduce evaluation time. Alternative to the embodiment shown in this diagram, multiple alpha (a) multipliers can be employed between the output of the registers and the input of the registers (e.g., multiple “×α” blocks could be employed instead of a singular “×α” block for each register). If this multiple alpha (α) multipliers are employed, then access to each intermediate result (i.e., each result after each alpha (α) multiplier) must be accessible for Chien searching evaluation. For example, multiple XOR trees would then operate on each intermediate result point to allow that point's evaluation in Chien searching.
It is also noted with respect to this diagram that while (σp(x)) is shown within the first plurality of registers 1040, the actual values in these registers are the coefficients of some polynomial that is employed to compute error values at each error location.
The method 1100 involves retrieving a previous plurality of error location polynomial coefficients from a first plurality of registers (as shown in a block 1120) and also retrieving a current plurality of error location polynomial coefficients from a second plurality of registers (as shown in a block 1130).
The method 1100 then operate by employing the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients, as shown in a block 1140.
Once these new plurality of error location polynomial coefficients have been calculated, the method 1100 operate by storing the new plurality of error location polynomial coefficients in the second plurality of registers, as shown in a block 1150. It is noted that no more than the first plurality of registers and the second plurality of registers are employed for use in storing error location polynomial coefficients. The method 1100 then continues by employing the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal, as shown in a block 1160.
In an embodiment alternative to the 1100, a method could be implemented thereby performing Chien searching to process the error location polynomial to locate an error within the RS coded signal, and thereafter employing at least one of the first plurality of registers and the second plurality of registers to store a plurality of evaluated coefficients corresponding to each error location when processing the error location polynomial.
Any division operations performed in accordance with the method 1100 can also be performed using an inverter and a multiplier to effectuate the dividing operation. For example, the method 1100 can operate by inverting at least one coefficient of the previous plurality of error location polynomial coefficients, and then multiplying the inverted at least one coefficient of the previous plurality of error location polynomial coefficients and at least one coefficient of the current plurality of error location polynomial coefficients thereby calculating the discrepancy ratio.
It is also noted that, although parameterization helps achieve minimal area goals for such a decoder architecture as described herein, while still meeting the architectural constraints, some embodiment of the this design can include components which cannot be parameterized. It is noted also that various embodiments and variations of the Berlekamp-Massey processing in accordance with decoding of a RS coded signal can also be employed without departing from the scope and spirit of the invention.
The present invention has also been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention.
The present invention has been described above with the aid of functional building blocks illustrating the performance of certain significant functions. The boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention.
One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.
Moreover, although described in detail for purposes of clarity and understanding by way of the aforementioned embodiments, the present invention is not limited to such embodiments. It will be obvious to one of average skill in the art that various changes and modifications may be practiced within the spirit and scope of the invention, as limited only by the scope of the appended claims.
The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. § 119(e) to the following U.S. Provisional Patent Applications which are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility patent application for all purposes: 1. U.S. Provisional Application Ser. No. 60/878,553, entitled “Area efficient on-the-fly error correction code (ECC) decoder architecture,” (Attorney Docket No. BP5586), filed Jan. 4, 2007, pending. 2. U.S. Provisional Application Ser. No. 60/899,522, entitled “Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation,” (Attorney Docket No. BP5587), filed Feb. 5, 2007, pending. The following U.S. Utility patent application is hereby incorporated herein by reference in its entirety and is made part of the present U.S. Utility patent application for all purposes: 1. U.S. Utility patent application Ser. No. ______, entitled “Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation,” (Attorney Docket No. BP5587), filed concurrently on Mar. 13, 2007, pending.
| Number | Date | Country | |
|---|---|---|---|
| 60878553 | Jan 2007 | US | |
| 60899522 | Feb 2007 | US |
