Patent Application
20250211252
Embodiments of the present invention relate to an efficient approach to determine and/or correct errors in data bits.
A cross parity code (see, e.g., [Duchrau, G., Gössel, M. (2023). Modified Cross Parity Codes for Adjacent Double Error Correction. In: Goumas, G., Tomforde, S., Brehm, J., Wildermann, S., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2023. Lecture Notes in Computer Science, vol 13949. Springer, Cham.]) utilizes data bits that are arranged in a quadratic array with a row parity for every row, a column parity for every column and an overall parity for all data bits. Each parity is represented by a single bit. Each row parity is determined as a modulo 2 sum of this row's data bits and each column parity is determined as a modulo 2 sum of this column's data bits. Finally, the overall parity is determined as a modulo 2 sum of all data bits.
The square array comprises M columns and M rows, i.e., M2 data bits. The cross parity code provides 2M+1 check bits, i.e., the aforementioned column parities, row parities and the overall parity.
A single bit error in one of the data bits allows determining the position of the error as it affects a row parity and a column parity. Correcting the single bit error can be achieved by flipping the data bit at the identified position.
It is an objective to provide a different approach for detecting and/or correcting errors in data bits.
The examples suggested herein may be based on at least one of the following solutions. In particular combinations of the following features could be utilized in order to reach a desired result. The features of the method could be combined with any feature(s) of the device, computer program product or vice versa.
A method is provided for determining an error in k data bits comprising the steps:
It is noted that the k data bits may comprise any sort of bits, payload, filling bits, constants or the like. Insofar, the term “data bits” is used merely to be differentiated from the term “check bits”. Hence, there is a first type of bits, which can be used for any kind of information, i.e., the data bits, and a second type of bits, i.e., the check bits, which are determined based on the data bits.
Thus, the error is determined based on a number of M+n check bits. It is noted that the M check bits are a first type of check bits that are part of the structure, e.g., along a diagonal of an array (or matrix), and the n check bits are a second type of check bits that may be stored separate to the structure. One of the n check bits is determined for each of the n groups.
The k data bits are distributed across the structure, wherein a single data bit of the k data bits is associated with only one of n groups of the structure.
It is noted that the structure may be a functional structure, i.e., it may utilize memory cells that could be spread across a physical memory in various ways. The functional structure allows for some representation of the memory cells that enables utilizing the above mentioned effect, i.e., separating the structure into n groups, defining n check bits for the n groups and M check bits, which are different from the n check bits, but also dependent on the structure and are also determined based on the k data bits. In other words, “arranged according to a structure” does not limit the placement of memory cell pursuant to any physical structure (or memory), but instead enables the features of the functional structure as described herein.
According to an embodiment, the M check bits are used to partition the structure into the n groups.
According to an embodiment, the structure is an array, in particular an array with M lines and M columns, and the M check bits are arranged on a diagonal of the array that divides the array into two groups.
According to an embodiment, each of the M check bits is determined based on an XOR operation or an XNOR operation of the data bits of the column and line associated with this particular M check bit.
According to an embodiment, the structure comprises
data bits.
According to an embodiment, n=2 and two groups of the n check bits each comprises
check bits.
According to an embodiment, each of the n check bits is determined based on an XOR operation or an XNOR operation of the k/n data bits of its group.
According to an embodiment, the error is corrected by inverting the erroneous data bit.
Also, a device is provided for determining an error in k data bits, the device comprising at least one processing unit that is configured to conduct the steps of the method as described herein.
Such processing unit can comprise at least one, in particular several means that are arranged to execute the steps of the method described herein. The means may be logically or physically separated; in particular several logically separate means could be combined in at least one physical unit. Said processing unit may comprise at least one of the following: a processor, a microcontroller, a hard-wired circuit, an ASIC, an FPGA, a logic device.
Further, a device for error correction is suggested, comprising:
According to an embodiment, the second circuit and the third circuit are combined into a single circuit.
According to an embodiment, the first circuit, the second circuit and optionally the third circuit are combined as a single circuit.
According to an embodiment, the structure is a square array and the M check bits are located along the diagonal of the square array separating the structure into n=2 groups.
Also, a computer program product is provided that is directly loadable into a memory of a digital processing device, comprising software code portions for performing the steps of the method as described herein.
Embodiments are shown and illustrated with reference to the drawings. The drawings serve to illustrate the basic principle, so that only aspects necessary for understanding the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like features.
Hence, the square array 101 has M2 fields, M check bits and
data bits.
The M check bits ci (i=1, . . . , M) are part of the array 101 and separate the k data bits into n=2 different groups 102, 103.
Each of the check bits ci (i=1, . . . , M) is determined based on the data bits, e.g., as follows:
Hence, each of the check bits ci (i=1, . . . , M) is determined based on the data bits that are arranged in the same column and the same row as this particular check bit.
In addition, two check bits p1, p2 are determined based on the data bits of the different groups, i.e.
In other words, one check bit pi is determined for each of the n different groups, by adding the data bits that are located in each of the n groups.
It is noted that each of the addition is a XOR (exclusive or) operation or an XNOR (exclusive not or) operation. As each of the data bits are either 0 or 1, the following applies in case of the XOR operation: 0+0-0, 0+1=1+0=1, 1+1=0.
If a position of a single bit error is detected, this error can be corrected by flipping the bit (either from 1 to 0 or from 0 to 1). This can be done by conducting an XOR operation of the error bit with 1 (if the error bit is 0, the corrected bit will be 1 and vice versa).
As an example, a single bit error may occur that falsifies the data bit x22 into x22′. This affects (i.e., changes) the check bits c2, c3 and p2.
Based on the erroneous check bits c2 and c3 alone, the error could also have affected data bit x32. However, the falsified data bit x22′ also inverts check bit p2 (but not check bit p1). As p1 is the check bit for the group in which data bit x22′ is located, it can be concluded that the faulty data bit has to be data bit x22′ and data bit x32 is correct. The correction of the falsified data bit x22′ is as follows:
For each of the n groups an additional (extra) check bit is provided, which can be calculated by adding the data bits of each group. Hence, in total a number of M+n check bits are used to detect the error, to determine the position of the error and to correct the error. The correction can be done by flipping (inverting) the incorrect bit.
A burst error is an error that may in particular affect a number of consecutive bits. This may be detrimental if several check bits are affected by the same burst error. In order to mitigate this issue, it is suggested that the order of the data bits within the structure, e.g., the aforementioned array, is re-arranged to avoid that previously consecutive data bits are “close” to each other in the structure.
An array with an exemplary mapping to mitigate handling burst errors is suggested in
For example, the first circuit 401 may receive a stream of data bits, which is separated into chunks of k data bits. For each chunk of k data bits, a structure (e.g., square array with M2 fields) is determined with a diagonal of M check bits. Each of the M check bits is calculated based on the data bits of the column and the row identified by this particular check bit. Further, the M check bits along the diagonal of the square array separate the array into n=2 groups. For each group, an additional check bit p1, p2 is calculated based on the data bits of the respective group. Hence, in this example, the first circuit outputs the square array comprising k=M2−M data bits and M check bits together with n=2 (separate) check bits p1, p2 to be stored in the memory 402.
It is noted that a large amount of data bits can be separated into chunks of k data bits and processed as described, i.e., for each chunk a structure with M check bits and n separate check bits is compiled and stored in the memory 402. It is further noted that if a chuck of data bit comprises less than k data bits, filling bits can be used (which could be predetermined bits or a coded sequence of bits indicating an end of the data bits).
A second circuit 403, e.g., a processing unit that conducts read operations on the memory 402, reads the structure and the n check bits from the memory 402.
A third circuit 404 could serve as an error detection and/or correction unit, which determines, based on the structure and the n check bits associated with this structure, whether or not (at least) one of the k data bits associated with the structure is incorrect. This can be determined based on the M check bits that are part of the structure and the additional n check bits that are separate to the structure as described above. If an error is determined, it can be corrected by inverting the erroneous data bit.
It is noted that any combination of the first circuit, second circuit and/or third circuit could be combined as a single circuit. It is another option that the memory is implemented together with any combination of these circuits.
In one or more examples, the functions described herein may be implemented at least partially in hardware, such as specific hardware components or a processor. More generally, the techniques may be implemented in hardware, processors, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.
By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium, i.e., a computer-readable transmission medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are instead directed to non-transient, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Instructions may be executed by one or more processors, such as one or more central processing units (CPU), digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.
The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a single hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware.
Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. Further, the methods of the invention may be achieved in either all software implementations, using the appropriate processor instructions, or in hybrid implementations that utilize a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims.
