using multiple parity bits

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CPC
H03M13/11

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Parent Industries

HELECTRICITY H03Electronic circuits H03MCODING DECODING CODE CONVERSION IN GENERAL H03M13/00Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes

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H03M13/11using multiple parity bits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Optimization of the computation of parity check messages in a min-s...
- Patent number 12,341,531
- Issue date Jun 24, 2025
- AIRBUS DEFENCE AND SPACE SAS
- Lyonel Barthe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Check node updates in bit flipping decoders
- Patent number 12,341,530
- Issue date Jun 24, 2025
- SK Hynix NAND Product Solutions Corp.
- Zion Kwok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and chip for cyclic code encoding, circuit component, and el...
- Patent number 12,339,738
- Issue date Jun 24, 2025
- Huawei Technologies Co., Ltd.
- Liang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simplified system and method for bit-interleaved coded modulation w...
- Patent number 12,341,610
- Issue date Jun 24, 2025
- Hughes Network Systems, LLC
- Liping Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LDPC code matrices
- Patent number 12,334,952
- Issue date Jun 17, 2025
- ENTROPIC COMMUNICATIONS, LLC
- Shaw Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shift values for quasi-cyclic LDPC codes
- Patent number 12,334,955
- Issue date Jun 17, 2025
- Telefonaktiebolaget LM Ericsson (publ)
- Sara Sandberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controllers and memory systems including the same
- Patent number 12,334,953
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Jiho Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Threshold-based min-sum algorithm to lower the error floors of quan...
- Patent number 12,334,954
- Issue date Jun 17, 2025
- Arrowhead Center, Inc.
- Homayoon Hatami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controller performing error correction and operating method...
- Patent number 12,332,741
- Issue date Jun 17, 2025
- SK hynix Inc.
- Jae Yong Son
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transmitter and shortening method thereof
- Patent number 12,328,187
- Issue date Jun 10, 2025
- Samsung Electronics Co., Ltd.
- Hong-sil Jeong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bypassing iterations in a bit flipping decoder using a least reliab...
- Patent number 12,328,129
- Issue date Jun 10, 2025
- Micron Technology, Inc.
- Mustafa N. Kaynak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correction circuit and data transmission method
- Patent number 12,323,161
- Issue date Jun 3, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kangling Ji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for low density parity check channel coding in...
- Patent number 12,323,162
- Issue date Jun 3, 2025
- Huawei Technologies Co., Ltd.
- Liang Ma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-density parity-check (LDPC) encoding method and apparatus
- Patent number 12,323,163
- Issue date Jun 3, 2025
- Huawei Technologies Co., Ltd.
- Guido Montorsi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for operating low-density parity-check bit-flip...
- Patent number 12,316,345
- Issue date May 27, 2025
- SK Hynix NAND Product Solutions Corp.
- Zion Kwok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PHY-based retry techniques for die-to-die interfaces
- Patent number 12,316,343
- Issue date May 27, 2025
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wear levelling for differing memory types
- Patent number 12,314,131
- Issue date May 27, 2025
- PURE STORAGE, INC.
- John D. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error processing and correction of adjacent 2-bit errors
- Patent number 12,316,346
- Issue date May 27, 2025
- Infineon Technologies AG
- Jens Rosenbusch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for constructing fast converging polar codes w...
- Patent number 12,316,344
- Issue date May 27, 2025
- Korea Advanced Institute of Science and Technology
- Jeongseok Ha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast converging low-density parity-check techniques
- Patent number 12,308,958
- Issue date May 20, 2025
- QUALCOMM Incorporated
- Pinar Sen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Decoder, decoding method, memory controller, and memory system
- Patent number 12,308,856
- Issue date May 20, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hua Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication techniques involving pairwise orthogonality of adjace...
- Patent number RE50437
- Issue date May 20, 2025
- QUALCOMM Incorporated
- Thomas Joseph Richardson
Information Patent Grant
Programmable metadata
- Patent number 12,299,291
- Issue date May 13, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Check node data compression in memory systems
- Patent number 12,301,253
- Issue date May 13, 2025
- SK Hynix NAND Product Solutions Corp.
- Zion Kwok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resource efficient list decoding operations
- Patent number 12,301,256
- Issue date May 13, 2025
- QUALCOMM Incorporated
- Yevgeny Zagalsky
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for low density parity check channel coding in...
- Patent number 12,301,255
- Issue date May 13, 2025
- Huawei Technologies Co., Ltd.
- Jie Jin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Check node data compression in memory systems
- Patent number 12,301,252
- Issue date May 13, 2025
- SK Hynix NAND Product Solutions Corp.
- Zion Kwok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Early stopping of bit-flip low density parity check decoding based...
- Patent number 12,301,254
- Issue date May 13, 2025
- Micron Technology, Inc.
- Eyal En Gad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for hybrid-ARQ
- Patent number 12,301,258
- Issue date May 13, 2025
- Huawei Technologies Co., Ltd.
- Ming Jia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read recovery for redundant array of independent NAND stripes
- Patent number 12,298,852
- Issue date May 13, 2025
- Micron Technology, Inc.
- Prashant Parashari
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AREA OPTIMIZED MODIFIED CROSS PARITY CODE FOR FAST ERROR CORRECTION...
- Publication number 20250211252
- Publication date Jun 26, 2025
- INFINEON TECHNOLOGIES AG
- Georg Duchrau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAST COMBINED CHASE AND GMD DECODING OF GENERALIZED REED-SOLOMON CODES
- Publication number 20250211257
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Yaron SHANY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CHECK NODE UPDATES IN BIT FLIPPING DECODERS
- Publication number 20250211254
- Publication date Jun 26, 2025
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Zion KWOK
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DECODERS, DECODING METHODS, MEMORY CONTROLLERS AND MEMORY SYSTEMS
- Publication number 20250211253
- Publication date Jun 26, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hua Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...
- Publication number 20250202503
- Publication date Jun 19, 2025
- Avago Technologies International Sales Pte. Limited
- Rethnakaran Pulikkoonattu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...
- Publication number 20250202505
- Publication date Jun 19, 2025
- Avago Technologies International Sales Pte. Limited
- Rethnakaran Pulikkoonattu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...
- Publication number 20250202504
- Publication date Jun 19, 2025
- Avago Technologies International Sales Pte. Limited
- Rethnakaran Pulikkoonattu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...
- Publication number 20250202506
- Publication date Jun 19, 2025
- Avago Technologies International Sales Pte. Limited
- Rethnakaran Pulikkoonattu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RATE MATCHING FOR MULTI-SLOT UPLINK SHARED CHANNEL TRANSMISSION
- Publication number 20250202618
- Publication date Jun 19, 2025
- QUALCOMM Incorporated
- Gokul SRIDHARAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR CORRECTION BASED ON ASYMMETRIC RATIO
- Publication number 20250202502
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Meysam Asadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STORAGE DEVICES CONFIGURED TO GENERATE PARITY BASED ON RELIABILITY,...
- Publication number 20250192805
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Kangseok Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EXTENDING LOW-DENSITY PARITY CHECK (LDPC) CODES FOR WI-FI
- Publication number 20250192806
- Publication date Jun 12, 2025
- QUALCOMM Incorporated
- Thomas Joseph Richardson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Wireless Transport Framework with Uncoded Transport Tunneling
- Publication number 20250192804
- Publication date Jun 12, 2025
- Coherent Logix, Incorporated
- Kevin A. Shelby
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DNA STORAGE ERROR CORRECTION CODE ARCHITECTURE FOR OPTIMIZED DECODING
- Publication number 20250183915
- Publication date Jun 5, 2025
- Western Digital Technologies, Inc.
- Alexander BAZARSKY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Erasure Coding on Partial Code Block Communication Interruption
- Publication number 20250183918
- Publication date Jun 5, 2025
- Hughes Network Systems, LLC
- Victor LIAU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM
- Publication number 20250183914
- Publication date Jun 5, 2025
- Huawei Technologies Co., Ltd
- Chen ZHENG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Control Information for a Wirelessly-Transmitted Data Stream
- Publication number 20250184556
- Publication date Jun 5, 2025
- HyperX Logic, Inc.
- Colleen J. McGinn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
- Publication number 20250175195
- Publication date May 29, 2025
- SK HYNIX INC.
- Chaehyeon SHIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HARD DECODING METHODS IN DATA STORAGE DEVICES
- Publication number 20250173220
- Publication date May 29, 2025
- KIOXIA Corporation
- Avi Steiner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STOP CRITERION FOR DECODING AN LDPC CODE
- Publication number 20250167807
- Publication date May 22, 2025
- AIRBUS DEFENCE AND SPACE SAS
- Lyonel BARTHE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR DECODING CODEWORDS
- Publication number 20250167812
- Publication date May 22, 2025
- INNOGRIT TECHNOLOGIES CO., LTD
- Chenrong Xiong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE METADATA
- Publication number 20250165160
- Publication date May 22, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-PERFORMANCE SCL BIT-FLIP DECODER FOR CONCATENATED POLAR CODES
- Publication number 20250167810
- Publication date May 22, 2025
- British Telecommunications public limited company
- Mo HAO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOFT DECODING OF THE FLOQUET CODES
- Publication number 20250165840
- Publication date May 22, 2025
- Microsoft Technology Licensing, LLC
- Nicolas Guillaume DELFOSSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF THE COMPUTATION OF PARITY CHECK MESSAGES IN A MIN-S...
- Publication number 20250167806
- Publication date May 22, 2025
- AIRBUS DEFENCE AND SPACE SAS
- Lyonel BARTHE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE SCALING OF PARITY CHECK MESSAGES FOR LDPC DECODING
- Publication number 20250167808
- Publication date May 22, 2025
- AIRBUS DEFENCE AND SPACE SAS
- Lyonel BARTHE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HAMMING CODE ENCODING AND ARRANGING METHOD AND STORAGE DEVICE DETEC...
- Publication number 20250167809
- Publication date May 22, 2025
- FocalTech Systems Co., Ltd.
- Yen-Kai TSAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR DETECTION AND CLASSIFICATION AT A HOST DEVICE
- Publication number 20250158639
- Publication date May 15, 2025
- Micron Technology, Inc.
- Aaron P. Boehm
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY SYSTEM AND METHOD
- Publication number 20250157564
- Publication date May 15, 2025
- KIOXIA Corporation
- Motoki SHIMIZU
- G11 - INFORMATION STORAGE
Information Patent Application
CHANNEL CODING METHOD, PROCESSING DEVICE, COMMUNICATION METHOD AND...
- Publication number 20250150198
- Publication date May 8, 2025
- Beijing ESWIN Computing Technology Co., Ltd.
- Yanqi WU
- H03 - BASIC ELECTRONIC CIRCUITRY

using multiple parity bits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Optimization of the computation of parity check messages in a min-s...

Check node updates in bit flipping decoders

Method and chip for cyclic code encoding, circuit component, and el...

Simplified system and method for bit-interleaved coded modulation w...

LDPC code matrices

Shift values for quasi-cyclic LDPC codes

Memory controllers and memory systems including the same

Threshold-based min-sum algorithm to lower the error floors of quan...

Memory controller performing error correction and operating method...

Transmitter and shortening method thereof

Bypassing iterations in a bit flipping decoder using a least reliab...

Error correction circuit and data transmission method

Method and apparatus for low density parity check channel coding in...

Low-density parity-check (LDPC) encoding method and apparatus

Systems and methods for operating low-density parity-check bit-flip...

PHY-based retry techniques for die-to-die interfaces

Wear levelling for differing memory types

Error processing and correction of adjacent 2-bit errors

Method and apparatus for constructing fast converging polar codes w...

Fast converging low-density parity-check techniques

Decoder, decoding method, memory controller, and memory system

Communication techniques involving pairwise orthogonality of adjace...

Programmable metadata

Check node data compression in memory systems

Resource efficient list decoding operations

Method and apparatus for low density parity check channel coding in...

Check node data compression in memory systems

Early stopping of bit-flip low density parity check decoding based...

System and method for hybrid-ARQ

Read recovery for redundant array of independent NAND stripes

Patents Applicationslast 30 patents

AREA OPTIMIZED MODIFIED CROSS PARITY CODE FOR FAST ERROR CORRECTION...

FAST COMBINED CHASE AND GMD DECODING OF GENERALIZED REED-SOLOMON CODES

CHECK NODE UPDATES IN BIT FLIPPING DECODERS

DECODERS, DECODING METHODS, MEMORY CONTROLLERS AND MEMORY SYSTEMS

SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...

SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...

SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...

SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CH...

RATE MATCHING FOR MULTI-SLOT UPLINK SHARED CHANNEL TRANSMISSION

ERROR CORRECTION BASED ON ASYMMETRIC RATIO

STORAGE DEVICES CONFIGURED TO GENERATE PARITY BASED ON RELIABILITY,...

EXTENDING LOW-DENSITY PARITY CHECK (LDPC) CODES FOR WI-FI

Wireless Transport Framework with Uncoded Transport Tunneling

DNA STORAGE ERROR CORRECTION CODE ARCHITECTURE FOR OPTIMIZED DECODING

Using Erasure Coding on Partial Code Block Communication Interruption

APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM

Control Information for a Wirelessly-Transmitted Data Stream

CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

HARD DECODING METHODS IN DATA STORAGE DEVICES

STOP CRITERION FOR DECODING AN LDPC CODE

SYSTEMS AND METHODS FOR DECODING CODEWORDS

PROGRAMMABLE METADATA

HIGH-PERFORMANCE SCL BIT-FLIP DECODER FOR CONCATENATED POLAR CODES

SOFT DECODING OF THE FLOQUET CODES

OPTIMIZATION OF THE COMPUTATION OF PARITY CHECK MESSAGES IN A MIN-S...

ADAPTIVE SCALING OF PARITY CHECK MESSAGES FOR LDPC DECODING

HAMMING CODE ENCODING AND ARRANGING METHOD AND STORAGE DEVICE DETEC...

ERROR DETECTION AND CLASSIFICATION AT A HOST DEVICE

MEMORY SYSTEM AND METHOD

CHANNEL CODING METHOD, PROCESSING DEVICE, COMMUNICATION METHOD AND...