Patent Application
20240107749
Embedded memory is important to the performance of modern system-on-a-chip (SoC) technology. Low power and high density embedded memory is used in many different computer products and further improvements are always desirable.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
13 provide cross-sections of two example arrangement of access transistors with capacitors over and under the access transistors, where capacitors in different layers are coupled to different platelines, and the platelines include stacked vias, according to some embodiments of the present disclosure.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating IC devices implementing memory with one access transistor for multiple capacitors as described herein, it might be useful to first understand phenomena that may come into play in certain IC arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Some memory devices may be considered “standalone” devices in that they are included in a chip that does not also include compute logic (where, as used herein, the term “compute logic devices” or simply “compute logic” or “logic devices,” refers to IC components, e.g., transistors, for performing computing/processing operations). Other memory devices may be included in a chip along with compute logic and may be referred to as “embedded” memory devices. Using embedded memory to support compute logic may improve performance by bringing the memory and the compute logic closer together and eliminating interfaces that increase latency. Various embodiments of the present disclosure relate to embedded memory arrays, as well as corresponding methods and devices.
Described herein are memory arrangements and corresponding methods and devices. In some embodiments, the memory arrangements may include hysteretic memory. Hysteretic memory refers to a memory technology employing hysteretic materials or arrangements, where a material or an arrangement may be described as hysteretic if it exhibits the dependence of its state on the history of the material (e.g., on a previous state of the material). Ferroelectric (FE) and antiferroelectric (AFE) materials are one example of hysteretic materials. Layers of different materials arranged in a stack to exhibit charge-trapping phenomena is one example of a hysteretic arrangement.
A FE or an AFE material is a material that exhibits, over some range of temperatures, spontaneous electric polarization, i.e., displacement of positive and negative charges from their original position, where the polarization can be reversed or reoriented by application of an electric field. In particular, an AFE material is a material that can assume a state in which electric dipoles from the ions and electrons in the material may form a substantially ordered (e.g., substantially crystalline) array, with adjacent dipoles being oriented in opposite (antiparallel) directions (i.e., the dipoles of each orientation may form interpenetrating sub-lattices, loosely analogous to a checkerboard pattern), while a FE material is a material that can assume a state in which all of the dipoles point in the same direction. Because the displacement of the charges in FE and AFE materials can be maintained for some time even in the absence of an electric field, such materials may be used to implement memory cells. Because the current state of the electric dipoles in FE and AFE materials depends on the previous state, such materials are hysteretic materials. Memory technology where logic states are stored in terms of the orientation of electric dipoles in (i.e., in terms of polarization of) FE or AFE materials is referred to as “FE memory,” where the term “ferroelectric” is said to be adopted to convey the similarity of FE memories to ferromagnetic memories, despite the fact that there is typically no iron (Fe) present in FE or AFE materials.
A stack of alternating layers of materials that is configured to exhibit charge-trapping is an example of a hysteretic arrangement. Such a stack may include as little as two layers of materials, one of which is a charge-trapping layer (i.e., a layer of a material configured to trap charges when a voltage is applied across the material) and the other one of which is a tunnelling layer (i.e., a layer of a material through which the charge is to be tunneled to the charge-trapping layer). The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include a metal or a semiconductor material that is configured to trap charges. For example, a material that includes silicon and nitrogen (e.g., silicon nitride) may be used in/as a charge-trapping layer. Because the trapped charges may be kept in a charge-trapping arrangement for some time even in the absence of an electric field, such arrangements may be used to implement memory cells. Because the presence and/or the amount of trapped charges in a charge-trapping arrangement depends on the previous state, such arrangements are hysteretic arrangements. Memory technology where logic states are stored in terms of the amount of charge trapped in a hysteretic arrangement may be referred to as “charge-trapping memory.”
Hysteretic memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high speed writing. In addition, hysteretic memories may be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology. Therefore, over the last few years, these types of memories have emerged as promising candidates for many growing applications.
The performance of a hysteretic memory cell may depend on the number of factors. One factor is the ability of a cell to prevent or minimize detrimental effects of voltages which may unintentionally disturb a polarization state or a trapped charge that the cell is supposed to hold. Unlike ferromagnetic cores which have square-like hysteresis loops with sharp transitions around their coercive points, as is desirable for memory implementations, hysteresis loops of hysteretic materials/arrangements may not always have sharp transitions which means that even relatively small voltages can inadvertently disturb their polarization states. One approach to address this issue could be to improve processing techniques for creating hysteretic materials/arrangements in an attempt to realize square-like hysteresis loops. Another approach is to overcome this shortcoming of the materials by employing creative circuit architectures, e.g., by using access transistors to control access to hysteretic memory cells.
Access transistors have been used in the past to realize memory where each memory cell includes one capacitor for storing a memory state (e.g., logical “1” or “0”) of the cell and an access transistor controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a “1T-1C memory cell,” highlighting the fact that it uses one access transistor (i.e., “1T” in the term “1T-1C memory cell”) and one capacitor (i.e., “1C” in the term “1T-1C memory cell”). The capacitor of a 1T-1C memory cell may be coupled to either a source or a drain (S/D) terminal/region of the access transistor (e.g., to the source terminal/region of the access transistor), while the other S/D terminal/region of the access transistor (e.g., to the drain terminal/region) may be coupled to a bitline, and a gate terminal of the access transistor may be coupled to a wordline. Since such a memory cell can be fabricated with as little as a single access transistor, it can provide higher density and lower standby power versus some other types of memory in the same process technology. The capacitors of 1T-1C memory cells may be implemented using a ferroelectric material instead of, or in addition to, a conventional dielectric material, thus realizing ferroelectric 1T-1C memory cells. Inventors of the present disclosure realized that memory arrays implementing ferroelectric 1T-1C memory cells may have limitations in terms of, e.g., the number of active memory layers, memory density, and fabrication approaches.
Embodiments of the present disclosure may improve on at least some of the challenges and issues of existing memory arrays by increasing the number of active memory layers, to generate a vertically-stacked memory using fewer masks and at a lower cost. In particular, embodiments of the present disclosure provide various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. In some embodiments, the capacitors are hysteretic capacitors. As used herein, a capacitor is referred to as a “hysteretic capacitor” if, instead of or in addition to a conventional dielectric material, the capacitor includes a hysteretic material or a hysteretic arrangement as a capacitor insulator that separates first and second capacitor electrodes. An individual one of the multiple hysteretic capacitors may store a memory state, thus realizing a memory cell of a memory array. An example memory unit of an IC device implementing memory with one access transistor for multiple hysteretic capacitors includes an access transistor and N hysteretic capacitors coupled to the access transistor in a way that allows selecting all of the N hysteretic capacitors for performing READ and/or WRITEs operation when the access transistor is ON (e.g., when current may be conducted between source and drain terminals of the access transistor). An example IC device includes a memory array of M of such memory units, as well as W wordlines, B bitlines, and P platelines, where any of variables N, M, W, B, and P may be any integer greater than 1.
An IC device may be provided on a support structure such as a substrate, a die, a wafer, or a chip, and, in various arrangements disclosed herein, various capacitors and platelines may be arranged in different layers with respect to the support structure than layers in which wordlines and/or bitlines are implemented, thus realizing a three-dimensional (3D) stacked architecture of the memory array. Incorporating capacitors and platelines in different layers with respect to a support structure may allow significantly increasing density of memory cells in a memory array having a given footprint area (the footprint area being defined as an area in a plane of the support structure, or a plane parallel to the plane of the support structure, i.e., the x-y plane of the example coordinate system shown in the present drawings), or, conversely, allow significantly reducing the footprint area of the memory array with a given density of memory cells. IC devices implementing memory with one access transistor for multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high density embedded memory compatible with advanced CMOS processes. Other technical effects will be evident from various embodiments described here.
As used herein, a “memory state” (or, alternatively, a “logic state,” a “state,” or a “bit” value) of a memory cell refers to one of a finite number of states that the cell can have, e.g., logic states “1” and “0.” When any of the memory cells as described herein use a hysteretic material such as a FE or an AFE material, in some embodiments, a logic state of the memory cell may be represented simply by presence or absence of polarization of a FE or an AFE material in a certain direction (for example, for a two-state memory where a memory cell can store one of only two logic states—one logic state representing the presence of polarization in a certain direction and the other logic state representing the absence of polarization in a certain direction). In other embodiments of memory cells that include hysteretic materials such as FE or AFE materials, a logic state of a memory cell may be represented by the amount of polarization of a FE or an AFE material in a certain direction (for a multi-state memory where a memory cell can store one of three or more logic states, where different logic states represent the presence of different amounts of polarization in a certain direction). When any of the memory cells as described herein use a charge-trapping hysteretic arrangement, in some embodiments, a logic state of a memory cell may be represented simply by presence or absence of charge trapped in a charge-trapping hysteretic arrangement (for example, for a two-state memory where a memory cell can store one of only two logic states—one logic state representing the presence of charge and the other logic state representing the absence of charge). In other embodiments of memory cells that include charge-trapping hysteretic arrangements, a logic state of a memory cell may be represented by the amount charge trapped in a charge-trapping hysteretic arrangement (for example, for a multi-state memory where a memory cell can store one of three or more logic states, where different logic states represent the presence of different amounts of trapped charges). As used herein, “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, some descriptions may refer to a particular S/D region of a transistor being either a source region or a drain region. However, unless specified otherwise, which region of a transistor is considered to be a source region and which region is considered to be a drain region is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions provided herein are applicable to embodiments where the designation of source and drain regions may be reversed. Furthermore, in context of S/D regions, the term “region” may be used interchangeably with the terms “contact” and “terminal” of a transistor.
As used herein, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, analogous elements designated in the present drawings with different reference numerals after a dash, e.g., capacitors 106-1, 106-2, and so on may be referred to together without the reference numerals after the dash, e.g., as “capacitors 106.” In order to not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference sign.
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices implementing memory with one access transistor for multiple capacitors as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various IC devices implementing memory with one access transistor for multiple capacitors cells as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
In general, any of variables N, M, W, B, and P may be any integer greater than 1 and may be different from one another, although in some specific embodiments two of more of these variables may be of the same value (e.g., the number of wordlines 140 may be equal to the number of bitlines 150, i.e., W=B in some embodiments). In some embodiments, the value of one of these variables depends on the value of one or more of the other ones of these variables (e.g., in various embodiments, the number of platelines 160 may depend on one or more of the number of wordlines 140, the number of bitlines 150, and the number of capacitors 114 in each of the memory units 110). The following convention is used in some of the subsequent drawings and in the present descriptions to refer to different instances of the wordlines 140, bitlines 150, and platelines 160 of the IC device 100. An individual wordline 140 is labeled in some of the subsequent drawings as WLi, where i is an integer between 1 and W, identifying one of the W wordlines 140. An individual bitline 150 is labeled in some of the subsequent drawings as BLi, where j is an integer between 1 and B, identifying one of the B bitlines 150. An individual capacitor 114 within a given memory unit 110 is labeled in some of the subsequent drawings as CAPk, where k is an integer between 1 and N, identifying one of the N capacitors 114. An individual plateline 160 is labeled in some of the subsequent drawings with one or two indices that may depend on the arrangement of the wordlines 140 and the bitlines 150, and to which one of the N capacitors 114 the plateline 160 is coupled to, such one or two indices identifying one of the P platelines 160. A three-dimensional tensor may then be defined, where indices i, j, and k of a given element of the tensor uniquely identify each of the capacitors 114 of the IC device 100 in terms of a unique combination of a wordline 140-i and a bitline 150-j to which the memory unit 110 of a given capacitor 114 belongs to, in combination with a unique identification of the capacitor 114-k within that memory unit 110. Because each capacitor 114 may be used to store a logic state, thus serving as a memory cell of the IC device 100, such a tensor may be used to uniquely identify each memory cell of the IC device 100.
As shown in
In some embodiments, the access transistors 112 of the IC device 100 may be implemented as transistors having a non-planar architecture. Examples of transistors having a non-planar architecture include double-gate transistors, trigate transistors, FinFETs, and nanoribbon-based transistors. In comparison to a planar architecture where the transistor channel has only one confinement surface, a non-planar architecture is any type of architecture where the transistor channel has more than one confinement surfaces. A confinement surface refers to a particular orientation of the channel surface that is confined by the gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as single-gate transistors.
Where the memory units 210A and 210B differ from one another is in what the other, second, capacitor electrode (labeled in the example of
Each of the WL 140, the BL 150, and the PL 160, as well as intermediate elements coupling these lines to various terminals described herein, may be formed of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, with metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys oxides or carbides of one or more metals.
As shown in
In some embodiments, the hysteretic element 118 may be provided as a layer of a FE or an AFE material. Such an FE/AFE material may include one or more materials that can exhibit sufficient FE/AFE behavior even at thin dimensions, e.g., such as an insulator material at least about 5%, e.g., at least about 7% or at least about 10%, of which is in an orthorhombic phase and/or a tetragonal phase (e.g., as a material in which at most about 95-90% of the material may be amorphous or in a monoclinic phase). For example, such materials may be based on hafnium and oxygen (e.g., hafnium oxides), with various dopants added to ensure sufficient amount of an orthorhombic phase or a tetragonal phase. Some examples of such materials include materials that include hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials that include hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials that include hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials that include hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials that include hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other materials which exhibit FE/AFE behavior at thin dimensions may be used as the hysteretic elements 118 and are within the scope of the present disclosure.
In other embodiments, the hysteretic element 118 may be provided as a stack of alternating layers of materials that can trap charges. In some such embodiments, the stack may be a two-layer stack, where one layer is a charge-trapping layer and the other layer is a tunnelling layer. The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include an electrically conductive material such as a metal, or a semiconductor material. In some embodiments, the charge-trapping layer may include a material that includes silicon and nitrogen (e.g., silicon nitride). In general, any material that has defects that can trap charge may be used in/as a charge-trapping layer. Such defects are very detrimental to operation of logic devices and, therefore, typically, deliberate steps need to be taken to avoid presence of the defects. However, for memory devices, such defects are desirable because charge-trapping may be used to represent different memory states of a memory cell.
In some embodiments of the hysteretic element 118 being provided as a stack of alternating layers of materials that can trap charges, the stack may be a three-layer stack where an insulator material is provided on both sides of a charge-trapping layer. In such embodiments, a layer of an insulator material on one side of the charge-trapping layer may be referred to as a “tunnelling layer” while a layer of an insulator material on the other side of the charge-trapping layer may be referred to as a “field layer.”
In various embodiments of the hysteretic element 118 being provided as a stack of alternating layers of materials that can trap charges, a thickness of each layer the stack may be between about 0.5 and 10 nanometers, including all values and ranges therein, e.g., between about 0.5 and 5 nanometers. In some embodiment of a three-layer stack, a thickness of each layer of the insulator material may be about 0.5 nanometers, while a thickness of the charge-trapping layer may be between about 1 and 8 nanometers, e.g., between about 2.5 and 7.5 nanometers, e.g., about 5 nanometers. In some embodiments, a total thickness of the hysteretic element 118 provided as a stack of alternating layers of materials that can trap charges (i.e., a hysteretic arrangement) may be between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, e.g., about 6 nanometers.
What
What
Each of
In some implementations, the relative orientations of wordlines 140, bitlines 150, and platelines 160 as shown in
The support structure over which the IC device 100 is provided may, e.g., be the wafer 1500 of
In the IC device 300, each of the memory units 110 is implemented as the memory unit 210A of
Thus, in the IC device 300, corresponding capacitors 114 of the memory units 110 coupled to a single bitline 150-j (i.e., of the memory units 110 that belong to the column j) are coupled to a single plateline 160, where the capacitors 114 of different memory units 110 are described as “corresponding” when they have the same index k identifying them. For example, in the IC device 300, capacitor CAP1 of the memory unit 110-11, capacitor CAP1 of the memory unit 110-21, and so on until capacitor CAP1 of the memory unit 110-W1 are corresponding capacitors, each coupled to the plateline P11 and included in different memory units 110 of column 1; capacitor CAP2 of the memory unit 110-11, capacitor CAP2 of the memory unit 110-21, and so on until capacitor CAP2 of the memory unit 110-W1 are corresponding capacitors, each coupled to the plateline P12 and included in different memory units 110 of column 1; and so on up to capacitor CAPN of the memory unit 110-11, capacitor CAPN of the memory unit 110-21, and so on until capacitor CAPN of the memory unit 110-W1 also being corresponding capacitors, each coupled to the plateline P12 and included in different memory units 110 of column 1. The memory units 110 to which the platelines P11 to P1N of the IC device 300 are coupled are memory units 110 of the column 1 (i.e., memory units 110 coupled to the bitline BL1). In another example, in the IC device 300, capacitor CAP1 of the memory unit 110-1B, capacitor CAP1 of the memory unit 110-2B, and so on until capacitor CAP1 of the memory unit 110-WB are corresponding capacitors, each coupled to the plateline PB1 and included in different memory units 110 of column B; capacitor CAP2 of the memory unit 110-1B, capacitor CAP2 of the memory unit 110-2B, and so on until capacitor CAP2 of the memory unit 110-WB are corresponding capacitors, each coupled to the plateline PB2 and included in different memory units 110 of column B; and so on up to capacitor CAPN of the memory unit 110-1B, capacitor CAPN of the memory unit 110-2B, and so on until capacitor CAPN of the memory unit 110-WB also being corresponding capacitors, each coupled to the plateline PBN and included in different memory units 110 of column B. The memory units 110 to which the platelines PB1 to PBN of the IC device 300 are coupled are memory units 110 of the column B (i.e., memory units 110 coupled to the bitline BLB). Thus, in the IC device 300, memory units 110 of different columns (i.e., memory units 110 coupled to different bitlines 150) are coupled to respective different sets of N platelines 160. More generally, in the IC device 300, a memory unit 110-ij, coupled to the wordline WLi and to the bitline BLj, is coupled to a set of platelines PLj1 through PLjN, where, more specifically, each capacitor CAPk of the memory unit 110-ij is coupled to a corresponding plateline PLjk. In such an arrangement, the total number of platelines 160 in the IC device 300 is BxN.
In the IC device 300, each capacitor 114 may be addressed (i.e., selected for READ and WRITE operations) by a unique combination of a wordline WLi, a bitline BLj, and a plateline PLjk. In the context of the present disclosure, a combination of control lines is described as “unique” when the combination differs from all other combinations in at least one control line being different. For example, in the IC device 300, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., j=1 and k=2), while the capacitor CAP2 of the memory unit 110-W1 may be addressed by a combination of the wordline WLW (i.e., i=W), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., j=1 and k=2). While the bitlines 150 and the platelines 160 in these two combinations are the same (i.e., BL1 and PL12 for each of the two combinations), the wordlines 140 are different (i.e., WL1 in the first combination and WLW in the second combination), making these combinations unique with respect to one another. In another example for the IC device 300, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., j=1 and k=2), while the capacitor CAP2 of the memory unit 110-1B may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL B (i.e., j=13), and the plateline PLB2 (i.e., j=B and k=2). While the wordlines 140 in these two combinations are the same (i.e., WL1 for each of the two combinations), the bitlines 150 and the platelines 160 are different (i.e., respectively, BL1 and PL12 in the first combination and, respectively, BLB and PLB2 in the second combination), making these combinations unique with respect to one another. In yet another example for the IC device 300, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., j=1 and k=2), while the capacitor CAPN of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL1N (i.e., j=1 and k=N). While the wordlines 140 and the bitlines 150 in these two combinations are the same (i.e., WL1 and BL1 for each of the two combinations), the platelines 160 are different (i.e., PL12 in the first combination and PL1N in the second combination), making these combinations unique with respect to one another. Having each capacitor 114 of the IC device 100 being addressed by a unique combination of a wordline WLi, a bitline BLj, and a plateline PLjk, e.g., as is the case with the IC device 300, advantageously allows performing READ and WRITE operations on different memory cells (i.e., on different capacitors 114) independently of one another.
In the IC device 400, each of the memory units 110 is implemented as the memory unit 210A of
Thus, in the IC device 400, corresponding capacitors 114 of the memory units 110 coupled to a single wordline 140-i (i.e., of the memory units 110 that belong to the row i) are coupled to a single plateline 160, where, as described above, the capacitors 114 of different memory units 110 are described as “corresponding” when they have the same index k identifying them. For example, in the IC device 400, capacitor CAP1 of the memory unit 110-11, capacitor CAP1 of the memory unit 110-12, and so on until capacitor CAP1 of the memory unit 110-1B are corresponding capacitors, each coupled to the plateline P11 and included in different memory units 110 of row 1; capacitor CAP2 of the memory unit 110-11, capacitor CAP2 of the memory unit 110-12, and so on until capacitor CAP2 of the memory unit 110-1B are corresponding capacitors, each coupled to the plateline P12 and included in different memory units 110 of row 1; and so on up to capacitor CAPN of the memory unit 110-11, capacitor CAPN of the memory unit 110-21, and so on until capacitor CAP N of the memory unit 110-1B also being corresponding capacitors, each coupled to the plateline P1N and included in different memory units 110 of row 1. The memory units 110 to which the platelines P11 to P1N of the IC device 400 are coupled are memory units 110 of the row 1 (i.e., memory units 110 coupled to the wordline WL1). In another example, in the IC device 400, capacitor CAP1 of the memory unit 110-W1, capacitor CAP1 of the memory unit 110-W2, and so on until capacitor CAP1 of the memory unit 110-WB are corresponding capacitors, each coupled to the plateline PW1 and included in different memory units 110 of row W; capacitor CAP2 of the memory unit 110-W1, capacitor CAP2 of the memory unit 110-W2, and so on until capacitor CAP2 of the memory unit 110-WB are corresponding capacitors, each coupled to the plateline PW2 and included in different memory units 110 of row W; and so on up to capacitor CAPN of the memory unit 110-W1, capacitor CAPN of the memory unit 110-W2, and so on until capacitor CAPN of the memory unit 110-WB also being corresponding capacitors, each coupled to the plateline PWN and included in different memory units 110 of row W. The memory units 110 to which the platelines PW1 to PWN of the IC device 400 are coupled are memory units 110 of the row W (i.e., memory units 110 coupled to the wordline WLW). Thus, in the IC device 400, memory units 110 of different rows (i.e., memory units 110 coupled to different wordlines 140) are coupled to respective different sets of N platelines 160. More generally, in the IC device 400, a memory unit 110-ij, coupled to the wordline WLi and to the bitline BLj, is coupled to a set of platelines PLi1 through PLiN, where, more specifically, each capacitor CAPk of the memory unit 110-ij is coupled to a corresponding plateline PLk. In such an arrangement, the total number of platelines 160 in the IC device 400 is WxN.
Similar to the IC device 300, in the IC device 400, each capacitor 114 may be addressed (i.e., selected for READ and WRITE operations) by a unique combination of a wordline WLi, a bitline BLj, and a plateline PLik. For example, in the IC device 400, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., i=1 and k=2), while the capacitor CAP2 of the memory unit 110-W1 may be addressed by a combination of the wordline WLW (i.e., i=W), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., i=1 and k=2). While the bitlines 150 and the platelines 160 in these two combinations are the same (i.e., BL1 and PL12 for each of the two combinations), the wordlines 140 are different (i.e., WL1 in the first combination and WLW in the second combination), making these combinations unique with respect to one another. In another example for the IC device 400, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., i=1 and k=2), while the capacitor CAP2 of the memory unit 110-W1 may be addressed by a combination of the wordline WLW (i.e., i=W), the bitline BL1 (i.e., j=1), and the plateline PLW2 (i.e., i=W and k=2). While the bitlines 150 in these two combinations are the same (i.e., BL1 for each of the two combinations), the wordlines 140 and the platelines 160 are different (i.e., respectively, WL1 and PL12 in the first combination and, respectively, WLW and PLW2 in the second combination), making these combinations unique with respect to one another. In yet another example for the IC device 400, the capacitor CAP2 of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL12 (i.e., i=1 and k=2), while the capacitor CAPN of the memory unit 110-11 may be addressed by a combination of the wordline WL1 (i.e., i=1), the bitline BL1 (i.e., j=1), and the plateline PL1N (i.e., i=1 and k=N). While the wordlines 140 and the bitlines 150 in these two combinations are the same (i.e., WL1 and BL1 for each of the two combinations), the platelines 160 are different (i.e., PL12 in the first combination and PL1N in the second combination), making these combinations unique with respect to one another. Having each capacitor 114 of the IC device 100 being addressed by a unique combination of a wordline WLi, a bitline BLj, and a plateline PLik, e.g., as is the case with the IC device 400, advantageously allows performing READ and WRITE operations on different memory cells (i.e., on different capacitors 114) independently of one another.
In the IC device 500, each of the memory units 110 is implemented as the memory unit 210B of
Thus, in the IC device 500, all N of the capacitors 114 of each of the memory units 110 coupled to a single wordline 140-i (i.e., of the memory units 110 that belong to the row i) are coupled to a single plateline 160-i. For example, in the IC device 500, all of the capacitors CAP1 through CAPN of each of the memory units 110-11 through 110-1B are coupled to the plateline where each set of capacitors CAP1 through CAPN is included in different memory units 110 of row 1. Similarly, all of the capacitors CAP1 through CAPN of each of the memory units 110-W1 through 110-WB are coupled to the plateline PW, where each set of capacitors CAP1 through CAPN is included in different memory units 110 of row W. Thus, in the IC device 500, memory units 110 of different rows (i.e., memory units 110 coupled to different wordlines 140) are coupled to respective different platelines 160. More generally, in the IC device 500, a memory unit 110-ij, coupled to the wordline WLi and to the bitline BLj, is coupled to a single plateline PLi, where, more specifically, each capacitor CAPk of the memory unit 110-ij is coupled to the same plateline PLi. In such an arrangement, the total number of platelines 160 in the IC device 500 is W.
In contrast to the IC device 300 and the IC device 400, in the IC device 500, not all capacitors 114 may be addressed by a unique combination of a wordline, a bitline, and a plateline. Rather, each N of the capacitors 114 of a memory unit 110-ij that is coupled to a wordline WLi and a bitline BLj are coupled to a single plateline PLi, making the combination of the wordline WLi, the bitline BLj, and the plateline PLi the same (i.e., not unique) for each of the N capacitors 114 of this memory unit. Having each N of the capacitors 114 of a memory unit 110-ij of the IC device 100 being addressed by the same combination of a wordline WLi, a bitline BLj, and a plateline PLi, e.g., as is the case with the IC device 500, does not allow performing READ and WRITE operations on different memory cells (i.e., on different capacitors 114) of a given memory unit 110 independently of one another. However, such implementations may be useful in deployment scenarios such as one-time-programming (OTP) where the individual capacitors of a given memory unit 110 may be pre-programmed differently in the design stage (e.g., during manufacture of the IC device 100) but then be addressed for READ and WRITE operations as a group. Such OTP implementations may, e.g., be used as a physical unclonable function (PUF) of the IC device 100. In such scenarios, the IC device 100 implemented as the IC device 500 may be advantageous in terms of, e.g., simpler fabrication.
Similar to the IC device 500, in the IC device 600 each of the memory units 110 is implemented as the memory unit 210B of
In contrast to the IC device 500, in the IC device 600 the platelines 160 are not parallel to the wordlines 140, meaning that a single plateline 160 is not shared among multiple bitlines 150. The platelines 160 are also not parallel to the bitlines 150, meaning that a single plateline 160 is not shared among multiple wordlines 140. Instead, in the IC device 600, each of the platelines 160 corresponds to a unique combination of a particular wordline 140-i and a particular bitline 150-j used to address the capacitors 114 of the memory unit 110-ij to which the plateline 160 is coupled. This is illustrated in
While each plateline PLij of the IC device 600 is coupled to a unique combination of a wordline WLi and a bitline BLj, not all capacitors 114 may be addressed by a unique combination of a wordline, a bitline, and a plateline. Rather, each N of the capacitors 114 of a memory unit 110-ij that is coupled to a wordline WLi and a bitline BLj are coupled to a single plateline PLij, making the combination of the wordline WLi, the bitline BLj, and the plateline PLij the same (i.e., not unique) for each of the N capacitors 114 of this memory unit. Having each N of the capacitors 114 of a memory unit 110-ij of the IC device 100 being addressed by the same combination of a wordline WLi, a bitline BLj, and a plateline PLij, e.g., as is the case with the IC device 600, does not allow performing READ and WRITE operations on different memory cells (i.e., on different capacitors 114) of a given memory unit 110 independently of one another, but may be useful and advantageous in certain deployment scenarios, such as those described for the IC device 500.
Various arrangements of the IC device 100 as illustrated in
A number of elements referred to in the description of
The access transistor 112 includes the channel material 704, gate 706, and S/D contacts 708. The gate 106 may be coupled to a WL, not specifically shown in
In general, implementations of the present disclosure may be formed or carried out on a support structure 702, such as a semiconductor substrate composed of semiconductor material systems, and in particular, N-type material systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure. In various embodiments the support structure 702 may include any such substrate that provides a suitable surface for providing any of the memory arrangements shown in
The access transistor 112 is formed over the support structure 702. The gate 706 may include a gate electrode and a gate dielectric. The gate electrode may include at least one P-type work function metal or N-type work function metal, depending on whether the access transistor 112 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor. For a PMOS transistor, metals that may be used for the gate electrode may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). Other materials that may be used include titanium nitride, tantalum nitride, hafnium nitride, tungsten, iridium, copper, or degenerately doped poly-silicon. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate dielectric may include one or more high-k dielectrics. Examples of high-k materials that may be used in the gate dielectric may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, silicon oxide, tungsten oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, lead zinc niobate, aluminum nitride, and silicon nitride. In some embodiments, the gate dielectric may consist of a stack of two or more dielectric layers, e.g., a stack of two or more of the high-k materials listed above. The gate dielectric, or a layer of the gate dielectric, may comprise a mixture of the materials listed above and/or of other oxides, nitrides, or oxynitrides.
The gate dielectric may be deposited using a conformal deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Conformal deposition generally refers to deposition of a certain coating on any exposed surface of a given structure. A conformal coating may, therefore, be understood as a coating that is applied to exposed surfaces of a given structure, and not, for example, just to the horizontal surfaces. In some embodiments, an annealing process may be carried out on the gate dielectric during manufacture of the access transistor 112 to improve the quality of the gate dielectric. The gate dielectric may have a thickness, a dimension measured in the direction of the z-axis of the reference coordinate system x-y-z shown in
In some embodiments, the channel material 704 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material 704 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material 704 may include a combination of semiconductor materials where one semiconductor material may be used for the channel portion and another material, sometimes referred to as a “blocking material,” may be used between the channel portion and the support structure over which the access transistor 112 is provided. In some embodiments, the channel material 704 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material 704 may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the access transistor 112 is an NMOS), the channel material 704 may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material 704 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material 704 may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material 704, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material 704 may be relatively low, for example below 1015 dopant atoms per cubic centimeter (cm−3), and advantageously below 1013 cm−3.
For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 112 is a PMOS), the channel material 704 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material 704 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material 704 may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material 704, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material is relatively low, for example below 1015 cm−3, and advantageously below 1013 cm−3.
In some embodiments, the access transistor 704 may be a thin film transistor (TFT). A TFT is a special kind of a field-effect transistor made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a supporting layer that may be a non-conducting layer. At least a portion of the active semiconductor material forms a channel of the TFT. In some embodiments, the channel material 704 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin film channel material 704 may be deposited at relatively low temperatures, which allows depositing the channel material 704 within the thermal budgets imposed on back end fabrication to avoid damaging other components, e.g., front end components such as the logic devices.
The conductive node 710 is a conductive material that couples an S/D contact to a set of capacitors 114. In this example, the conductive node 710 also forms one electrode (e.g., the C1 electrode shown in
Each of the conductive layers 712-1 through 712-6 may be considered to be in a separate capacitor layer of the device illustrated in
In this example, each conductive layer 712-1 through 712-6 is coupled to a respective conductive via 716-1 through 716-6. Each of the conductive vias 716 extends down from a front side of the device. The conductive via 716-1 is coupled to the top conductive layer 712-1 (or plateline) on the highest capacitor layer, and each subsequent conductive via 716-2 through 716-6 is coupled to the next conductive layer 712 (or plateline) in a lower capacitor layer. For example, the conductive via 716-2 extends through the capacitor layer that includes the conductive layer 712-1, but is not coupled to the conductive layer 712-1. The conductive via 716-6 extends through the capacitor layers of each of the conductive layers 712-1 through 712-5 to connect to the conductive layer 712-6. The conductive vias 716-4 through 716-6 also extend through the support structure 702 and through a device layer that includes the access transistors 112.
The legend in
In this example, in the access transistor 112, a first S/D contact 708 (e.g., a source contact) on the left of the gate 706 may be coupled to a BL, as illustrated in
The conductive node 710 is a conductive material that couples an S/D contact to a set of capacitors 114. In this example, the conductive node 710 also forms one electrode (e.g., the C1 electrode shown in
Each of the conductive layers 712-1 through 712-6 may be considered to be in a separate capacitor layer of the device illustrated in
In this example, each conductive layer 712-1 through 712-6 is coupled to a single via 716. The conductive layers 712-1 through 712-6 may be considered a single plateline 160, or coupled to a single plateline (e.g., the via 716 is the plateline 160), in the circuit diagram shown in
13 provide cross-sections of two example arrangement of access transistors with capacitors over and under the access transistors, where capacitors in different layers are coupled to different platelines, and the platelines include stacked vias, according to some embodiments of the present disclosure. These arrangements are similar to the arrangement shown in
13 illustrates another embodiment in which the conductive vias 716-4 through 716-6 stop at the front side of the support structure 701, and each of the conductive vias 716-4 through 716-6 is coupled to a second conductive via 1002-4 through 1002-6 that connects to the respective conductive layer 712-4 through 712-6. As in
In this example, each conductive layer 712-1 through 712-3 over the device layer is coupled to a respective conductive via 716-1 through 716-3. Each of the conductive vias 716 extends down from a front side of the device. The conductive via 716-1 is coupled to the top conductive layer 712-1 (or plateline) on the highest capacitor layer, and each subsequent conductive via 716-2, 716-3 is coupled to the next conductive layer 712 (or plateline) in a lower capacitor layer. For example, the conductive via 716-2 extends through the capacitor layer that includes the conductive layer 712-1, but is not coupled to the conductive layer 712-1.
Each conductive layer 712-4 through 712-6 below the device layer is coupled to a respective backside conductive via 1302-4 through 1302-6. Each of the backside conductive vias 1302 extends upwards from a back side of the device. The conductive via 1302-6 is coupled to the bottom conductive layer 1302-6 (or plateline) on the lowest capacitor layer, and each subsequent conductive via 1302-5, 1302-4 is coupled to the next conductive layer 712 (or plateline) in a higher capacitor layer. For example, the conductive via 1302-5 extends through the capacitor layer that includes the conductive layer 712-6, but is not coupled to the conductive layer 712-6.
In this example, the conductive vias 716 and 1302 do not extend through the support structure 702 or through a device layer that includes the access transistors 112. Using backside conductive vias 1302 to access the backside conductive layers consumes less surface area of the device than using the frontside conductive vias 716-4 through 716-6 as illustrated in
Arrangements with one or more IC devices implementing memory with one access transistor for multiple capacitors as disclosed herein may be included in any suitable electronic device.
Arrangements with one or more IC devices implementing memory with one access transistor for multiple capacitors as disclosed herein may be included in any suitable electronic device.
The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the IC devices implementing memory with one access transistor for multiple capacitors as described herein). In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies 2256 may include one or more IC devices implementing memory with one access transistor for multiple capacitors, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any IC devices implementing memory with one access transistor for multiple capacitors.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include embedded memory, e.g., one or more IC devices implementing memory with one access transistor for multiple capacitors as described herein.
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an integrated circuit (IC) device including a device layer including an access transistor; a first plurality of capacitor layers over the device layer, the first plurality of capacitor layers including a first plurality of capacitors, each of the first plurality of capacitors coupled to a source or drain of the access transistor; and a second plurality of capacitor layers under the device layer, the second plurality of capacitor layers including a second plurality of capacitors, each of the second plurality of capacitors coupled to the source or drain of the access transistor.
Example 2 provides the IC device of example 1, where a first via is coupled to a first capacitor layer of the second plurality of capacitor layers, and a second via is coupled to a second capacitor layer of the second plurality of capacitor layers.
Example 3 provides the IC device of example 2, where the first via extends through the first plurality of capacitor layers and through the device layer.
Example 4 provides the IC device of example 3, where the second via extends through the first plurality of capacitor layers, through the device layer, and through the first capacitor layer.
Example 5 provides the IC device of example 2, where the first via extends through the device layer, and the first via is coupled to a third via over the first via, the third via extending through the first plurality of capacitor layers.
Example 6 provides the IC device of example 2, where the first via is a backside via that extends in a direction away from the device layer.
Example 7 provides the IC device of example 6, where the first capacitor layer is between the device layer and the second capacitor layer, and the first via extends through the second capacitor layer.
Example 8 provides the IC device of example 1, where a via is coupled to a first capacitor layer of the second plurality of capacitor layers, and the via is coupled to a second capacitor layer of the second plurality of capacitor layers.
Example 9 provides the IC device of example 8, where the via extends through the first plurality of capacitor layers and through the device layer.
Example 10 provides the IC device of example 8, where the via is a first via that extends through the device layer, and the first via is coupled to a second via over the first via, the second via extending through the first plurality of capacitor layers.
Example 11 provides the IC device of example 8, where the via is a backside via that extends in a direction away from the device layer.
Example 12 provides a memory device including an access transistor; a first plurality of capacitors over the access transistor, the first plurality of capacitors coupled to a source or drain of the access transistor, and each of the first plurality of capacitors coupled to a respective one of a first plurality of platelines; and a second plurality of capacitors under the access transistor, the second plurality of capacitors coupled to the source or drain of the access transistor, and each of the second plurality of capacitors coupled to a respective one of a second plurality of platelines.
Example 13 provides the memory device of example 12, where a first plateline of the second plurality of platelines is coupled to a first via, and a second plateline of the second plurality of platelines is coupled to a second via.
Example 14 provides the memory device of example 13, where the first via extends through a layer of the memory device including the access transistor, and the second via extends through the layer of the memory device including the access transistor.
Example 15 provides the memory device of example 14, where the first via is coupled to a third via over the first via, the third via extending through layers of the memory device including the first plurality of capacitors.
Example 16 provides the memory device of example 13, where the first via is a backside via that extends in a direction away from the access transistor.
Example 17 provides a memory device including an access transistor; a first plurality of capacitors over the access transistor, the first plurality of capacitors coupled to a source or drain of the access transistor, and each of the first plurality of capacitors coupled to a first plateline; and a second plurality of capacitors under the access transistor, the second plurality of capacitors coupled to the source or drain of the access transistor, and each of the second plurality of capacitors coupled to a second plateline.
Example 18 provides the memory device of example 17, where the second plateline is coupled to a via that extends through a layer of the memory device including the access transistor.
Example 19 provides the memory device of example 18, where the via further extends through layers of the memory device including the first plurality of capacitors.
Example 20 provides the memory device of example 17, where the second plateline is coupled to a via that extends in a direction away from the access transistor.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
