Patent Grant
8653832
The present invention relates to active matrix arrays and elements thereof. In a particular aspect, the present invention relates to digital microfluidics, and more specifically to AM-EWOD. Electrowetting-On-Dielectric (EWOD) is a known technique for manipulating droplets of fluid on an array. Active Matrix EWOD (AM-EWOD) refers to implementation of EWOD in an active matrix array, for example by using thin film transistors (TFTs).
The contact angle θ is thus a measure of the hydrophobicity of the surface. Surfaces may be described as hydrophilic if θ<90 degrees or hydrophobic if θ>90 degrees, and as more or less hydrophobic/hydrophilic according to the difference between the contact angle and 90 degrees.
If the droplet consists of an ionic material, it is well known that it is possible to change the hydrophobicity of the surface by the application of an electric field. This phenomenon is termed electrowetting. One means for implementing this is using the method of electrowetting on dielectric (EWOD), shown in
A lower substrate 25 has disposed upon it a conductive electrode 22, with an insulator layer 20 deposited on top of that. The insulator layer 20 separates the conductive electrode 22 from the hydrophobic surface 16 upon which the droplet 4 sits. By applying a voltage V to the conductive electrode 22, the contact angle θ 6 can be adjusted. An advantage of manipulating contact angle θ 6 by means of EWOD is that the power consumed is low, being just that associated with charging and discharging the capacitance of the insulator layer 20.
The above background art is all well known and a more detailed description can be found in standard textbooks, e.g. “Introduction to Microfluidics”, Patrick Tabeling, Oxford University Press, ISBN 0-19-856864-9, section 2.8.
U.S. Pat. No. 6,565,727 (Shenderov, issued May 20, 2003) discloses a passive matrix EWOD device for moving droplets through an array. The device is constructed as shown in
U.S. Pat. No. 6,911,132 (Pamula et al, issued Jun. 28, 2005) discloses an arrangement, shown in
U.S. Pat. No. 7,255,780 (Shenderov, issued Aug. 14, 2007) similarly discloses a passive matrix EWOD device used for carrying out a chemical or biochemical reaction by combining droplets of different chemical constituents.
It may be noted that it is also possible, albeit generally not preferred, to implement an EWOD system to transport droplets of oil immersed in an aqueous ionic medium. The principles of operation are very similar to as already described, with the exception that the oil droplet is attracted to the regions where the conductive electrode is held at low potential.
When performing droplet operations it is in general very useful to have some means of sensing droplet position, size and constitution. This can be implemented by a number of means. For example an optical means of sensing may be implemented by observing droplet positions using a microscope. A method of optical detection using LEDs and photo-sensors attached to the EWOD substrate is described in Lab Chip, 2004, 4,310-315.
One particularly useful method of sensing is measuring the electrical impedance between an electrode 38 of the lower (patterned) conductive electrode 22 and the electrode 28 of the top substrate.
EWOD devices have been identified as a promising platform for Lab-on-a-chip (LoaC) technology. LoaC technology is concerned with devices which seek to integrate a number of chemical or biochemical laboratory functions onto a single microscopic device. There exists a broad range of potential applications of this technology in areas such as healthcare, energy and material synthesis. Examples include bodily fluid analysis for point-of-care diagnostics, drug synthesis, proteomics, etc.
A complete LoaC system could be formed, for example, by an EWOD device to other equipment, for example a central processing unit (CPU) which could be configured to perform one or more multiple functions, for example:
Thin film electronics based on thin film transistors (TFTs) is a very well known technology which can be used, for example, in controlling Liquid Crystal (LC) displays. TFTs can be used to switch and hold a voltage onto a node using the standard display pixel circuit shown in
Many modern displays use an Active Matrix (AM) arrangement whereby a switch transistor is provided in each pixel of the display. Such displays often also incorporate integrated driver circuits to supply voltage pulses to the row and column lines (and thus program voltages to the pixels in an array). These are realised in thin film electronics and integrated onto the TFT substrate. Circuit designs for integrated display driver circuits are very well known. Further details on TFTs, display driver circuits and LC displays can be found in standard textbook, for example “Introduction to Flat Panel Displays”, (Wiley Series in Display Technology, WileyBlackwell, ISBN 0470516933).
U.S. Pat. No. 7,163,612 (Sterling et al., issued Jan. 16, 2007) describes how TFT-based electronics may be used to control the addressing of voltage pulses to an EWOD array using circuit arrangements very similar to those employed in AM display technologies.
Such an approach may be termed “Active Matrix Electrowetting on Dielectric” (AM-EWOD). There are several advantages in using TFT-based electronics to control an EWOD array, namely:
A further advantage of using TFT based electronics to control an AM-EWOD array is that, in general, TFTs can be designed to operate at much higher voltages than transistors fabricated in standard CMOS processes. However the large AM-EWOD programming voltages (20-60V) can in some instances still exceed the maximum voltage ratings of TFTs fabricated in standard display manufacturing processes. To some extent it is possible to modify the TFT design to be compatible with operation at higher voltages, for example by increasing the device length and/or adding Gate-Overlap-Drain (GOLD) or Lightly Doped Drain (LDD) structures. These are standard techniques for improving Metal-On-Semiconductor (MOS) device reliability which can be found described, for example, in “Hot Carrier Effects in MOS Devices”, Takeda, Academic Press Inc., ISBN 0-12-682240-9, pages 40-42. However such modifications to device design may impair the TFT performance. For example, structural modifications to improve reliability may increase device self resistance and inter-terminal capacitances. The effects of this are particularly deleterious for devices which are required to operate at high speed or to perform analogue circuit functions. It is therefore desirable to restrict the use of modified high voltage devices to only those functions for which a high voltage capability is necessary, and to design driver circuits such that as few devices as possible are required to operate at the highest voltages.
Fluid manipulation by means of electrowetting is also a well known technique for realizing a display. Electronic circuits similar or identical to those used in conventional Liquid Crystal Displays (LCDs) may be used to write a voltage to an array of EW drive electrodes. Coloured droplets of liquid are located at the EW drive electrodes and move according the programmed EW drive voltage. This in turn influences the transmission of light through the structure such that the whole structure functions as a display. An overview of electrowetting display technology can be found in “Invited Paper: Electro-wetting Based Information Displays”, Robert A. Hayes, SID 08 Digest pp 651-654.
In recent years there has been much interest in realising AM displays with an array based sensor function. Such devices can be used, for example as user input devices, e.g. for touch-screen applications. One such method for user interaction is described in US20060017710 (Lee et al., published Jan. 26, 2006) and shown in
U.S. Pat. No. 7,163,612 noted above also describes how TFT-based sensor circuits may be used with an AM-EWOD, e.g. to determine drop position. In the arrangement described there are two TFT substrates, the lower one being used to control the EWOD voltages, and the top substrate being used to perform a sensor function.
A number of TFT based circuit techniques for writing a voltage to a display pixel and measuring the capacitance at the pixel are known. US20060017710 discloses one such an arrangement. The circuit is arranged in two parts which are not directly connected electrically, shown
A disadvantage of the above circuit is that there is no provision of any DC current path to the sense node 102. As a result the potential of this node may be subject to large pixel-to-pixel variations, since fixed charge at this node created during the manufacturing process may be variable from pixel-to-pixel. An improvement to this circuit is shown in
In general it may be noted that in this application, both the value of the LC capacitance and the change in capacitance associated with touch are very small (of order a few fF). One consequence of this is that reference capacitor CS 98 can also be made very small (typically a few fF). The small LC capacitance also makes changes difficult to sense. British applications GB 0919260.0 and GB 0919261.8 describe means of in-pixel amplification of the small signals sensed. However in an EWOD device the capacitances presented by droplets are much larger and amplification is generally not required.
As well as implementing sensor pixel circuits onto a TFT substrate it is also well known to integrate sensor driver circuits and output amplifiers for the readout of sensor data onto the same TFT substrate, as described for example for an imager-display in “A Continuous Grain Silicon System LCD with Optical Input Function”, Brown et al. IEEE Journal of Solid State Circuits, Vol. 42, Issue 12, December 2007 pp 2904-2912. The same reference also describes how calibration operations may be performed to remove fixed pattern noise from the sensor output.
There are several methods that may be used to form a capacitor circuit element in a thin film manufacturing process as would be used for example to manufacture a display. Capacitors can be formed for example using the source and gate metal layers as the plates, these layers being separated by an interlayer dielectric. In situations where it is important to keep the physical layout footprint of the capacitor it is often convenient to use a metal-oxide-semiconductor (MOS) capacitor as described in standard textbooks, e.g. Semiconductor Device Modeling for VLSI, Lee et al., Prentice-Hall, ISBN 0-13-805656-0, pages 191-193. A disadvantage of MOS capacitors is that the capacitance becomes a function of the terminal biases if the potentials are not arranged so that the channel semiconductor material is completely in accumulation.
A known lateral device type which can be realised in thin film processes is a gated P-I-N diode 144, shown
The gated P-I-N diode 144 may be configured as a type of MOS capacitor by connecting the anode and cathode terminals together to form one terminal of the capacitor, and by using the gate terminal 140 to form the other terminal.
By connecting the gated P-I-N diode 144 in this way it functions in a similar way to the MOS capacitor as already described, with the important difference that most of the channel region remains accumulated with carriers almost regardless of the voltage between the terminals. The operation of the gated P-I-N diode 144 connected in this way is illustrated in
It is also possible to form a voltage dependent capacitor from a gated P-I-N diode 144, by connecting a bias voltage to the anode terminal 137 of the device relative to the cathode terminal 138. The bias applied, −VX, should be chosen such that the gated P-I-N diode 144 remains reverse biased.
In both AM-EWOD and AM displays a number of possible alternative configurations for storing a programmed write voltage within a pixel are possible. For example an SRAM cell can be used to store the programmed voltage as is very well known and described in standard text books, for example “VLSI Design Techniques for Analog and Digital Circuits”, Geiger et al, McGraw-Hill, ISBN 0-07-023253-9, Section 9.8.
An alternative technology for implementing droplet microfluidics is dielectrophoresis. Dielectrophoresis is a phenomenon whereby a force may be exerted on a dielectric particle by subjecting it to a varying electric field. An introduction may be found in “Introduction to Microfluidics”, Patrick Tabeling, Oxford University Press (January 2006), ISBN 0-19-856864-9, pages 211-214. “Integrated circuit/microfluidic chip to programmably trap and move cells and droplets with dielectrophoresis”, Thomas P Hunt et al, Lab Chip, 2008, 8,81-87 describes a silicon integrated circuit (IC) backplane to drive a dielectropheresis array for digital microfluidics. This reference also includes an array-based integrated circuit for supplying drive waveforms to array elements.
The invention relates to an AM-EWOD device with an array based integrated impedance sensor for sensing the location, size and constitution of ionic droplets. The preferred pixel circuit architecture utilises an AC coupled arrangement to write the EW drive voltage to the EW drive element and sense the impedance at the EW drive element.
The advantages of including an impedance sensor capability in an AM-EWOD device are as follows:
The advantages of integrating an impedance sensor capability into the AM-EWOD drive electronics are as follows:
The advantages of the AC coupled arrangement disclosed in the preferred embodiments for writing an EW drive voltage to the EW drive element and sensing the impedance at the EW drive element are as follows:
According to an aspect of the invention, an array element circuit with an integrated impedance sensor is provided. The array element circuit includes an array element which is controlled by application of a drive voltage by a drive element; writing circuitry for writing the drive voltage to the drive element; and sense circuitry for sensing an impedance presented at the drive element.
According to another aspect, the array element is a hydrophobic cell having a surface of which the hydrophobicity is controlled by the application of the drive voltage by the drive element, and the sense circuitry senses the impedance presented at the drive element by the hydrophobic cell.
According to another aspect, the writing circuitry is configured to perturb the drive voltage written to the drive element; the sense circuitry is configured to sense a result of the perturbation of the drive voltage written to the drive element, the result of the perturbation being dependent upon the impedance presented at the drive element; and the sense circuitry includes an output for producing an output signal a value of which represents the impedance presented at the drive element.
In accordance with another aspect, the sense circuitry is AC coupled to the drive element.
In accordance with another aspect, the drive element includes a node between the hydrophobic cell and a capacitor which stores the written drive voltage; and the sense circuitry includes a sensor row select line connected to the capacitor, the sensor row select line serving to provide at least one pulse to the node via the capacitor in order to sense the impedance presented at the drive element.
In yet another aspect, the capacitor is formed by a gated diode.
According to another aspect, the sense circuitry comprises a sense node AC coupled to the drive element; and the sense circuitry further includes reset circuitry for resetting a voltage at the sense node prior to sensing the impedance presented at the drive element.
According to another aspect, the reset circuitry comprises a pair of diodes connected in series with the sense node therebetween and connected at opposite ends to corresponding reset lines.
In accordance with another aspect, the reset circuitry includes at least one transistor having a gate coupled to a reset line for selectively coupling the sense node to a reset potential.
In still another aspect, the array element circuit including a counter-substrate and the impedance presented at the drive element representing the impedance between the drive element and the counter-substrate.
According to another aspect, an active-matrix device is provided which includes a plurality of array element circuits arranged in rows and columns; a plurality of source addressing lines each shared between the array element circuits in corresponding same columns; a plurality of gate addressing lines each shared between the array element circuits in corresponding same rows; and a plurality of sensor row select lines each shared between the array element circuits in corresponding same rows. Each of the plurality of array element circuits includes an array element which is controlled by application of a drive voltage by a drive element; writing circuitry for writing the drive voltage to the drive element, the writing circuitry being coupled to a corresponding source addressing line and gate addressing line among the plurality of source addressing lines and gate addressing lines; and sense circuitry for sensing an impedance presented at the drive element, the sense circuitry being coupled to a corresponding sensor row select line.
In yet another aspect, the array elements are hydrophobic cells having a surface of which the hydrophobicity is controlled by the application of the drive voltage by the corresponding drive element, and the corresponding sense circuitry senses the impedance presented at the drive element by the hydrophobic cell.
According to another aspect, with respect to each of the plurality of array element circuits: the writing circuitry is configured to perturb the drive voltage written to the drive element; the sense circuitry is configured sense a result of the perturbation of the drive voltage written to the drive element, the result of the perturbation being dependent upon the impedance presented at the drive element; and the sense circuitry includes an output for producing an output signal a value of which represents the impedance presented at the drive element.
In another aspect, the device includes a plurality of sensor output lines each shared between the array element circuits in corresponding same columns, and the outputs of the plurality of array element circuits are coupled to a corresponding sensor output line.
With yet another aspect, each of the plurality of array element circuits the sense circuitry is AC coupled to the drive element.
In still another aspect, with respect to each of the plurality of array element circuits: the drive element includes a node between the hydrophobic cell and a capacitor which stores the written drive voltage; and the corresponding row select line is connected to the capacitor, the sensor row select line serving to provide at least one pulse to the node via the capacitor in order to sense the impedance presented at the drive element.
According to another aspect, with respect to each of the plurality of array element circuits: the sense circuitry comprises a sense node AC coupled to the drive element; and the sense circuitry further comprises reset circuitry for resetting a voltage at the sense node prior to sensing the impedance presented at the drive element.
According to another aspect, the device includes a counter-substrate shared by the array element circuits, and the impedance presented at the corresponding drive element representing the impedance between the corresponding drive element and the counter-substrate.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
In the annexed drawings, like references indicate like parts or features:
The first embodiment is shown in
Referring again to
Each array element contains an EW drive electrode 152 to which a voltage VWRITE can be programmed. Also shown is a load element represented by capacitor CL 154. The capacitor CL 154 specifically represents the impedance between the EW drive electrode 152 and the counter-substrate 36, and thus represents the impedance presented by the hydrophobic cell included in the array element. The value of capacitor CL 154 is dependent on the presence of, size of and constitution of any liquid droplet located at the hydrophobic cell within that particular array element within the array.
The circuit is connected as follows:
The source addressing line 62 is connected to the drain of transistor 68. The gate addressing line 64 is connected to the gate of transistor 68. The source of transistor 68 is connected to the EW drive electrode 152. The source addressing line 62, transistor 68, gate addressing line 64 and storage capacitor CS 58 make up writing circuitry for writing a drive voltage to the EW drive electrode 152 as will be further described herein. Capacitor CS 58 is connected between the EW drive electrode 152 and the sensor row select line RWS 104. Coupling capacitor CC 146 is connected between the EW drive electrode 152 and the gate of transistor 94. The anode of the diode 148 is connected to the reset line 108. The cathode of the diode 148 is connected to the gate of transistor 94 and to the anode of diode 202. The cathode of diode 202 is connected to the reset line RSTB 200. The drain of transistor 94 is connected to the VDD power supply line 150. The source of transistor 94 is connected to the sensor output line COL 106 shared between the array elements of the same column.
The operation of the circuit is as follows:
In operation the circuit performs two basic functions, namely (i) writing a voltage to the drive element comprising the EW drive electrode 152 so as to control the hydrophobicity of the hydrophobic cell within the array element; and (ii) sensing the impedance presented by the hydrophobic cell at the drive element including the EW drive electrode 152.
In order to write a voltage, the required write voltage VWRITE is programmed onto the source addressing line 62 via the column driver (e.g., 78 in
In order to sense the impedance presented at the EW drive electrode 152 following the writing of the voltage VWRITE, the sense node 102 is first reset.
Specifically, sense circuitry included within the control circuitry includes reset circuitry which performs the reset operation. The reset circuitry includes, for example, the diodes 148 and 202 connected in series with sense node 102 therebetween. As noted above, the opposite ends of the diodes 148 and 202 are connected to the reset lines RST 108 and RSTB 200, respectively. The reset operation, if performed, occurs by taking the reset line RST 108 to its logic high level, and the reset line RSTB 200 to its logic low level. The voltage levels of the reset lines RST 108 and RSTB 200 are arranged so that the logic low level of reset line RSTB 200 and the logic high level of the reset line RST 108 are identical, a value VRST. The value VRST is chosen so as to be sufficient to ensure that transistor 94 is turned off at this voltage. When the reset operation is effected, one of diodes 148 or 202 is forward biased, and so the sense node 102 is charged/discharged to the voltage level VRST. Following the completion of the reset operation, the reset line RST 108 is taken to its logic low level and the reset line RSTB 200 to its logic high level. The voltage levels of the reset line RST 108 low logic level and reset line RSTB 200 high logic level are each arranged so as to be sufficient to keep both diodes 148 and 202 reversed biased for the remainder of the sense operation.
The sense circuitry in the embodiment of
Where
CTOTAL=CS+CC+CL (equation 3)
In general the capacitive components are sized such that storage capacitor CS is of similar order in value to the load impedance as represented by capacitor CL in the case when a droplet is present, and such that the storage capacitor CS is 1-2 orders of magnitude larger in value than the coupling capacitor CC. The perturbation ΔVWRITE in the voltage of the EW drive electrode 152 due to the pulse ΔVRWS on the sensor row select line RWS 104 then also results in a perturbation ΔVSENSE of the potential at the sense node 102 due to the effects of the coupling capacitor CC. The perturbation ΔVSENSE in potential at the sense node 102 is given approximately by
where CDIODE represents the capacitance presented by diode 148 and CT represents the parasitic capacitance of transistor 94. In general the circuit is designed so that the coupling capacitor CC is larger than the parasitic capacitances CDIODE and CT. As a result the perturbation ΔVSENSE of the voltage at the sense node 102 is in general similar to the perturbation ΔVWRITE of the write node voltage at the EW drive electrode 152 (though this is not necessarily required to be the case). Capacitor CS has a dual function; it functions as a storage capacitor, storing an electrowetting voltage is written to the array element. It also functions as a reference capacitor when sensing impedance; the impedance is measured essentially by comparing CS to the droplet capacitance Cdrop.
The overall result of pulsing the sensor row select line RWS 104 is that the voltage potential at the sense node 102 is perturbed by an amount ΔVSENSE that depends on the impedance represented by capacitor CL (which again is dependent on the presence of, size of and constitution of any droplet located at the particular array element) for the duration of the RWS pulse. As a result the transistor 94 may be switched on to some extent during the RWS operation in which the RWS pulse is applied to the sensor row select line RWS 104. The sensor output line COL 106 is loaded by a suitable biasing element (e.g. a resistor or a transistor, not shown), which may be common to each array element in the same column. Transistor 94 thus operates as a source follower and the output voltage appearing at the sensor output line COL 106 during the row select operation is a function of the impedance represented by capacitor CL. This voltage may then be sampled and read out by a second stage amplifier using well known techniques, as for example described for an imager-display as referenced in the prior art section. The array element circuit of
It may be noted that following the sense operation when the voltage on the sensor row select line RWS 104 is returned to its original value, the potential of the EW drive electrode 152 returns to substantially the same value as prior to the sense operation. In this regard the sensor operation is non-destructive; indeed any voltage written to the EW drive electrode 152 is only disturbed for the duration of the RWS pulse on the sensor row select line RWS 104 (which is typically only for a few microseconds, for example). It may also be noted that in this arrangement there is no additional DC leakage path introduced to the EW drive electrode 152.
It may also be noted that it is not in all cases necessary to perform the reset operation using reset lines RST 108 and RSTB 200 at the start of every sense operation. In some instances it may be adequate and/or preferable to reset the sense node 102 on a more occasional basis. For example, if a series of sensor measurements are to be made a single reset operation could be performed before making the first measurement but with no reset performed between measurements. This may be advantageous because the potential at the sense node 102 immediately prior to each measurement would not be subject to variability due to the imperfections of the reset operation. Variability in the reset level could be affected by factors such as ambient illumination and temperature which may be subject to variations during the course of the measurements.
It may also be noted that in certain circumstances it may also be advantageous to perform the reset operation whilst the AM-EWOD write voltage VWRITE is being written to the EW drive electrode 152 via the source addressing line 62.
This is the case, for example, if one wishes to perform a sense operation on array elements within one row of the array whilst simultaneously writing a voltage to the EW drive electrode 152 of array elements in a different row. This is because during the write operation, if a step in voltage occurs at the EW drive electrode 152, then a proportion of this voltage will couple via coupling capacitor CC 146 to the sense node 102. This may have the effect of turning on to some extent transistor 94 in the row to which a write voltage VWRITE is being written. This will in turn influence the potential of the sensor output line COL 106, and thus affect the sensor function of the row being sensed. This difficulty can be avoided by performing a reset operation on the row being written, thus pinning the potential of the sense node 102 for elements in this row and preventing transistor 94 from being turned on.
The advantages of this embodiment are as follows:
It may be noted that none of these advantages would be realised in the case where the sense node 102 was DC coupled to the EW drive electrode 152 (for example by replacing coupling capacitor CC 146 with a short circuit). In this case an additional leakage path would be introduced to the EW drive electrode 152 (leakage through the reverse biased diode 148), the EW drive voltage VWRITE as written would be destroyed by performing the sense operation and high voltages would appear across the terminals of transistor 94 and diode 148.
In a typical design, the value of storage capacitor CS may be relatively large, for example several hundred femto-farads (fF). To minimise the layout area it is therefore advantageous to implement this device as a MOS capacitor.
A second embodiment of the invention is shown in
The operation of the second embodiment is identical to that of the first embodiment, where the gated P-I-N diode 144 performs the function of the capacitor CS of the first embodiment. In general the voltage levels of the pulse provided on the sensor row select line RWS 104 are arranged such that the capacitance of the gated P-I-N diode 144 is maintained at the maximum level for both the high and low levels of the RWS voltage.
The advantage of this embodiment is that by using a gated P-I-N diode 144 to perform the function of a capacitor, the voltage levels assigned to the RWS pulse are not required to be arranged so that the voltage across the device is always above a certain threshold level (in order to maintain the capacitance). This means that the voltage levels of the RWS pulse high and low levels can, for example, reside wholly within the programmed range of the EW drive voltages. The overall range of voltages required by the array element circuit as a whole is thus reduced compared to that of the first embodiment where a MOS capacitor is used to implement capacitor CS 58.
This advantage is realised whilst also maintaining a small layout footprint of the gated diode, comparable to that of a MOS capacitor. The small layout footprint may be advantageous in terms of minimising the physical size of the circuit elements in the array, for the reasons previously described. It will be apparent to one skilled in the art that this embodiment could also be implemented with the gated P-I-N diode 144 connected the other way round, i.e. with the anode and cathode terminals both connected to the EW drive electrode 152, and the gate terminal connected to the sensor row select line RWS 104.
It will be readily apparent to one skilled in the art that a number of variants to the circuits of the first and second embodiments could also be implemented. For example, the source follower transistor 94 and switch transistor 68 could both be implemented with pTFT devices rather than nTFT devices.
None of these changes substantially affect the basic operation of the circuit as described above. Therefore, further detail is omitted for sake of brevity.
The third embodiment of the invention is shown in
The reset line RST 108 in this embodiment is connected to the gate of transistor 206. The source and drain terminals of transistor 206 are connected to the sense node 102 and the power supply line VRST 208 respectively.
The operation of this embodiment is as described for the first embodiment except in the performance of the reset operation. In this embodiment reset is performed by taking the reset line RST 108 to a logic high level. This has the effect of turning on transistor 206 such that the potential of the sense node 102 is charged/discharged to the reset potential on power supply line VRST 208. When the reset operation is not being performed, the reset line RST 108 is switched to logic low so as to switch transistor 206 off.
An advantage of this embodiment over the first embodiment is that it can be implemented without the need for any diode elements (diodes may not be available as standard library components within the manufacturing process). A further advantage of this embodiment is that the array element circuit requires only n-type TFT components and is thus suitable for implementation within a single channel manufacturing process (where only n-type devices are available).
The fourth embodiment is shown in
This embodiment is as the first embodiment
The reset line RST 108 is connected to the gate of transistor 206. The reset line RSTB 200 is connected to the gate of transistor 205. The source of transistors 205 and 206 are connected together and to the sense node 102. The drain of transistors 205 and 206 are connected together and to the power supply line VRST 208.
The operation of this embodiment is as described for the first embodiment in
The advantages of this embodiment are as follows:
The fifth embodiment of the invention is shown in
The operation of the array element circuit is similar to the first embodiment. Initially the sense node 102 is reset by switching the line RST/RWS 170 to a voltage level V1 sufficient to forward bias diode 148 and the connection to the reset line RSTB 200 to a voltage sufficient to forward bias diode 202. The line RST/RWS 170 is then switched to a lower voltage level V2 such that the diode 148 is reverse biased, and reset line RSTB 200 is taken to a high value such that diode 202 is reverse biased. During the row select operation, the line RST/RWS 170 is then switched to a third voltage level V3, creating a voltage step of magnitude V3−V2, which in turn perturbs the voltage at the EW drive electrode 152 and sense node 102, thus enabling the impedance CL to be measured. A requirement for the circuit to operate properly is that voltage levels V2 and V3 must be less than V1 and so not forward bias diode 148 during the row select operation.
An advantage of this embodiment is that the number of voltage lines required by the array element is reduced by one compared with the first and second embodiments, whilst also maintaining the capability to perform a reset operation.
The sixth embodiment is shown in
An advantage of the sixth embodiment in comparison to the first embodiment is that the number of voltage lines required by the array element is reduced by one. An advantage of the sixth embodiment compared to the fifth embodiment is that only two different voltage levels need to be applied to the line RWS/RSTB line 204 during operation. This has the advantage of simplifying the control circuits required to drive the connection.
It will be apparent to one skilled in the art that the fifth and sixth embodiments could also be implemented where the source follower transistor if a p-type transistor and the row select operation is implemented by a negative going pulse applied to the RWS/RST, RWS/RSTB lines.
The seventh embodiment of the invention is shown in
The operation of the circuit is essentially similar to that of the second embodiment with the exception that the bias supply VBR 172 is maintained at a bias VX below that of the bias voltage of the sensor row select line RWS 104 throughout the operation of the circuit. This has the effect of making the gated P-I-N diode 144 function like a voltage dependent capacitor, having a bias dependence that is a function of VX, as described in prior art.
By choosing the range of operation of the RWS pulse high and low levels and an appropriate value of VX it is therefore possible to make the gated P-I-N diode 144 function as a variable capacitor whose value depends upon the choice of VX. The overall circuit functions as described in the second embodiment, where the gated P-I-N diode 144 is a capacitor whose capacitance can be varied. The circuit can therefore effectively operate in different ranges according to whether this capacitance is arranged to take a high or a low value
An advantage of the circuit of this embodiment is that a higher range of droplet impedances can be sensed than may be the case if the capacitance is implemented as a fixed value. A further advantage is that a variable capacitor may be implemented by means of no additional circuit components and only one additional bias line.
Whilst this embodiment describes a particularly advantageous implementation of a variable capacitance, it will be apparent to one skilled in the art that there are multiple other methods for implementing variable or voltage dependent capacitors. For example, additional TFTs which function as switches could be provided. These could be configured to switch in or out of the circuit additional capacitor elements. These could be arranged either in series or in parallel with capacitor CS.
The eighth embodiment of the invention is as any of the previous embodiments where the voltage pulse applied to the sensor row select line RWS 104 is arranged to consist of N multiple pulses. This is shown in
The operation of the circuit is then otherwise identical to as was described in the first embodiment. However the response of the array element circuit to the modified RWS pulse 180 may differ in accordance with the constituent components of the droplet impedance. This can be appreciated with reference to
According to this embodiment, a series of multiple impedance measurements may be made, these being performed where the number of component pulses comprising the row select pulse, N, is different for each individual measurement. By determining the sensor output for two or more different values of N it is thus possible to measure the frequency dependence of the droplet capacitance CL. Since the insulator capacitance C, is generally known, this method can further be used to determine information regarding the impedance components Cdrop and Rdrop. Since these are related to the droplet constitution, for example its conductivity, information regarding the droplet constitution may be determined.
In this mode of operation it is useful, although not essential, to arrange the RWS pulse on the sensor row select line RWS 104 such that the total time for which this connection is at the high level is the same for each N. This ensures that the source follower transistor 94 is turned on (to an extent determined by the various impedances) for the same amount of time, regardless of the value of N.
The ninth embodiment of the invention is shown in
The circuit contains the following elements:
Connections supplied to the array element are as follows:
Each array element contains an EW drive electrode 152 to which a voltage VWRITE can be programmed. Also shown represented is a load element CL 154 representing the impedance between the EW drive electrode 152 and the counter-substrate 36. The value of CL is dependent on the presence of, size of and constitution of any droplet at the array element in the array as in the previous embodiments.
The circuit is connected as follows:
The source addressing line 62 is connected to the drain of transistor 68. The gate addressing line 64 is connected to the gate of transistor 68. The source of transistor 68 is connected to the EW drive electrode 152. Capacitor CS 190 is connected between the EW drive electrode 152 and the power supply line VSS 184. Coupling capacitor CC 146 is connected between the EW drive electrode 152 and the gate of transistor 94. The anode of the diode 148 is connected to the power supply VSS 184. The cathode of the diode 148 is connected to the gate of transistor 94. Coupling capacitor CC 146 is connected between the EW drive electrode 152 and power supply VSS 184. The drain of the switch transistor T3186 is connected to the gate of transistor 94. The source of transistor T3 is connected the power supply VSS 184. The gate of transistor T3186 is connected to the sensor row select line RWS 104. The drain of transistor 94 is connected to the sensor row select line RWS 104. The source of transistor 94 is connected to the sensor output line COL 106. The capacitor CP is connected between the sense node 102 and the power supply VSS 184.
The operation of the circuit is as follows:
In order to write a voltage, the required write voltage VWRITE is programmed onto the source addressing line 62. The gate addressing line 64 is then taken to a high voltage such that transistor 68 is switched on. The voltage VWRITE (plus or minus a small amount due to non-ideality of 68) is then written to the EW drive electrode 152 and stored on the capacitance present at this node, and in particular on capacitor CS. The gate addressing line 64 is then taken to a low level to turn off transistor 68 and complete the write operation.
In order to sense the impedance presented at the EW drive electrode 152, a voltage pulse is applied to the electrode of the counter-substrate 36. A component of this voltage pulse is then AC coupled onto the EW drive electrode 152 and on to the sense node 102. For the row of the array element to be sensed, the sensor row select line RWS 104 is taken to a high voltage level. This results in switch transistor T3186 being switched off so that there is no DC path to ground from the sense node 102. As a result the voltage coupled onto the sense node 102 results in the source follower transistor 94 being partially turned on to an extent which is in part dependent on the capacitive load of the droplet CL. The function of capacitor CP is to ensure that voltage coupled onto the sense node 102 from the pulse applied to the counter substrate is not immediately discharged by parasitic leakage through transistor 186 and diode 148. CP should therefore be sufficiently large to ensure that the potential at the sense node 102 is not unduly influenced by leakage through the transistor 186 and the diode 148 for the duration of the sense operation.
For row elements not being sensed, transistor 186 remains switched on so that the component of the voltage pulse from the counter-substrate 36 coupled onto the sense node 102 is immediately discharged to VSS.
To ensure successful operation, the low level of the RWS pulse and the bias supply VSS must be arranged such that the source follower transistor 94 remains switched off when the RWS pulse on the sensor row select line RWS 104 is at the low level.
An advantage of this embodiment compared to the first embodiment is that one fewer voltage supply line per array element is required.
The tenth embodiment of the invention is shown in
The circuit contains the following elements:
Connections supplied to the array element are as follows:
Each array element contains an EW drive electrode 152 to which a voltage VWRITE can be programmed. Also shown represented is a load element CL 154 representing the impedance between the EW drive electrode and the counter-substrate 36. The value of CL is dependent on the presence of, size of and constitution of any droplet at the located at that array element within the array.
The circuit is connected as follows:
The source addressing line 62 is connected to the input of the SRAM cell 194. The gate addressing line 64 is connected to the enable terminal of the SRAM cell 194. The output of the SRAM cell is connected to the drain of transistor 196. The source of transistor 196 is connected to the EW drive electrode 152. The sensor enable line SEN 198 is connected to the gate of transistor 196. Capacitor CS 58 is connected between the source of 196 and the sensor row select line RWS 104. Coupling capacitor CC 146 is connected between the source of 196 and the gate of transistor 94. The anode of the diode 148 is connected to the reset line RST 108. The cathode of the diode 148 is connected to the gate of transistor 94 and to the anode of diode 202. The cathode of diode 202 is connected to the reset line RSTB 200. The drain of transistor 94 is connected to the VDD power supply line 150. The source of transistor 94 is connected to the sensor output line COL 106.
The operation of the circuit is similar to the first embodiment, except that a digital value is written to the EW drive electrode 152. To write a voltage to the EW drive electrode 152, the sensor enable line SEN 198 is taken high to switch on transistor 196. The required digital voltage level (high or low) is programmed on to the source addressing line 62. The gate addressing line 64 is then set high to enable the SRAM cell 194 of the row being programmed and write the desired logic level onto the SRAM cell 194. The gate addressing line 64 is then taken low to complete the writing operation.
To perform a sensor operation the sensor enable line SEN 198 is taken low. The rest of the sensor portion of the circuit then operates in the same way as was described for the first embodiment of the invention. Following completion of the sensor operation the sensor enable line SEN 198 can be taken high again so that the programmed voltage stored on the SRAM cell 194 can be once again written to the EW drive electrode 152.
An advantage of this embodiment is that by implementing the write function of the AM-EWOD device using an SRAM cell 194, the write voltage is not required to be continually refreshed. For this reason an SRAM implementation can have lower overall power consumption than implementation using a standard display pixel circuit as described in previous embodiments.
It will be obvious to one skilled in the art that an SRAM implementation of the write portion of the circuit may also be combined with any one of embodiments 2-8.
The eleventh embodiment is as any of the previous embodiments where the droplets consist of a non-polar material (e.g. oil) immersed in a conductive aqueous medium. An advantage of this embodiment is that the device may be used to control, manipulate and sense liquids which are non-polar.
It will be apparent to one skilled in the art that any of the previous embodiments can be implemented in an AM-EWOD device whereby thin film electronics are disposed upon a substrate to perform the dual functions of programming an EWOD voltage and sensing capacitance at multiple locations in an array.
Suitable technologies for integrated drive electronics and sensor output electronics have been described in the prior art section.
It will be further apparent to one skilled in the art that such an AM-EWOD device can be configured to perform one or more droplet operations as described in prior art, where the sensor function described can be used to perform any of the functions described in prior art.
It will be further apparent to one skilled in the art that the AM-EWOD device described could form part of a complete lab-on-a-chip system as described in prior art. Within such as system, the droplets sensed and/or manipulated in the AM-EWOD device could be chemical or biological fluids, e.g. blood, saliva, urine, etc, and that the whole arrangement could be configured to perform a chemical or biological test or to synthesise a chemical or biochemical compound.
Although the invention has been shown and described with respect to a certain embodiment or embodiments, equivalent alterations and modifications may occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. For example, while the present invention has been described herein primarily in the context of an EWOD device it will be appreciated that the invention is not limited to an EWOD device and may also be utilized more generally in any type of array device in which it is desirable to incorporate an integrated impedance sensor. For example, it will be apparent to one skilled in the art that the invention may also be utilized in alternative systems wherein there is a requirement to write a voltage to a drive electrode and sense the impedance at the same node. For example the invention may be applied to a droplet manipulation dielectrophoresis system such as described in the prior art section which also contains an integrated impedance sensor capability. According to another example, the invention may be applied to an electrowetting based display, as for example described in the prior art section, having an-inbuilt capability for sensing the impedance of the fluid material used to determine the optical transmission of the display. In this application the impedance sensor capability may be used, for example as a means for detecting deformity of the fluid material due to the display being touched and thus function as a touch input device. Alternatively the impedance sensor capability may be used as a means for detecting faulty array elements which do not respond in the correct manner to the applied EW drive voltage.
In particular regard to the various functions performed by the above described elements (components, assemblies, devices, compositions, etc.), the terms (including a reference to a “means”) used to describe such elements are intended to correspond, unless otherwise indicated, to any element which performs the specified function of the described element (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein exemplary embodiment or embodiments of the invention. In addition, while a particular feature of the invention may have been described above with respect to only one or more of several embodiments, such feature may be combined with one or more other features of the other embodiments, as may be desired and advantageous for any given or particular application.
Industrial Applicability
By integrating sensor drive circuitry and output amplifiers into the AM-EWOD drive electronics, the impedance can be measured at a large number of points in an array with only a small number of connections being required to be made between the AM-EWOD device and external drive electronics. This improves manufacturability and minimises cost compared to the prior art
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