Patent Grant
9761162
Field of the Invention
The present invention relates to an array substrate, a method for inspecting an array substrate, and a method for inspecting a display panel.
Description of the Background Art
A display panel is provided with an array substrate. The array substrate has a glass substrate on which a display circuit is located to form display portions. An array inspection includes a technique, which has been known, of writing electrical charge on each of pixels forming the display portion and reading the electrical charge maintained in the pixels to inspect gate signal lines and source signal lines of semiconductor switching elements for breaks and short circuits, the pixels for defects, and the semiconductor switching elements for failures. The array inspection typically causes each of inspection needles (probes) to collectively come into contact with an inspection terminal located at each of the gate signal lines and each of the source signal lines and then inputs an inspection signal to each of the gate signal lines to successively operate the semiconductor switching elements formed at each intersection while inputting an inspection signal to each of the source signal lines to write the electrical charge on the pixels.
In general, terminals (mounting terminals) for mounting semiconductor chips and flexible print cables (FPCs) in the following steps may be used as the inspection terminals, or the inspection terminals may be provided separately near the terminals. The inspection terminals are provided in this manner, allowing for the inspection of the display circuit in a range of the terminals to the display portion.
In the technique of inspecting the array substrate as described above, the inspection terminals connected to the plurality of gate signal lines and the plurality of source signal lines are probed individually, so that a probe unit (unit including a plurality of probes mounted thereon) serving as an inspection jig needs to be manufactured for each of types in which the inspection terminals are disposed differently.
Meanwhile, a panel lighting inspection is performed in a panel state. The panel state is a state in which the display panel including the array substrate and a display element is formed. For example, liquid crystals are sealed between the array substrate and a counter substrate to form a liquid crystal display panel. The panel lighting inspection displays an image on the display panel and determines whether the image is properly displayed. For example, the panel lighting inspection similar to the technique of inspecting the array substrate probes all of the inspection terminals of the source signal lines and the gate signal lines, inputs the inspection signals to the source signal lines and the gate signal lines, and then checks the image to determine whether each of the pixels performs a correct display.
In recent times, a circuit capable of collectively controlling the plurality of gate signal lines and the plurality of source signal lines is provided beforehand on the array substrate, and a collective lighting inspection that enables a specific display with the extremely small number of probes is also applied.
Unlike the inspection technique of individually probing the inspection terminals each located at the plurality of gate signal lines and the plurality of source signal lines, the technique of the collective lighting inspection eliminates influences of a resolution of a display panel and a design (such as the number of bumps) of a semiconductor chip on an inspection device, achieving general-purpose inspections at low cost.
In the above-mentioned inspection technique, a lighting inspecting circuit including a plurality of inspection semiconductor switching elements or the like has been located in a semiconductor chip mounting region including the semiconductor chip mounted therein. However, the semiconductor chip mounting region needs to be reduced in size with miniaturization of the semiconductor chip and a narrow frame of the display panel, so that the lighting inspecting circuit has conceivably been divided into a plurality thereof located in a region except for the semiconductor chip mounting region (see Japanese Patent Application Laid-Open No. 11-316389 (1999), for example).
In recent times, while a high resolution of the display panel and a high density of the semiconductor chips result in miniaturization of the mounting terminals of the semiconductor chips and the inspection terminals disposed around the mounting terminals, the intervals between the mounting terminals and the inspection terminals have had a tendency to become narrow. This makes stable probing difficult. At the same time, manufacturing the probes is also difficult.
Moreover, using the collective lighting inspecting circuit of the conventional technology enables to inspect wiring of the display portion, the semiconductor elements, and wiring from the mounting terminals of the semiconductor chips to the display portion regardless of the high resolution of the display panel and the high density of the semiconductor chips, but the lighting state actually needs to be checked. Thus, the inspections need to be performed after steps are advanced to a level that enables display. For example, in a case of a liquid crystal display apparatus, the array substrate and the counter substrate overlap each other, and the liquid crystals need to be sealed therebetween. Therefore, when a defect is found in the array substrate in the collective lighting inspection, the counter substrate, the liquid crystals, and the cost that has been spent in manufacturing are wasted. In this respect, the array inspection for a single array substrate is desired.
It is an object of the present invention to provide an array substrate capable of performing stable probing upon an array inspection.
An array substrate according to the present invention includes a plurality of first signal lines, a plurality of second signal lines, a pixel switch element, and a first array inspecting terminal. The plurality of first signal lines extend parallel to each other. The plurality of second signal lines extend parallel to each other and intersect the plurality of first signal lines. The pixel switch element is located at an intersection of each of the plurality of first signal lines and each of the plurality of second signal lines. The first array inspecting terminal is connected to two or more third signal lines of the plurality of first signal lines. To perform an inspection for a unit of the two or more third signal lines by detecting a value of a voltage or a current generated in the two or more third signal lines, the first array inspecting terminal is configured to receive an inspection signal for generating the voltage or the current.
A method for inspecting an array substrate according to the present invention is a method for inspecting an array substrate described below. The array substrate includes a plurality of first signal lines, a plurality of second signal lines, a pixel switch element, and a first array inspecting terminal. The plurality of first signal lines extend parallel to each other. The plurality of second signal lines extend parallel to each other and intersect the plurality of first signal lines. The pixel switch element is located at an intersection of each of the plurality of first signal lines and each of the plurality of second signal lines. The first array inspecting terminal is connected to two or more third signal lines of the plurality of first signal lines. In the method for inspecting an array substrate according to the present invention, an inspection signal for generating a voltage or a current in the two or more third signal lines is input to the first array inspecting terminal, and an inspection for a unit of the two or more third signal lines is performed by detecting the voltage or the current.
In the array substrate and the method for inspecting an array substrate according to the present invention, the first array inspecting terminal is connected to the two or more third signal lines. Thus, the first array inspecting terminal can be provided in a relatively great size, and thus the stable probing can be performed upon the array inspection.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
<Array Substrate Before Array Inspection>
The array substrate 1 includes a substrate (such as a transparent substrate and a glass substrate as the more detailed example), which is not shown, and various structural components described below are located on this substrate. As shown in
A plurality of gate signal lines 12a and a plurality of source signal lines 12b are located in the display region 10. The plurality of gate signal lines 12a extend parallel to each other. Hereinafter, the extending direction of the gate signal lines 12a is referred to as an X direction. The plurality of source signal lines 12b extend parallel to each other and intersect the plurality of gate signal lines 12a. For example, the plurality of source signal lines 12b extend in a Y direction substantially orthogonal to the X direction.
Also in the illustration of
Each region surrounded by the gate signal lines 12a and the source signal lines 12b corresponds to a pixel region. Pixels as a whole are formed in a matrix, for example.
A signal is input to the gate signal line 12a to turn the pixel switch element 18 on. A signal is input to the source signal line 12b in this state, and a voltage is then charged in the storage capacitor C10. The voltage charged in the storage capacitor C10 corresponds to a voltage applied to the pixel (more specifically, a display element, such as a liquid crystal, corresponding to the pixel). The display element changes display in response to the voltage.
In the illustration of
The semiconductor chip mounting regions 20a, 20b are regions in which semiconductor chips (gate driving circuit (gate driver IC) or source driving circuit (source driver IC)) are mounted. For example, the gate driving circuit (not shown) that outputs the signal to the gate signal line 12a is mounted in the semiconductor chip mounting region 20a, and the source driving circuit (not shown) that outputs the signal to the source signal line 12b is mounted in the semiconductor chip mounting region 20b.
In the illustration of
The output terminals 22a are also each connected to the common break inspecting wire 26a through the capacitor element C20a. The break inspecting wire 26a is connected to a break inspecting terminal 28a located on the array substrate 1. The capacitor elements C20a, the break inspecting wire 26a, and the break inspecting terminal 28a are used for inspecting a break in the gate signal lines 12a and the leads 24a. This will be described below in detail.
A plurality of output terminals 22b, a plurality of capacitor elements C20b, and a break inspecting wire 26b are located in the semiconductor chip mounting region 20b. The output terminals 22b are provided side by side in the X direction, for example, and are each connected to the source signal line 12b through a lead 24b. The output terminals 22b are also connected to output bumps of the semiconductor chip (source driving circuit). Thus, the semiconductor chip is electrically connected to the source signal lines 12b through the output terminals 22b and the leads 24b.
The output terminals 22b are also each connected to the common break inspecting wire 26b through the capacitor element C20b. The break inspecting wire 26b is connected to a break inspecting terminal 28b located on the array substrate 1. The capacitor elements C20b, the break inspecting wire 26b, and the break inspecting terminal 28b are used for inspecting a break in the source signal lines 12b and the leads 24b. This will be described below in detail.
The array substrate 1 is provided with array inspecting terminals 30a, 30b. The array inspecting terminals 30a are disposed in a region different from the semiconductor chip mounting region 20a and disposed on the side opposite to the semiconductor chip mounting region 20a with respect to the display region 10 in the illustration of
The array inspecting terminals 30b are disposed in a region different from the semiconductor chip mounting region 20b and disposed on the side opposite to the semiconductor chip mounting region 20b with respect to the display region 10 in the illustration of
The array inspecting terminals 30a, 30b are terminals used in an array inspection for the single array substrate 1. In the array inspection, an inspection signal is input to the gate signal lines 12a through the array inspecting terminals 30a, 30b. A specific example of the array inspection will be described below.
Also in the illustration of
Next, an array inspection method for the array substrate 1 according to the first preferred embodiment will be described.
<Array Inspection>
Here, a break inspection of the gate signal lines 12a and the leads 24a and of the source signal lines 12b and the leads 24b is described as an example of the array inspection. In addition, an inspection method disclosed in Japanese Patent Application No. JP2013-146082, for example, may be applied to this inspection, so that the specification will omit detailed descriptions and have simple descriptions.
Probes are applied to the array inspecting terminals 30a and the break inspecting terminal 28a. Then, one of the array inspecting terminals 30a and the break inspecting terminal 28a are each applied with the different potential through the probes. For example, a direct-current power supply is connected between the one array inspecting terminal 30a and the break inspecting terminal 28a.
At this time, if a path (the gate signal lines 12a, the leads 24a, the output terminals 22a, the capacitor elements C20a, and the break inspecting wire 26a) between the one the array inspecting terminal 30a and the break inspecting terminal 28a is not broken, the current flows through the path.
In the illustration of
Meanwhile, if one of the gate signal lines 12a or one of the leads 24a connected to the one array inspecting terminal 30a is broken, the current flows through only one of the paths. A value of the current at this time is smaller than a value in the case where the current flows through the two paths. Therefore, when the current is detected and is smaller than the reference value, it can be determined that the gate signal line 12a or the lead 24a connected to the one array inspecting terminal 30a is broken. The well-known inspection device including the probes can perform the detection and the determination.
It should be noted that the inspection device hardly determines which path of the two paths connected to the array inspecting terminal 30a is broken. Thus, the inspection device notifies a worker of both the paths without specifying any of the paths. The worker who receives the notification checks these paths, for example, through visual inspection to specify the broken place.
The potential is successively applied to the plurality of array inspecting terminals 30a to repeatedly perform the above-mentioned inspection. This can inspect the break in all of the gate signal lines 12a and the leads 24a.
The inspection of the source signal lines 12b and the leads 24b is similar, thereby avoiding to repeat the description.
In the conventional array inspection, gate signal lines and source signal lines are each provided with an array inspecting terminal to inspect the gate signal lines or the source signal lines one by one. This allows to minutely specify a defective place since the defect in the signal lines can be detected by determining an electrical amount (current or voltage) in the array inspection and comparing the amount with the reference value. In other words, this allows to specify the defective place without the need for the visual inspection by the worker.
On the other hand, in the first preferred embodiment, the voltage is collectively applied to the plurality of signal lines on purpose to perform the array inspection of a unit of the plurality of signal lines. Consequently, accuracy decreases in terms of specifying the defective place, but the array inspecting terminals 30a, 30b can increase in size, allowing to contribute to the stable probing. Moreover, the probes can be easily manufactured in a sufficient size. Furthermore, life of the probes can be extended.
The array inspecting terminals 30a, 30b are provided, whereby the number of array inspecting terminals can be reduced. This can increase flexibility in placement while the common placement has hardly been adopted for a plurality of types due to the problem of spacing or the like. If the plurality of types can have the same placement, the same probe unit (inspection device) can be used. Thus, a cost of inspection can be greatly reduced.
Moreover, the two or more gate signal lines or the two or more source signal lines are connected to the one array inspecting terminal to perform the array inspection, so that the number of signal lines (namely, resolution of display image) seen from the inspection device is reduced. Thus, an inspection tact can be increased by the reduced number of signal lines. Furthermore, to make efficient use of a measurement channel (measurement terminal) of the inspection device, the greater number of array substrates 1 can be inspected simultaneously in a multi-measurement that simultaneously measures the plurality of array substrates 1.
In the first preferred embodiment, the array inspecting terminal 30a is connected to the two or more gate signal lines 12a and the array inspecting terminal 30b is connected to the two or more source signal lines 12b, but any one of the array inspecting terminals 30a, 30b may only be connected to the two or more signal lines. Here, when the array inspecting terminals 30a and the array inspecting terminals 30b do not need a distinction therebetween, they are simply referred to as array inspecting terminals, and when the gate signal lines 12a and the source signal lines 12b do not need a distinction therebetween, they are also simply referred to as signal lines.
The array inspection is not limited to the inspection described above. In other words, an inspection for a unit of two or more signal lines may be performed by inputting an inspection signal to an array inspecting terminal and detecting an electrical amount generated in the two or more signal lines connected to the array inspecting terminal. A configuration of a circuit necessary for the inspection may be modified as appropriate according to a necessary array inspection. For example, an inspection and a configuration of a circuit disclosed in Japanese Patent Application No. JP2013-146082 may be applied as appropriate.
Although the signal lines connected to the array inspecting terminal include the freely-selected number thereof, the number of signal lines is preferably ten or less, for example. Thus, accuracy of the array inspection can be ensured to some extent, and a range including a defect capable of being specified can be made narrow to some extent. It is also appropriate to connect the ten or more signal lines to the array inspecting terminal in a case where it is determined that the accuracy of the array inspection is reduced and the range including the defect capable of being specified is expanded.
<Array Substrate after Array Inspection>
In this embodiment, the two or more signal lines are connected to each other through the array inspecting terminal. Thus, in this state, different signals cannot be output to the two or more signal lines. Consequently, each pixel cannot be operated individually. Therefore, after completion of the array inspection, the connection between the two or more signal lines needs to be interrupted.
As shown in
Alternatively, part of the gate signal lines 12a and part of the source signal lines 12b may be removed without cutting the array substrate 1. For example, part of each of the gate signal lines 12a between the array inspecting terminals 30a and the display region 10 is removed with, for example, a laser, and part of each of the source signal lines 12b between the array inspecting terminals 30b and the display region 10 is removed with, for example, a laser. Consequently, the connection between the array inspecting terminals 30a and the gate signal lines 12a (more specifically, the gate signal lines 12a on the display region 10 side) is interrupted, and the connection between the array inspecting terminals 30b and the source signal lines 12b (more specifically, the source signal lines 12b on the display region 10 side) is interrupted. Thus, the signal can be individually output to the gate signal lines 12a through the output terminals 22a, and the signal can be individually output to the source signal lines 12b through the output terminals 22b.
<Display Panel>
The array substrate 1 with a display element can form a display panel. An example includes a liquid crystal display panel. As shown in
The liquid crystal display panel 100 is irradiated with light such that the light passes through the array substrate 1, the counter substrate 2, and the liquid crystal 3. In the array substrate 1, voltage is applied to the gate signal lines 12a and the source signal lines 12b to apply the voltage to every pixel, to thereby control an alignment state of the liquid crystals in every pixel and thus to control a light transmittance of every pixel. Consequently, the liquid crystal display panel 100 displays a display image.
<Connection Modes Between Array Inspecting Terminals and Signal Lines>
In the illustration of
Thus, as one of the array inspections, the two signal lines adjacent to each other can be inspected for the presence or absence of a short circuit. It will be described below in detail.
With reference to
In
The probes are applied to the array inspecting terminals 30a_1, 30a_2 to detect the presence or absence of a short circuit between two of the gate signal lines 12a_1 to 12a_4 adjacent to each other. Then, for example, the array inspecting terminals 30a_1, 30a_2 are each applied with the different potential. For example, the direct-current power supply is connected between the array inspecting terminals 30a_1, 30a_2.
If the short circuit occurs between any of the gate signal lines 12a_1 to 12a_4, the current flows between the array inspecting terminals 30a_1, 30a_2 through the short-circuit place.
Then, when the current flowing to the array inspecting terminals 30a_1, 30a_2 is detected and the current value is greater than the reference value, it is determined that the short circuit occurs between any of the gate signal lines 12a_1 to 12a_4.
The inspection device can perform the detection and the determination. It should be noted that the inspection device hardly determines where the short circuit occurs in the gate signal lines 12a_1 to 12a_4. Thus, the inspection device notifies a worker that the short circuit occurs in the gate signal lines 12a_1 to 12a_4 without specifying the short-circuit place. The worker who receives the notification specifies the short-circuit place in the gate signal lines 12a_1 to 12a_4, for example, through visual inspection.
As described above, the two adjacent signal lines are connected to the different array inspecting terminals, allowing for the short-circuit detection.
In addition, the array inspecting terminal does not necessarily need to be connected to the signal lines while skipping one of the signal lines. The array inspecting terminal may be connected to the signal lines while skipping at least one of the signal lines and the two adjacent signal lines may be connected to the different array inspecting terminals. In other words, the array substrate includes the array inspecting terminal connected to the signal lines while skipping at least one of the signal lines and the array inspecting terminal connected to two or more signal lines each adjacent to the signal lines.
The array inspecting switch element 50a is located on each of the gate signal lines 12a between the display region 10 and the array inspecting terminals 30a. Thus, the array inspecting switch elements 50a select conduction or non-conduction between the array inspecting terminals 30a and the gate signal lines 12a (more specifically, the gate signal lines 12a on the display region 10 side).
The array inspecting switch element 50b is located on each of the source signal lines 12b between the display region 10 and the array inspecting terminals 30b. Thus, the array inspecting switch elements 50b select conduction or non-conduction between the array inspecting terminals 30b and the source signal lines 12b (more specifically, the source signal lines 12b on the display region 10 side).
An array inspecting switch terminal 52 is located on the array substrate 1. The array inspecting switch terminal 52 is connected to all control electrodes of the array inspecting switch elements 50a, 50b. A signal is input to the array inspecting switch terminal 52, whereby the array inspecting switch elements 50a, 50b can be controlled.
When the array inspection is performed, a signal for turning the array inspecting switch elements 50a, 50b on is input to the array inspecting switch terminal 52, to thereby electrically connect the array inspecting terminals 30a and the gate signal lines 12a and electrically connect the array inspecting terminals 30b and the source signal lines 12b.
Thus, the array inspection using the array inspecting terminals 30a, 30b can be performed. The example of the array inspection is as described in the first preferred embodiment.
On the other hand, when the array inspection is not performed, a signal for turning the array inspecting switch elements 50a, 50b off is input to the array inspecting switch terminal 52. Thus, a signal can be individually output to each of the gate signal lines 12a through the output terminals 22a, and a signal can be individually output to each of the source signal lines 12b through the output terminals 22b.
The first preferred embodiment has a concern that cutting of the array substrate 1 or removal of the signal lines causes scattered matter. In this case, a step of removing the scattered matter attached on the array substrate 1 may be needed. However, as in the second preferred embodiment, using the array inspecting switch elements 50a, 50b can eliminate the step.
The array substrate 1 in
The collective lighting inspecting terminals 60a, 61a are each connected to the gate signal lines 12a through the collective lighting inspecting switch elements 68a. The collective lighting inspecting switch element 68a is provided with respect to each of the gate signal lines 12a. In the illustration of
The number of (two herein) collective lighting inspecting terminals 60a, 61a connected to the gate signal lines 12a is lower than that of array inspecting terminals 30a connected to the gate signal lines 12a.
The collective lighting inspecting terminals 60b to 62b are each connected to the source signal lines 12b through the collective lighting inspecting switch elements 68b. The collective lighting inspecting switch element 68b is provided with respect to each of the source signal lines 12b. In the illustration of
Here, red pixels, blue pixels, and green pixels are assumed to be disposed side by side in the stated order in the X direction, and the collective lighting inspecting terminals 60b to 62b are connected to the source signal lines 12b of the pixels corresponding to each color. For example, the collective lighting inspecting terminal 60b is connected to the source signal lines 12b corresponding to the red pixels, the collective lighting inspecting terminal 61b is connected to the source signal lines 12b corresponding to the blue pixels, and the collective lighting inspecting terminal 62b is connected to the source signal lines 12b corresponding to the green pixels.
The number of (three herein) collective lighting inspecting terminals 60b to 62b connected to the source signal lines 12b is lower than that of array inspecting terminals 30b connected to the source signal lines 12b.
An collective lighting inspecting switch terminal 66 is located on the array substrate 1. The collective lighting inspecting switch terminal 66 is connected to all control electrodes of the collective lighting inspecting switch elements 68a, 68b.
The array substrate 1 can perform the collective lighting inspection as described below.
<Collective Lighting Inspection>
The collective lighting inspection is performed in a display panel state. In other words, the collective lighting inspection is performed after the display panel formed of the array substrate 1 and the display element is manufactured (for example, see the liquid crystal display panel 100 in
In the collective lighting inspection, the probe is applied to each of the terminals 19, 60a, 61a, 60b to 62b, 66. Then, a predetermined potential is applied to the common wire terminal 19, and a signal for turning the collective lighting inspecting switch elements 68a, 68b on is output to the collective lighting inspecting switch terminal 66. Consequently, an inspection signal can be applied to the gate signal lines 12a and the source signal lines 12b through the collective lighting inspecting terminals 60a, 61a, 60b to 62b.
Then, for example, the inspection signal is input to the collective lighting inspecting terminals 60a, 60b. Consequently, only the pixels of a predetermined color (for example, red) among the even-numbered pixels in the Y direction are operated. At this time, the inspection display image displayed on the display panel is inspected whether it is correctly displayed.
Then, the inspection signal is input to the collective lighting inspecting terminals 60a, 61a, 60b to 62b as appropriate, and the similar inspection method checks the operations of all the pixels. Thus, the collective lighting inspection is performed.
After completion of the collective lighting inspection, the collective lighting inspecting switch elements 68a, 68b are turned off.
In the third preferred embodiment, the two collective lighting inspecting terminals 60a, 61a are provided as the collective lighting inspecting terminals connected to the gate signal lines 12a, but the number of collective lighting inspecting terminals connected to the gate signal lines 12a may be set freely. Similarly, the number of collective lighting inspecting terminals connected to the source signal lines 12b may also be set freely.
<Differences Between Array Inspecting Terminals and Collective Lighting Inspecting Terminals>
In the collective lighting inspection as described above, the inspection display image (display pattern) is displayed on the display panel and the inspection display image is checked to see that each of the pixels operates properly. In other words, in the collective lighting inspection different from the array inspection, the electrical amount is not detected, and the image is optically identified (for example, visual inspection) to determine whether each of the pixels emits proper light. Therefore, to improve inspection efficiency, the collective lighting inspection operates the plurality of pixels at the same time for checking the inspection display image displayed by the plurality of pixels at once, instead of successively operating the pixels one by one for checking the pixels one by one.
Hence, as shown in
However, the collective lighting inspecting terminals 60a, 61a, 60b to 62b are terminals for displaying the inspection display image in the collective lighting inspection and are unlike, in terms of technical ideas, the array inspecting terminals 30a, 30b that used for performing the inspection by detecting the electrical amount without displaying the inspection display image. In other words, even if each of the collective lighting inspecting terminals 60a, 61a, 60b to 62b is connected to the plurality of signal lines, applying the collective lighting inspecting terminals 60a, 61a, 60b to 62b to the array inspecting terminals 30a, 30b cannot be derived from the technical ideas (ideas of checking the inspection display image) in the collective lighting inspection.
<Switch Elements>
In the illustration of
On the other hand, when the influences are negligible, switch elements having both the functions of the array inspecting switch elements 50a, 50b and the collective lighting inspecting switch elements 68a, 68b may be provided. For example, in
Upon the array inspection or the collective lighting inspection, the inspection switch elements 70a, 70b are turned on. When these inspections are not performed, the inspection switch elements 70a, 70b are turned off.
The array substrate 1 can reduce the size of the circuit as compared to that in
In terms of sharing the circuit, part of wiring pattern disposed for the collective lighting inspecting circuit may be used as the array inspecting terminals. This can reduce the manufacturing cost.
In addition, according to the present invention, the above preferred embodiments can be arbitrarily combined, or each preferred embodiment can be appropriately varied or omitted within the scope of the invention.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-030873 | Feb 2014 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6677171 | Nagata | Jan 2004 | B1 |
| 6940300 | Jenkins | Sep 2005 | B1 |
| 20090179875 | Li | Jul 2009 | A1 |
| 20150015820 | Masutani et al. | Jan 2015 | A1 |
| Number | Date | Country |
|---|---|---|
| H11-316389 | Nov 1999 | JP |
| 2015-018144 | Jan 2015 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20150235582 A1 | Aug 2015 | US |
