Patent Application
20210335839
The present application relates to the field of panel display, in particular to an array substrate, a method for manufacturing the same, a display panel and a method for manufacturing the same.
A display panel has a display area (or active area, AA area) and a non-display area. In the display area, a plurality of pixels are configured to form a pixel array, while in the non-display area, a plurality of metal layers are disposed to form peripheral lines. Each pixel generally includes at least a thin film transistor and a pixel electrode connected to the thin film transistor, and each pixel is surrounded by two adjacent scanning lines and two adjacent data lines. These scanning lines and data lines extend from the display area to the non-display area, and are electrically connected to a driver chip via the peripheral lines of the non-display area, thus realizing the normal work of the display panel. A fan-out line is formed by the convergence of the peripheral lines from one end connecting the scanning line and the data line to the area where the driver chip is located. That is, a plurality of peripheral lines have large spacing at the end near the active area and a small spacing at the end near the driver chip, thus forming a fan shape substantially.
After studies, the inventor finds that fan-out lines, especially metal leads, are prone to metal cracks, which eventually lead to bright traces in the display panel, which has a great impact on the yield of the display panel. Therefore, how to reduce or even avoid the occurrence of metal cracks is a technical problem which needs to be urgently solved by those skilled in the art.
The present application is directed to an array substrate and a manufacturing method thereof, and a display panel and a manufacturing method thereof, the occurrence rate of a metal crack can be lowered, an electrostatic damage of a detection circuit in a bonding area can be avoided, and image quality of the display panel is improved.
In order to achieve the above purpose, the present application provides an array substrate, including:
a substrate;
a detection circuit and at least one metal layer deviating from the detection circuit, both located on the substrate; and
a protective layer covering the metal layer and exposing the detection circuit.
Optionally, a material of the protective layer is one or a combination of silicon nitride, silicon oxide and silicon oxynitride.
Optionally, the array substrate further includes a plurality of input and output terminals formed on the substrate, and the protective layer exposes the plurality of input and output terminals.
Optionally, the detection circuit and the plurality of input and output terminals form a bonding area, and an area exposed by the protective layer is equal to the bonding area or greater than the bonding area.
Optionally, the substrate includes a packaging area, and the protective layer only covers the metal layer in the packaging area.
Correspondingly, the present application further provides a method for manufacturing an array substrate, including:
providing a substrate, and forming a detection circuit and at least one metal layer deviating from the detection circuit both on the substrate; and
forming a protective layer, enabling the protective layer to cover the metal layer and expose the detection circuit.
Optionally, the method for manufacturing an array substrate further includes: arranging a plurality of input and output terminals on the substrate, the protective layer exposing the plurality of input and output terminals.
Optionally, the substrate includes a packaging area; and the protective layer only covers the metal layer in the packaging area.
Optionally, the substrate includes a display area and a non-display area, and the packaging area, the detection circuit and the plurality of input and output terminals are all located in the non-display area; the metal layer is formed both in the non-display area and the display area; and while forming the metal layer, the detection circuit is formed in the non-display area and a plurality of thin film transistors are formed in the display area; the protective layer is formed both in the non-display area and the display area; and the forming a protective layer further comprises: removing a portion of the protective layer corresponding to a position of a contact hole in the display area to expose the contact hole while enabling the protective layer to expose the detection circuit.
Correspondingly, the present application further provides a display panel, including an array substrate and a glass cover plate, the display panel includes a display area and a non-display area, the non-display area further includes a packaging area and a bonding area, and the array substrate includes:
a substrate;
a detection circuit and at least one metal layer deviating from the detection circuit, both located on the substrate; and
a protective layer, the protective layer covering the metal layer and exposing the detection circuit;
a packaging area of the array substrate or the glass cover plate is coated with a frit to package the array substrate and the glass cover plate; and
the display panel further includes a driver chip bonded in the bonding area.
Optionally, a material of the protective layer is one or a combination of silicon nitride, silicon oxide and silicon oxynitride.
Optionally, the array substrate further includes a plurality of input and output terminals formed on the substrate, and the protective layer exposes the plurality of input and output terminals.
Optionally, the detection circuit and the plurality of input and output terminals are both located in the bonding area, and an area exposed by the protective layer is equal to the bonding area or greater than the bonding area.
Optionally, the protective layer only covers the metal layer in the packaging area.
Correspondingly, the present application further provides a method for manufacturing a display panel, the display panel includes a display area and a non-display area, the non-display area further includes a packaging area and a bonding area, and the method includes:
manufacturing an array substrate by using the method for manufacturing an array substrate as described above, and providing a glass cover plate;
coating a packaging area of the array substrate or the glass cover plate with a frit, and packaging the array substrate and the glass cover plate;
performing laser irradiation on the frit; and
bonding a driver chip in the bonding area.
Compared with the prior art, in the array substrate and the manufacturing method thereof, and the display panel and the manufacturing method thereof provided by the present application, after at least one metal layer is formed on the substrate, the protective layer is formed on the metal layer, the protective layer can protect the metal layer, damage caused to the metal layer when laser irradiation is subsequently performed on the frit in the display panel is avoided, and therefore the occurrence rate of a metal crack is lowered, and the yield of the display panel is improved easily. Besides, due to the technical scheme of the present application, the protective layer exposes the detection circuit, electrostatic damage, caused by covering by the protective layer, of the detection circuit can be avoided, and the yield of the display panel is further improved.
A display panel, such as an organic light-emitting diode (OLED) display panel commonly includes an array substrate and a glass cover plate which are arranged oppositely. The display panel includes a display area and a non-display area, and a packaging area is arranged in the non-display area, and used for coating with frit to package the array substrate and the glass cover plate.
As shown in
In order to well package the substrate 10 and the glass cover plate 20, a scheme of one embodiment of the present application is as follows: after at least one metal layer is formed on the substrate, a protective layer is formed on the metal layer. The protective layer can protect the metal layer, damage caused to the metal layer when laser irradiation is subsequently performed on the frit in the display panel may be avoided (for example, it is avoided that a crack occurs on the metal layer in an advancing direction perpendicular to laser), and therefore occurrence of a metal crack is lowered. The applicant further finds that accidentally, the method lowers the bright line badness rate of the display panel, and the reason why a bright line occurs on the display panel is that the damage or the crack of the metal layer can result in that a certain data line or a scanning line in the display area cannot receive a signal or a received signal is not accurate.
In another embodiment of the present application, a substrate is provided, and a detection circuit and at least one metal layer deviating from the detection circuit are formed on the substrate; and a protective layer is formed, and the protective layer covers the metal layer, and exposes the detection circuit. The inventor finds that, after at least one metal layer is formed on the substrate, the protective layer is formed on the metal layer. The protective layer can protect the metal layer, damage caused to the metal layer when laser irradiation is subsequently performed on the frit in the display panel is avoided, and therefore the occurrence rate of a metal crack is lowered, and the yield of the display panel is improved easily. Besides, after the protective layer is formed, the protective layer exposes the detection circuit, electrostatic badness, caused by covering by the protective layer, of the detection circuit can be avoided, especially, accumulated electrostatic charges in the detection circuit (CT circuit) may be eliminated, and therefore the yield of the display panel is further improved.
For the purpose of making the content of the present application more clear, the content of the present application is further illustrated in conjunction with the drawings of the description. Of course, the present application is not limited to the specific embodiments, and common substituting known very well by those skilled in the art is also contained in the protection scope of the present application.
Secondly, the present application utilizes the schematic view to perform detailed expression, and when the embodiments of the present application are illustrated in detail, in order to facilitate illustration, the schematic view is not partially amplified according to the common proportion, which should not serve as limitation of the present application.
Referring to
Step S01: Provide a substrate, and form a detection circuit and at least one metal layer deviating from the detection circuit on the substrate.
Step S02: Form a protective layer, and enable the protective layer to cover the metal layer and expose the detection circuit.
In step S01, a substrate 100 is provided. In the present embodiment, the substrate 100 includes a display area and a non-display area, and the non-display area encircles the display area. A packaging area and a driver chip bonding area are arranged in the non-display area. Of course, in other embodiments, the non-display area and the display area may also be located on different surfaces of the substrate. For example, the non-display area is located on a back side of the substrate, an area of the display area is not occupied, and therefore the resolution ratio is increased, so that a narrow frame or no frame is achieved, which is not limited by the present application.
The substrate 100 may be made of a transparent material, such as glass, quartz, silicon wafers, polycarbonate, polymethyl methacrylate or metal foil or the like. The substrate 100 may be a rigid substrate, and may also be a flexible substrate. Selection and pretreatment of the substrate 100 are familiar to those skilled in the art, and thus is not illustrated in detail. The display area is subsequently used for forming a scanning line, a data line, a transistor switch or a pixel electrode or the like on the substrate 100. The non-display area is subsequently used for forming a fan-out wire on the substrate 100, and used for connecting the scanning line, the data line and the like of the display area to a driver chip.
As shown in
As shown in
Referring to a position relationship schematic view of the packaging area A and the bonding area B in
Then, referring to
While the detection circuit 330, the input terminal 310 and the output terminal 320 are formed in the bonding area B of the substrate 100, at least one metal layer deviating from the detection circuit 330 is formed in the non-display area of the substrate 100, and here, “deviating” means no overlapping in a direction perpendicular to the substrate 100. In the present embodiment, preferably, three metal layers are formed in the non-display area of the substrate 100, and respectively are a bottom metal layer 110, an intermediate metal layer 120 and a top metal layer 130. In other embodiments, two metal layers, four metal layers or more metal layers may also be formed, and it needs to be determined according to an actual requirement of the array substrate, which is not limited in the present application. The bottom metal layer 110, the intermediate metal layer 120 and the top metal layer 130 are isolated by a dielectric layer 140. A position relationship of the metal layers, the input terminal 310, the output terminal 320 and the detection circuit 330 is as shown in
Preferably, the input terminal 310 and the output terminal 320 each include two metal layers connected via a contact hole. The input terminal 310 and the output terminal 320 are formed while the bottom metal layer 110, the intermediate metal layer 120 and the top metal layer 130 are formed.
For example, a first metal layer is formed in the bonding area while the bottom metal layer 110 is formed, then a dielectric layer is formed in the bonding area while the dielectric layer is formed on the bottom metal layer 110, after that, etching (the etching may be synchronous with certain time etching in the display area) is performed on the dielectric layer to form a through hole, then filling is performed on the through hole to form a second metal layer while the intermediate metal layer 120 is formed, and the first metal layer and the second metal layer form the input terminal 310 or the output terminal 320.
Preferably, in the process of forming a thin film transistor in the display area, the detection circuit is formed in the bonding area. Preferably, the detection circuit includes a plurality of mutually connected thin film transistors, the quantity of the transistors and a connection relationship between the transistors are determined according to an actual requirement, a specific structure of the detection circuit is not described in detail in the present embodiment, and the detection circuit is not specifically limited by the present application.
Preferably, a plurality of metal film layers are also formed in the display area of the substrate 100 while the input terminal 310 and the output terminal 320 are formed in the non-display area of the substrate 100, for example, a data line, a scanning line or a pixel electrode or the like is formed. That is, a plurality of metal layers are formed in the non-display area and an input/output terminal is formed in the bonding area of the non-display area while the data line, the scanning line, the pixel electrode or other metal film layers are formed in the display area. Thus, a material of the plurality of metal layers and the input/output terminal depends on a material of the data line, the scanning line, the pixel electrode or other metal film layers formed both in the display area, and materials of the plurality of metal layers may be different from one another, and may also be totally the same. The material of the plurality of metal layers contains, but is not limited, to copper, aluminum, nickel, magnesium, chromium, molybdenum, tungsten, alloys thereof and the like. Of course, the plurality of metal layers may also be formed separately in the non-display area of the substrate 100.
The plurality of metal layers is isolated by the dielectric layers 140, the dielectric layers 140 between different metal layers are formed in different steps, but all configured for isolating the metal layers, thus, no distinguishing is performed in
A method for forming the plurality of metal layers and the dielectric layers in the non-display area of the substrate 100 is introduced simply below, and includes following steps.
Firstly, a first dielectric layer is formed on the substrate 100, and preferably, a chemical vapor deposition method may be adopted for forming, such as, high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHVCVD) or the like. Then, bottom metal is formed on the first dielectric layer, and preferably, forming is achieved by adopting a sputtering method. Then patterning is performed on the bottom layer metal, the patterning process includes, for example, spin coating of photoresist, exposing, developing and an etching processes, and the bottom metal layer 110 is formed. Then the above step is repeated, a second dielectric layer is formed on the bottom metal layer 110, the second dielectric layer covers the bottom metal layer 110, then intermediate metal is formed on the second dielectric layer, and etching is performed to form the intermediate metal layer 120. Then a third dielectric layer is formed on the intermediate metal layer 120, the third dielectric layer covers the intermediate metal layer 120. Finally, top metal is formed on the third dielectric layer, and after etching, the top metal layer 130 is formed. The first dielectric layer, the second dielectric layer and the third dielectric layer form the dielectric layer 140 as shown in
In step S02, referring to
In the present embodiment, the protective layer 150 is formed by adopting the chemical vapor deposition method, according to conditions of the forming a protective layer 150, preferably, cavity temperature is 350° C. to 400° C., cavity pressure is 900 mtorr to 1100 mtorr, film forming time is 350 s to 450 s, and optimally, the cavity temperature is 385° C., the cavity pressure is 1000 mtorr, and the film forming time is 400 s.
Preferably, a protective layer is also formed in the display area while the protective layer 150 is formed in the non-display area. That is, the protective layer is formed both on the whole substrate 100, etching is performed on the protective layer at a position, provided with a contact hole, in the display area, the contact hole is exposed, and it is avoided that the protective layer affects connection of the display area. A film layer before the protective layer is formed in the display area is not limited, for example, the top metal layer is formed in the non-display area while the data line is formed in the display area, later if the protective layer is directly formed, in the display area, the protective layer is formed on the data line. If the protective layer is formed after other film layers (such as the scanning line) need to be formed on the data line in the display area, in the display area, the protective layer is formed on the scanning line.
The protective layer 150 is formed on the top metal layer 130. The protective layer 150 is used for protecting the metal layer, influences of laser to the metal layer when laser irradiation is subsequently performed are avoided, and therefore a metal crack is avoided, the occurrence rate of the metal crack is lowered, and finally, the yield of the display panel is improved. However, due to the fact that the protective layer 150 is also formed in the bonding area B, the detection circuit 330 in the bonding area B is covered by the protective layer 150, elimination of surface charges is not facilitated, occurrence of electrostatic badness on the detection circuit is caused easily, and thus, the step S04 needs to continue to be performed.
Then, referring to
Specifically, a photoresist layer is formed on the protective layer 150, exposing and developing are performed on the photoresist layer, a patterned photoresist layer is formed, and the protective layer 150 on the detection circuit 330, the input terminal 310 and the output terminal 320 in the bonding area B is exposed; then, with the patterned photoresist layer as a mask, etching is performed on the protective layer 150, preferably, etching is performed on the protective layer 150 by adopting plasma dry etching, an exposed protective layer 150 is removed, and the detection circuit 330, the input terminal 310 and the output terminal 320 in the bonding area B are exposed.
Preferably, etching gas is mixed gas of C2HF5 (pentafluoroethane), H2 (hydrogen) and Ar (argon). The argon may improve energy of ion bombardment, reaction of pentafluoroethane and the protective layer is promoted through ion bombardment, and the reaction rate may be increased. The etching gas may also be mixed gas of CF4 (carbon tetrafluoride) and O2 (oxygen), or other etching gas known by those skilled in the art, and of course, etching may also be performed on the protective layer 150 by adopting other etching methods known by those skilled in the art, which is not limited by the present application.
Preferably, performing patterning on the protective layer 150 further includes exposing a remaining bonding area, except the detection circuit 330, the input terminal 310 and the output terminal 320, that is, by performing patterning on the protective layer 150, a size of the formed opening hole is equal to that of the bonding area. As shown in
Of course, in order to avoid influences on the display panel when the driver chip is bonded subsequently, when patterning is performed on the protective layer 150, the non-display area distanced from a periphery of the bonding area B within 0-100 μm may also be exposed, such as an opening 170 in
Of course, when patterning is performed on the protective layer 150, etching may also be performed on an area, except the packaging area A, of the non-display area while the protective layer in the bonding area B is removed, only the protective layer 150 (as shown in
When etching is performed on the protective layer 150, the protective layer in the display area may also be removed at the same time. That is, after the protective layer is formed, it is needed to perform etching on the protective layer at the position, provided with the contact hole, in the display area, and the contact hole is exposed. In addition, in the etching process, the protective layer on the bonding area in the non-display area may be removed in an etching manner, the protective layer in the remaining area, except the packaging area, in the non-display area may also be removed in an etching manner, all the protective layer in the display area may also be etched away, and it is needed to perform selection according to actual conditions.
Specifically, the protective layer 150 is coated with the photoresist layer, exposing is performed on the photoresist layer via a mask. For positive photoresist, the mask may only expose the contact hole in the display area, or the whole display area is exposed, or the bonding area in the non-display area is exposed, or other areas, except the packaging area, in the non-display area are exposed, or all the non-display area except the packaging area and all the display area are exposed, and the mask for using is determined according to a specific condition. Then developing is performed on the photoresist layer after the photoresist layer is subjected to exposing, the patterned photoresist layer is formed. Then etching is performed on the protective layer with the patterned photoresist layer as the mask. Finally, a remaining photoresist layer is stripped away, and a pattern of a needed protective layer is formed.
It needs to be noted that in the process of performing etching on the protective layer with the patterned photoresist layer as the mask, it needs to avoid damage to other film layers below the protective layer, for example, when etching is performed on the protective layer of the remaining area, except the packaging area, of the non-display area, it needs to avoid damage to the top metal layer below the protective layer. Aiming at the problem, an etching selection ratio may be adjusted, a proper etching selection ratio is selected to perform etching on the protective layer, it is guaranteed that a high etching rate is achieved on the protective layer, a low etching rate is achieved on remaining film layers, or no etching is performed on the remaining film layers. For example, preferably the etching selection ratio of the protective layer to the remaining film layers is greater than 5:1.
Besides, in the step of performing etching on the protective layer 150, partial etching may also be performed on the protective layer 150 in the packaging area, so that at least part of a surface, deviating from the top metal layer 130, of the protective layer 150 in the packaging area is a concave surface, a convex surface or a concave-convex surface. That is, at least part of the surface, deviating from the top metal layer 130, of the protective layer 150 is a non-plane surface, a better bonding force is achieved between coated frit and the protective layer 150, that is, the bonding force of the frit and the protective layer is improved via the non-plane surface, and therefore reliability of the finally formed display panel is improved.
Preferably, the concave surface or the convex surface is one or a combination of a cylinder, a cone, a circular truncated cone or a hemisphere. The concave-convex surface is formed by connecting the concave surface and the convex surface in a staggered manner, and may also be formed by arranging the concave surface and the convex surface at intervals in a staggered manner. For example, the concave surface is composed of a plurality of grooves formed on the surface of the protective layer 150, and the grooves may be the same in size and shape, and may also be different in size and shape. For example, the convex surface is composed of a plurality of protrusions formed on the surface of the protective layer 150, and the protrusions may be the same in size and shape, and may also be different in size and shape. The concave-convex surface is composed of the plurality of grooves and the plurality of protrusions formed on the surface of the protective layer 150, and similarly, shapes and sizes of the grooves and the protrusions are not limited.
Finally, a structure as shown in
Correspondingly, the present application further provides a manufacturing method of a display panel, including the manufacturing method of the array substrate as mentioned above. Referring to
Manufacturing of an array substrate is completed, and a glass cover plate 200 is provided.
A packaging area of the array substrate or the glass cover plate 200 is coated with frit 160, and the array substrate is packaged with the glass cover plate 200.
Laser irradiation is preformed on the frit; a protective layer 150 can protect a metal layer, it is avoided that the metal layer generates a crack, the occurrence rate of the crack is lowered, and the yield of the display panel is improved.
A driver chip is bonded in a bonding area of the array substrate, due to the fact that a protective layer on a testing circuit 330 is removed, it can be avoided that a detection circuit is damaged by static electricity, the occurrence rate of electrostatic badness is lowered, and the yield of the display panel is further improved.
Correspondingly, the present application further provides an array substrate, which is manufactured by adopting the manufacturing method of the array substrate as mentioned above. The array substrate includes:
a substrate;
a detection circuit and at least one metal layer deviating from the detection circuit located on the substrate; and
a protective layer, the protective cover covering the metal layer and exposing the detection circuit.
Specially, referring to
The protective layer 150 is formed on the top metal layer 130. The protective layer 150 can protect the metal layer, damage caused to the metal layer when laser irradiation is subsequently performed on the frit in the display panel is avoided, and therefore the occurrence rate of a metal crack is lowered, and the yield of a display panel is improved easily; patterning is performed on the protective layer 150 after the protective layer 150 is formed, the detection circuit 330 and the input/output terminal 310/320 in the bonding area are exposed, electrostatic badness, caused by covering by the protective layer, of the detection circuit can be avoided, and the yield of the display panel is further improved.
Correspondingly, the present application further provides a display panel, which is manufactured by adopting the manufacturing method of the display panel as mentioned above.
To sum up, in the array substrate and the manufacturing method thereof, and the display panel and the manufacturing method thereof, after at least one metal layer is formed on the substrate, the protective layer is formed on the metal layer. The protective layer can protective the metal layer, damage caused to the metal layer when laser irradiation is subsequently performed on the frit in the display panel is avoided, and therefore the occurrence rate of the metal crack is lowered, and the yield of the display panel is improved easily. In addition, due to the technical scheme of the present application, the protective layer exposes the detection circuit, electrostatic badness, caused by covering by the protective layer, of the detection circuit can be avoided, and the yield of the display panel is further improved.
The above description is only description of a preferable embodiment of the present application, and is not intended to do any limitation on the scope of the prevent application, and any alternation and modification made by those skilled in the art of the present application according to the above disclosed content both belong to the protective scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201710677512.5 | Aug 2017 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/082961 | 4/13/2018 | WO | 00 |
