BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross sectional view of a flat panel display (FPD) assembly, as known in the prior art.
FIG. 2 is a cross sectional view of an amorphous silicon (a-Si) thin film transistor (TFT), as known in the prior art.
FIG. 3 shows the formation of the conductive channel and current flow in the TFT of FIG. 2, as known in the prior art.
FIG. 4A is an energy band diagram of an ideal amorphous semiconductor, as known in the prior art.
FIG. 4B is an energy band diagram of a typical amorphous semiconductor, as known in the prior art.
FIG. 5 is an energy band diagram of an MIS (metal-insulator-semiconductor), as known in the prior art.
FIG. 6 shows a number of plots of drain-to-source currents of TFTs as a function of inverse temperature, as known in the prior art.
FIG. 7A is an energy band diagram of an MIS device prior to the application of an electric bias.
FIG. 7B is an energy band diagram of the MIS device of FIG. 7A after the application of an electric bias causing charges to be trapped in the band gap.
FIG. 7C is an energy band diagram of the MIS device of FIG. 7A after the application of an electric bias causing states to be created in the band gap
FIG. 8 shows the dependence of TFT threshold voltage shift on bias stress time and bias stress voltage.
FIG. 9 show various plots of the drain-to-source current as a function of gate-to-source voltage for a good and a defective TFT before and after application of a bias stress.
FIG. 10 is a flowchart of steps taken to detect defects related to the a-Si:H layer in TFTs, in accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
In accordance with the present invention, to detect defects in a TFT panel, an electric bias is applied to the TFT panel for a known time period. The applied electric bias induces charge trapping in the SiNx film and/or state creation in the a-Si:H film, thus giving rise to the TFT threshold voltage shift. The shift in the threshold voltage results in the variation of the TFT IOFF current. The amount of the threshold voltage shift (ΔVT) depends on the applied bias voltage, the duration of the bias, as well as the initial density of state in the films.
FIG. 7A is an energy band diagram of an MIS device prior to the application of an electric bias. FIG. 7B is an energy band diagram of the MIS device of FIG. 7A after the application of an electric bias causing charges to be trapped in the band gap. FIG. 7C is an energy band diagram of the MIS device of FIG. 7A after the application of an electric bias causing states to be created in the band gap.
FIG. 8 shows the dependence of TFT threshold voltage shift on the bias stress time and bias stress voltage. As seen from FIG. 8, the longer the stress time or the greater the bias voltage VGB, the greater is the amount of the threshold voltage shift AVT.
Plot 100 of FIG. 9 shows the drain-to-source current as a function of gate-to-source voltage for both a good and a defective TFT before application of a bias stress. Plot 102 of FIG. 9 shows the drain-to-source current as a function of gate-to-source voltage for a good TFT after application of a bias stress. Plot 104 of FIG. 9 shows the drain-to-source current as a function of gate-to-source voltage for a defective TFT after the application of a bias stress. As seen from FIG. 9, for each gate-to-source voltage, the shift in current—caused by the shift in the threshold voltage—is greater for a defective TFT than a good TFT.
Thus, in accordance with the present invention, to detect defects related to the a-Si:H layer in TFTs, an electric bias stress is applied for a time sufficient to increase the defect's density of states. The increase in the defect's density of states causes a corresponding shift in the threshold voltage and the Ioff of the device. The stressed plate or panel with shifted threshold voltage can then be electrically tested using standard TFT array testers, such as the Array Checker manufactured by Photon Dynamics, Inc., located at 5970 Optical Court, San Jose, Calif. 95138, which uses a voltage imaging optical system (VIOS) technology. Other electrical array testers, such as those using electron beam technology or any other means to measure threshold voltage shift, may also be used.
FIG. 10 is a flowchart of steps taken to detect defects related to the a-Si:H layer in TFTs in accordance with one embodiment of the present invention. Electric (voltage) bias stress is applied to the panel under test 202. The voltage level and the duration of the bias is selected by the user. The application of the electric bias test ends at 204. The bias stress causes defective panels to have shifted threshold voltage shift. Next, a pixel electric test using a tester, such as the Array Checker, manufactured by Photon Dynamics, Inc., is performed to measure voltage changes. The defect threshold is set either prior or after the application of the stress test 208. The bias stress causes defective panels to have shifted threshold voltage shift which is detectable by the VIOS. Following the defect extraction 210, the worthiness of panel based on degree of defectiveness is determined 212.
In some embodiments, the user adjustable stress voltage may be ±50 volts, and the user adjustable stress time may vary between 1000 to 2000 seconds. The stress may be applied on a sample of panels in the fabrication flow or on every panel.
In some embodiments, the bias stress time may be reduced if accompanied by a temperature change in the panel. As such, the plate under test may be warmed or cooled simultaneously with the application of the voltage stress. Alternatively, the plate under test may be warmed or cooled either before or after the application of the voltage stress.
As long as the temperature of the a-Si:H film remains below the a-Si:H deposition temperature of approximately, e.g., 250 to 350° C., the TFTs (both good and defective) are not further damaged. Elevating the TFT temperature to, for example, 50° C. in combination with the stress test may be sufficient to reveal the defects.
TFTs stressed by the application of the heat relax back to their normal (good or defective) condition after the heat source is removed. Thus, heating may be required as the voltage testing is in progress. This arrangement may have a drawback if the voltage testing method has a dependency on temperature.
TFTs stressed by the application of a bias voltage relax back to their normal (good or defective) condition after the bias voltage is removed. Typical relaxation time may be several hours, and usually less than a day. Thus, a bias voltage may be applied to a plate at a different location from the array tester machine. The plate may subsequently be placed into the array tester for testing within a short period of time (less than a few hours). This may be helpful to keep the utilization of the array tester high.
The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Patent Application
20080024157
