Patent Application
20190120708
The present invention is related to integrated circuit (IC) chips and particularly to assessing and minimizing warpage in IC chips manufacturing and use.
Generally, Hooke's law provides that the strain or deformation of an elastic object or material is proportional to the stress (force) applied to it. It is well known in the integrated circuit (IC) chip manufacturing arts that heat during chip fabrication, as well as internally generated heat from subsequent environmental conditions, can deform the chip, known as warping. Moreover, during normal IC chip usage both localized heating and heat cycling can easily cause warpage strain as well. Warpage strain causes stress that progressively degrades chip materials during fabrication, and frequently leads to abnormal events and catastrophic failures, especially for yield and reliability. Thus, progressive warpage and strain during fabrication and chip service life are indicators of material degradation and potential catastrophic abnormal events.
Additionally, as IC fabrication technologies progress, back end of the line (BEOL) features shrink to twenty two nanometers (22 nm) and below. These technologies use more porous, low-modulus ultra-low-k materials in BEOL. These ultra-low-k materials cause additional, chip-package-interaction (CPI) susceptibility to warpage strain, making packaging more challenging.
Thus, there is a need for on-chip monitoring warpage strain in real-time and more particularly for monitoring and characterizing warpage strain in real-time, during chip fabrication, packaging and in use, and for taking steps to mitigate stress.
A feature of the invention is real-time on-chip warpage monitoring;
Another feature of the invention is a compact strain element for monitoring and characterizing warpage strain in real-time, during chip fabrication, packaging and in use;
Yet another feature of the invention is a single layer, thin film strain sensor and strain gage circuit for real-time monitoring and mitigating stress induced chip warpage during chip fabrication, packaging and in use.
The present invention relates to an on-chip strain gage for monitoring strain on an integrated circuit (IC) chip, the IC chip and method of monitoring and mitigating stress induced chip warpage. The strain gage sensor includes a strain sensor element in a single layer. The strain gage sensor quantifies and digitizes local strain which reflects local chip stress from chip warpage. During normal chip usage, the strain information may be used to alter chip operation.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Turning now to the drawings and more particularly
In this example, the preferred strain gage 100 also includes an amplifier 106, e.g., an operational amplifier. The amplifier 106 receives the stress responses 104 and provides an amplified signal 108 to an analog to digital (A/D) converter 110. The A/D converter 110 quantifies the amplified signal as a digital output 112. Also in this example, a suitable microcontroller 114 interrogates the digital output 112 against stored prior history and threshold values, and may store the interrogation results 116 in a register 118 for subsequent application.
For a piezoresistive thin-film layer element 120, the element 120 has a known, process dependent sheet resistance (ρ) and the strain sensor 120 has length (L) 120L, width (b) 120W, thickness or height (h) 120H and area A=L·W. Thus, the strain sensor element 120 has a nominal resistance determined by: R=ρ·L/A=(ρ/h)·(L/b). It should be noted that piezo-resistive semiconductor is also very sensitive to temperature change. Thus, using a piezoresistive element 120 also provides the optional capability to compensate for temperature through accurately measuring strain.
For a capacitive thin-film layer element 120, the element 120 is a capacitor that has a measurable change in dielectric constant in response to strain. This dielectric constant changes the capacitance of a suitably patterned capacitive element 120.
Local stress originate from strain, force, torque and/or other stimuli caused by the chip warping. Other stimuli may include, for example, displacement, acceleration and/or position. Mechanical strain (ε) contorts the strain element 120 in one or more dimensions 120H, 120L and/or 120W and has the form: ε=ΔD/D, where D is h, L or b depending on how the element 120 contorts. The gage factor (GF) for a strain element 120 is ratio of relative change in electrical resistance (ΔR) to the stress from the mechanical strain and has the form: GF=(ΔR/R)/ε. For any given strain gage, GF is a unit-less constant. It should be noted that GF for a semiconductor strain gauge element, e.g., doped silicon, is 1 to 2 orders magnitude higher than for metal foil strain gauges with the same dimensions.
In one preferred embodiment, the strain sensor element is a semiconductor, e.g., silicon 134 which exhibits the highest gage factor. Further, the selected semiconductor may be piezoresistive material. A piezoresistive semiconductor element may be a doped base material piezoresistor, boron diffusion p-doped, or arsenide diffusion n-doped, doped to a desired base resistance. Piezoresistive strain gauges are much more efficient than simple metal or resistive elements. Piezoresistor element can be compactly utilized in a Wheatstone bridge for accurately measuring resistance changes from strain.
In addition to doped semiconductor, suitable piezoelectric strain sensor material may include, for example, perovskites. Generally, perovskite materials are class of compounds with the same type of crystal structure as calcium titanate (CaTiO3), i.e., XIIA2+VIB4+X2−3 A 3 that exhibit dipole moment with strain. A preferred perovskite is lead zirconate titanate (PZT). PZTs are an intermetallic inorganic compound having the form Pb[ZrxTi1-x]O3, where 0≤x≤1, or (PbZrO3+PbTiO3). Other suitable, non-perovskite materials that also show strain sensitivity include, for example, aluminum nitride AlN and zinc oxide ZnO. Advantageously, depositing a thin film of perovskite and defining perovskite elements may be done at any design layer or level, including toward/at the end of chip fabrication, e.g., in the backend of the line (BEOL). For example, a simple mask and deposit or mask and etch step may be used to define a capacitive strain sensor with an easily measured capacitance value at almost any chip layer. Using a BEOL perovskite thin film, for example, is simple and easy, reducing manufacturing cost with minimal yield loss.
As shown by the example of
Typically, a completed IC chip may be flip-chip bonded to a carrier substrate for high-end applications, or where performance may not be a primary concern wire-bonded to the carrier substrate. With flip-chip bonding the top chip surface (including pads) faces down towards the carrier substrate where the chip is attached, e.g., with the pads soldered to the carrier substrate. Optionally, additional pads may be formed on the back side of the chip, e.g. using through-silicon-vias (TSVs). For a wire-bonded IC chip, extra top-side pads may be provided for probing. These optional pads provide independent strain gage testing, post packaging.
Chip warpage that occurs on the chip 170 after forming an element 100. Forming elements early in manufacturing, as well as at subsequent manufacturing layers, provides for characterizing both cumulative and stage by stage process warpage. Further, providing sufficient access to the strain gage 100 during manufacturing provides for in situ monitoring warpage, especially die during chip bonding and assembly. Once the chip 170 is complete through BEOL, the chip 170 itself may measure and digitize fabrication warpage induced strain from the strain gage 100, and optionally, compare the digitized values to a threshold value. Thereafter, during bonding and assembly, differential heating can by controlled and optimized in real-time by monitoring stress and adapting to maintain warpage within desired limits.
Additionally, if the chip I/O circuits 178 include a communications controller 180 such as Bluetooth controller or an NFC controller, the packaged chip may be provided with an antenna (e.g., a Bluetooth or NFC antenna) 182 for communicating with a local external device 184, e.g., a stand-alone computer, smart phone or tablet. An NFC antenna 182, when in the presence of a suitable radio frequency (RF) signal, Bluetooth or NFC, from the external device 184, not only provides for collecting strain data, but also power allows the IC chip 170 NFC controller 180 to extract power from the RF signal. Thus, the IC chip 170 can measure warpage and collect strain information even when the IC chip 170 is disconnected from normal power supplies.
Thus, when used in a suitable field application, the strain gage 100 provides for real-time stress and warpage monitoring even during active chip use. The strain gage 100 may be continually quantifying local strain, or remain dormant until a measurement is desired. Responding to measured strain/stress, the chip or a separate controller in the remote device 184 can take appropriate cooling action, e.g., through core activity modulation, activity rebalancing, or through a specific core process. Also, whenever the measured stress meets or exceeds a threshold, the chip can initiate/alter external cooling to protect itself from warpage-related mechanical stress and reliability problems.
Advantageously, a preferred strain gage circuit provides for real-time on-chip warpage monitoring during chip fabrication, packaging and in use. Further, the preferred sensor element is compact, formed in a single selected chip layer. Thus, the preferred strain sensor includes a thin film element that may be formed in any chip layer, as early as in device feature layers to the BEOL. The preferred sensor element, strain sensor and strain gage circuit provide for real-time monitoring and mitigating stress induced chip warpage during chip fabrication, bonding/packaging and in use.
Further, an IC chip with integrated Bluetooth or NFC communications capability and a preferred strain gage circuit can wirelessly provide stress monitoring information over an appropriate wireless network. Moreover, using signals to an NFC antenna, an external device can power the IC chip. Thus, the IC chip can self-measure warpage/die strain even without a normal power supply connection.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.
