Claims
- 1. A semiconductor device having conductive lines where the conductive lines have an increased thickness in critical path areas; comprising:a) a semiconductor structure having a top surface comprised of a first dielectric layer; b) a plurality of first level conductive lines over said first dielectric layer; at least portions of said first conductive lines running in a first direction; said first level conductive lines comprised of a first level first conductive line and a second first level conductive line; c) a second dielectric layer over said first level conductive lines and said first dielectric layer; d) a via opening in said second dielectric layer over a portion of said first level first conductive line; e) a plug filling said via opening; f) a trench pattern in said second dielectric layer; said trench pattern comprised of trenches that are approximately orthogonal to said first level conductive lines; g) said trenches filled with a conductive material to form supplemental second lines; h) second level conductive lines over at least portions of said supplemental second lines and said plug; said second level conductive lines having critical path areas; i) said second level conductive lines are aligned parallel to said trenches; said trenches formed in critical path areas of said second level conductive lines, said second level conductive lines are not formed to contact said first level conductive lines where a contact is not desired; whereby in the critical path areas of said second level conductive lines, said supplemental second lines underlie said second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.
- 2. The semiconductor device of claim 1 wherein said first level conductive lines are comprised of Al alloy.
- 3. The semiconductor device of claim 1 wherein said first level conductive lines are formed by blank depositing of a conductive layer and patterning said conductive layer.
- 4. The semiconductor device of claim 1 wherein said plug is comprised of a barrier layer and a tungsten (W) plug.
- 5. A semiconductor device having conductive lines where the lines have an increased thickness in critical path areas; comprising:a) a semiconductor structure having a top surface comprised of a first dielectric layer; b) a plurality of first level conductive lines over said first dielectric layer; at least portions of said first conductive lines running in a first direction; said first level conductive lines comprised of a first level first conductive line and a second first level conductive line; (1) said first level conductive lines are comprised of Al; (2) said first level conductive lines are formed by blank depositing of a Aluminum alloy conductive layer and patterning said conductive layer; c) a second dielectric layer over said first level conductive lines and said first dielectric layer; d) a via opening in said second dielectric layer over a portion of said first level first conductive line; e) a plug filling said via opening; (1) said plug comprised of a barrier layer and a tungsten (W) plug; f) a trench pattern in said second dielectric layer; said trench pattern comprised of trenches that are approximately orthogonal to said first level conductive lines; g) said trenches filled with a conductive material to form supplemental second lines; h) second level conductive lines over at least said supplemental second lines and said plug; said second level conductive lines have critical path areas; i) said second level conductive lines are aligned parallel to said trenches; said trenches formed in critical path areas of said second level conductive lines, said second level conductive lines are not formed to contact said first level conductive lines where a contact is not desired; whereby in the critical path areas of said second level conductive lines, said supplemental second lines underlie said second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.
Parent Case Info
This is a division of patent application Ser. No. 09/783,379, filing date Feb. 15, 2001 now U.S. Pat. No. 6,399,471, Assorted Aluminum Wiring Design To Enhance Chip-Level Performance For Deep Sub-Micron Application, assigned to the same assignee as the present invention.
US Referenced Citations (3)