Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention and its advantages are now described in conjunction with the accompanying drawings.
FIG. 1 shows a schematic circuit block diagram of an asymmetrical random access memory cell according to the invention, and
FIG. 2 shows a schematic circuit enabling read, write and write back operations for asymmetric memory cells and protects a floating bit-line against read signal loss due to leakage.
Claims
1. An asymmetrical random access memory cell (1) comprising at least two cross coupled inverters (2, 3), each having a node (22, 32) wherein each node is driven by a first and second bit-line (blt, blc) of a pair of complementary bit-lines, which are connected via at least a first and second pass-transistor (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds providing asymmetrically physical behaviours, and that the first and second pass-transistors (21, 31) are driven by a first and second wordline (wl, wwl), wherein the first and second wordlines are individually controlled.
2. The random access memory of claim 1 comprising a plurality of asymmetrical random access memory cells arranged in a plurality of columns and rows, wherein a control circuit is provided for controlling the first and second wordlines (wl, wwl).
3. The random access memory according to claim 2, wherein the memory cells of one of the pluralities of columns are further partitioned into a plurality of groups; each of the plurality of groups comprises a specific bit-line dedicated to the group; the first node of the cells of each group are connected to the specific bit-line (blt) dedicated to the group, and wherein the second bit-line (blc) is connected to the second node of each cell and is common to all cells within the column.
4. A method of operating a random access memory comprising the steps of:
driving a first and second pass-transistor during a write-cycle of a memory cell such that the first and second pass transistors are switched to an open state; anddriving either the first or the second pass-transistor during a read-cycle of the memory cell such that the driven first or second pass-transistor is switched open.
5. The method of claim 4, further comprising the step of:
driving the first pass-transistor (31);deriving a first signal from a dedicated node (32) of the first pass-transistor;driving the first signal onto a bit-line (blt);inverting the first signal;driving the first signal onto the complementary bit-line (blc); andopening the second pass-transistor (21).
6. The method of claim 4, further comprising the steps of:
opening the first pass-transistor (31);deriving a first signal from a dedicated node (32) of the first pass-transistor;driving a forced signal onto bit-line (blt), the forced signal corresponds to a data to be written;inverting the forced signal on bit-line (blt);driving the inverted forced signal onto the complementary bit-line (blc); andopening the second pass-transistor (21).
7. The method of claim 4, further comprising the step of:
performing read-write-back-cycles or write-cycles depending on a control signal, wherein the control signal controls a column of cells or a group of columns.
8. The method of claim 4, further comprising the step of:
selecting a first row;performing a write operation of a first plurality of memory cells on a plurality of selected columns while reading a second plurality of memory cells on a plurality of unselected columns corresponding to the first row.
9. The method of claim 4, further comprising the step of:
limiting the time the bit-line coupled to the pass-transistor is floating.
10. The method of claim 4, further comprising the step of:
activating a leakage compensating device depending on the detected state of the bit-line, wherein the detection is performed after a predetermined time, and wherein the leakage compensating device permanently charges the bit-line.
Patent Application
20070165447
