This application is related to our commonly assigned copending United States patent applications entitled: "METHOD AND APPARATUS FOR FORMING REDUNDANT VIAS BETWEEN CONDUCTIVE LAYERS OF AN INTEGRATED CIRCUIT" by Gabriel Bracha et. al., having U.S. patent application Ser. No. 08/535,427; "METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT" by Larry G. Jones et al., having U.S. patent application Ser. No. 08/426,211; "APPARATUS AND METHOD FOR AUTOMATED TRANSISTOR AND COMPONENT FOLDING TO PRODUCE OPTIMIZED CELL STRUCTURE" by Robert Maziasz et al., having U.S. patent application Ser. No. 08/597,788; "APPARATUS AND METHOD FOR AUTOMATICALLY PLACING TIES AND CONNECTION ELEMENTS WITHIN AN INTEGRATED CIRCUIT" by Mohan Guruswamy et al., having U.S. patent application Ser. No. 08/597,768; "APPARATUS AND METHOD FOR THE AUTOMATIC DETERMINATION OF A STANDARD LIBRARY HEIGHT WITHIN AN INTEGRATED CIRCUIT DESIGN" by Robert Maziasz et al., having U.S. patent application Ser. No. 08/598,555; "AUTOMATIC SYNTHESIS OF STANDARD CELL LAYOUTS" by Mohan Guruswamy et. al., filed of even date herewith; "AUTOMATIC LAYOUT SUBSTRATE AND WELL TIE STYLE SELECTION" by Mohan Guruswamy et. al., filed of even date herewith; "AUTOMATIC LAYOUT TRANSISTOR PLACEMENT" by Robert Maziasz et. al., filed of even date herewith; "AUTOMATIC ROUTING SPACE AND DIRECTION DETERMINATION" by Srilata Raman et. al., filed of even date herewith; "AUTOMATIC LAYOUT WIRE MINIMIZATION FOR GRIDDED PORTS" by Venkata Chiluvuri et. al., filed of even date herewith; "AUTOMATIC LAYOUT TRANSISTOR STACKING" by Robert Maziasz et. al., filed of even date herewith; "AUTOMATIC LAYOUT TIE FILLING" by Daniel Dulitz, filed of even date herewith; "AUTOMATIC LAYOUT CONTACT AND VIA FILLING" by Daniel Dulitz, filed of even date herewith; "AUTOMATIC LAYOUT NOTCH FILLING" by Daniel Dulitz, filed of even date herewith; "AUTOMATIC LAYOUT I/O PORT PLACEMENT" by Srilata Raman et. al., filed of even date herewith; "SEMICONDUCTOR DEVICE USING DIODE PLACE-HOLDERS AND METHOD OF MANUFACTURE THEREOF" by Daniel R. Cronin, et. al., filed of even date herewith.
Number | Name | Date | Kind |
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4888299 | Shiraishi et al. | Dec 1989 | |
5638288 | Deeley | Jun 1997 |
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Chao C.Chen and Shau-Lim Chow, "The Layout Synthesizer: An Automatic Netlist-to-Layout System," In Proc.26th ACM/IEEE Design Automation Conf., Jun. 1989, pp. 232-238. |
Chong-Leong Ong, Jeong-Tyng Li and Chi-Yuan Lo, "GENEC: An Automatic Cell Synthesis Tool," in Proc. 26th ACM/IEEE Design Automation Conf., Jun. 1989, pp. 239-244. |
G. Lakhani and S. Rao., "A multiple row-based layout generator for CMOS cells," ISCAS-90, pp. 1697-1700. |
M.Lefebvre and D.F.Skoll, "Picasso II: A CMOS leafe cell synthesis system, " in Proc. of International Workshop on Layout Synthesis, pp. 207-219, 1992. |
A.Domic,S.Levitin,N,Phillips,C.thai,T.Shipple,D.Bhavsar,and C.Bissell,"Cleo:a CMOS layout generator," in Proc. of Intl.Conf. on Computer-Aided Design, pp. 340-343, 1989. |
Y. Liao and S. Chow, "Routing considerations in symbolic layout synthesis," in Proc. of the 29th Design Automation Conference, pp. 682-686, 1992. |
J.Kim, S.M.Kang, and S.S.Sapatnekar, "High performance CMOS macromodule layout synthesis," in proc. of Intl. Symposium on Circuits and Systems, vol. 4 of 6, pp. 179-182, 1994. |
R.Bar-Yehuda,J.A.Feldman,R.Y.Pinter,S.Winder,"Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation, "IEEE Trans.on Computer-Aided Des.of ICs & Sys., vol.8, No.7, Jul. 1989, pp. 737-743. |
H.-R. Lin, H.-W. Perng, and Y.-C. Hsu, "Cell height reduction by routing over-the-cells," in Proc. of Intl. Symposium on circuits and Systems, pp. 2244-2247, 1992. |
F. Moraes, N.Azemard, M. Robert, and D. Auivergne, "Flexible macrocell layout generator,"in Proc. of Physical Design Workshop, pp. 105-116, 1993. |
B. Guan and C. Sechen, "Efficient standard cell generation when diffusion strapping is required," in Proc. of 5th Physical Design Workshop, pp. 268-272, 1996. |
K. Tani, et al, "Two-Dimmensional Layout Synthesis for Large-Scale CMOS Circuits," in Proceedings of Intl. Conference on Computer-Aided Design, 1991, pp. 490-493. |