Automatic Test Equipment (ATE) Realized Through Sharing Same Memory Space by Instruction Data and Vector Data

Information

  • Patent Application
  • 20070192661
  • Publication Number
    20070192661
  • Date Filed
    October 18, 2006
    17 years ago
  • Date Published
    August 16, 2007
    16 years ago
Abstract
An improved Automatic Test Equipment (ATE) in which Instruction Memory and a Vector Memory are combined together into a tester pattern memory in order to share the same memory space. As such, reducing the memory, size, and cost of the Automatic Test Equipment.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

The related drawings in connection with the detailed description of the present invention to be made later are described briefly as follows, in which:



FIG. 1 is a schematic diagram of an automatic test equipment (ATE) of the prior art;



FIG. 1A is the waveform of Vector Data transmitted to the programmable driver and comparator as shown in the ATE of FIG. 1;



FIG. 2 is a schematic diagram of another automatic test equipment (ATE) of the prior art;



FIG. 2A is the waveform of Vector Data and Instruction Data transmitted in the ATE of FIG. 2;



FIG. 3 is a schematic diagram of still another automatic test equipment (ATE) of the prior art;



FIG. 3A is the waveform of Data. Timing, Final Drive, Final Compare, DUT output, and Strobe Timing transmitted inside the ATE of FIG. 3;



FIG. 3B is the memory layout of the Control Memory and Pin Data Memory of the ATE of FIG. 3;



FIG. 4 is a schematic diagram of still another automatic test equipment (ATE) of the prior art;



FIG. 4A is a schematic diagram of the distributed 32-pin block memory of the ATE of FIG. 4;



FIG. 5 is a schematic diagram of an improved automatic test equipment (ATE) according to an embodiment of the present invention;



FIG. 5A is a memory layout for the distributed 16-pin block memory used in the ATE of FIG. 5;



FIG. 6 shows an example of Instruction and Pin Data executed through Register in the ATE of FIG. 5;



FIG. 7A is the distributed parallel processor ATE Test System according to prior art; and



FIG. 7B is the distributed parallel processor ATE Test System according to present invention.


Claims
  • 1. An improved automatic test equipment (ATE), comprising: an instruction memory; anda vector memory;wherein, the instruction memory and the vector memory share the same memory space in ATE, thus forming a tester pattern memory and sharing information in the ATE system, as such reducing the tester size and cost of ATE.
  • 2. The improved automatic test equipment (ATE) as claimed in claim 1, wherein one or more bits are utilized in the Tester Pattern Memory as an identifier to differentiate it between a Vector Word and an Instruction Word.
Priority Claims (1)
Number Date Country Kind
095105217 Feb 2006 TW national