Patent Application
20250048750
This application is filed based on and claims priority to Chinese Patent applications No. 202111643459.X, No. 202111633301.4 and No. 202111633446.4 which are filed on Dec. 29, 2021, the contents of which are hereby incorporated by reference in their entireties.
Embodiments of the disclosure relate to, but are not limited to, an avalanche photodetector and a method for preparing same.
As one of core components in a silicon photon architecture, an avalanche photodetector has a function of converting optical signals into electrical signals with a low power. A working principle of the avalanche photodetector is that photo-generated carriers (hole-electron pairs) generated by a photoelectric effect are rapidly accelerated when moving in a high electric field region. One or more collisions may occur during the movement. Through a collision ionization effect, secondary and tertiary new hole-electron pairs are generated, resulting in an avalanche multiplication effect, which makes the number of carriers increase rapidly, thus forming a relatively large optical signal current.
At present, germanium silicon (SiGe) materials compatible with a complementary metal oxide semiconductor (CMOS) process are widely used in a silicon photonic integrated chip to realize avalanche photodetection. A silicon material is used as an optical waveguide and also as an avalanche gain region (also referred to as a multiplication region), and a germanium (Ge) material is used to absorb photons. At present, the structure of the SiGe avalanche photodetector has following disadvantages. Firstly, an epitaxis process of monocrystalline silicon is required, which is complex in manufacturing. Secondly, an absorption region is usually P-type doped or N-type doped, which will cause light absorption loss and then reduce a quantum efficiency of the avalanche photodetector. Thirdly, the absorption region and the multiplication region are not easily adjustable independently, have a high precision requirement for concentrations in doped regions, and have a low process tolerance, which may easily lead to an unsatisfactory gain bandwidth. Therefore, the avalanche photodetector with SiGe materials needs further improvements.
In an aspect, embodiments of the disclosure provide an avalanche photodetector, including: a substrate, a surface of the substrate including a first semiconductor layer; and a second semiconductor layer on the first semiconductor layer, a material of the second semiconductor layer being different from a material of the first semiconductor layer. Here, the first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region arranged sequentially along a first direction, dopant concentrations decrease sequentially from the first P-type doped region to the third P-type doped region, dopant concentration decrease sequentially from the first N-type doped region to the third N-type doped region, and the first direction is a flow direction of electrons of the avalanche photodetector. The second semiconductor layer covers a portion of the second P-type doped region, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction. The first N-type doped region is connected to a first electrode; the third P-type doped region is connected to a second electrode; and the first P-type doped region is connected to a third electrode.
In some embodiments, the first intrinsic region, the third N-type doped region, a portion of the second P-type doped region adjacent to the third N-type doped region, and a portion of the third P-type doped region adjacent to the first intrinsic region in the first semiconductor layer have a first height H1 in a direction perpendicular to the substrate, and remaining zones in the first semiconductor layer have a second height H2. H1 is not equal to H2. The second semiconductor layer covers a portion of a zone of the second P-type doped region with the second height H2, a zone of the second P-type doped region with the first height H1, the third N-type doped region, the first intrinsic region, a zone of the third P-type doped region with the first height H1, and a portion of a zone of the third P-type doped region with the second height H2 sequentially along the first direction.
In some embodiments, H1 is greater than H2.
In some embodiments, H1 is smaller than H2.
In some embodiments, the avalanche photodetector further includes: an optical waveguide located on the first semiconductor layer, and including a front end close to a light incidence end and a tail end away from the light incidence end. A third height H3 of a portion of the second P-type doped region adjacent to the first P-type doped region in the first semiconductor layer is smaller than a fourth height H4 of remaining zones in the first semiconductor layer, to form a groove extending along a second direction, and the second direction is perpendicular to the first direction and is parallel to the surface of the substrate. The second semiconductor layer covers a portion of a zone the second P-type doped region with the fourth height H4, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction. The optical waveguide is located in the groove, and is arranged to extend roughly along the second direction and form a predetermined included angle with the second direction, to enable the front end to be close to the first P-type doped region and to enable the tail end to be close to the second P-type doped region with the fourth height H4.
In some embodiments, the optical waveguide is undoped or lightly doped.
In some embodiments, a first reverse bias voltage V1 is set between the first electrode and the third electrode, and a second reverse bias voltage V2 is set between the first electrode and the second electrode.
In some embodiments, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium silicon alloy, a III-V group material, and an alloy of the III-V group material.
In some embodiments, a dopant concentration in the first P-type doped region or the first N-type doped region is 1×1020/cm3˜5×1020/cm3, a dopant concentration in the second P-type doped region or the second N-type doped region is 2×1017/cm3˜5×1018/cm3, and a dopant concentration in the third P-type doped region or the third N-type doped region is 1.2×1017˜4×1017/cm3.
In some embodiments, a size of the second intrinsic region in the first direction is 50 nm to 800 nm.
In some embodiments, a size of the second semiconductor layer in the first direction is 150 nm to 1500 nm, a size of the second semiconductor layer in a second direction is 1 μm to 100 μm, and a size of the second semiconductor layer in a third direction is 150 nm to 600 nm. The third direction is perpendicular to the substrate, and the second direction is perpendicular to the third direction and is perpendicular to the first direction.
Embodiments of the disclosure further provide a method for preparing an avalanche photodetector, including the following operations. A substrate is provided. A surface of the substrate includes a first semiconductor layer. A selective doping process is performed, to form a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region sequentially along a first direction on the first semiconductor layer, dopant concentration decrease sequentially from the first P-type doped region to the third P-type doped region, and dopant concentrations decrease sequentially from the first N-type doped region to the third N-type doped region. A second semiconductor layer is formed. A material of the second semiconductor layer is different from a material of the first semiconductor layer, and the second semiconductor layer covers a portion of the second P-type doped region, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction. A first electrode, a second electrode and a third electrode that are perpendicular to a direction of a plane of the substrate are formed. The first electrode is electrically connected to the first N-type doped region. The second electrode is electrically connected to the third P-type doped region. The third electrode is electrically connected to the first P-type doped region. The first direction is a flow direction of electrons of the avalanche photodetector.
In some embodiments, the method further includes the following operation. Before performing the selective doping process, in zones where a portion of the second P-type doped region, a portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in a direction perpendicular to the substrate, a height different from a height of remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
In some embodiments, the operation that before performing the selective doping process, in the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed includes the following operation. In the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, a height H1 greater than a height H2 of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
In some embodiments, the operation that before performing the selective doping process, in the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed includes the following operation. In the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, a height H1 smaller than a height H2 of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
In some embodiments, the method further includes the following operation. Before performing the selective doping process, two wedge-shaped grooves are formed on zones where a portion of the second P-type doped region adjacent to the first P-type doped region is to be formed, to reserve a portion of the first semiconductor layer between the two wedge-shaped grooves.
In some embodiments, the portion of the first semiconductor layer reserved is undoped or lightly doped.
In some embodiments, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, germanium silicon alloy, a III-V group material and an alloy of the III-V group material.
In some embodiments, a dopant concentration in the first P-type doped region or the first N-type doped region is 1×1020/cm3˜5×1020/cm3, a dopant concentration in the second P-type doped region or the second N-type doped region is 2×1017/cm3˜5×1018/cm3, and a dopant concentration in the third P-type doped region or the third N-type doped region is 1.2×1017˜4×1017/cm3.
In some embodiments, the operation that the first electrode, the second electrode and the third electrode that are perpendicular to the direction of the plane of the substrate are formed includes the following operations. A cover layer covering the first semiconductor layer and the second semiconductor layer is formed. A first window, a second window and a third window are formed at an end of the first N-type doped region, an end of the third P-type doped region and an end of the first P-type doped region respectively along a second direction, to expose partial surfaces of the first P-type doped region, the third P-type doped region and the first N-type doped region. The second direction is perpendicular to the first direction and is parallel to the substrate. The first window, the second window and the third window are filled with metal, to form the first electrode, the second electrode and the third electrode.
One or more embodiments are described in an exemplary way with corresponding figures in the drawings, which do not constitute a limitation to the one or more embodiments, and the figures in the drawings do not constitute a limitation in scale unless specifically stated.
In order to make the technical solution and advantages of embodiments of the disclosure clearer, the technical solution of the disclosure is further described in detail below in combination with the drawings and particular embodiments.
In the embodiments of the disclosure, terms “first”, “second” and the like are used to distinguish similar objects, but are not used to describe a particular order or sequence.
In the embodiments of the disclosure, unless expressly specified and limited otherwise, an “on” or “below” relationship between two layers in a semiconductor structure may be a direct contact between the two layers, or an indirect contact between the two layers through an intermediate layer.
In the embodiments of the disclosure, a term “layer” refers to a material portion including a region with a thickness. The layer may extend on the entirety of an upper or lower structure, or may have a range smaller than that of the lower or upper structure. Further, the layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness smaller than a thickness of a continuous structure. For example, the layer may be located between top and bottom surfaces of the continuous structure, or the layer may be located between any horizontal plane pairs at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and/or along an inclined surface. Further, the layer may include multiple sub-layers.
In the embodiments of the disclosure, spatial relative terms such as “under”, “below”, “down”, “above”, “on”, “upward”, “downward” and the like may describe a relationship between (among) an element or feature and another (multiple) element(s) or feature(s) for ease of description in the disclosure, as shown in the drawings. The spatial relative terms aim to encompass different orientations of a component in use or operation, other than those depicted in the drawings. A device may be oriented in other ways (rotated by 90 degrees or in other orientations), and spatial relative descriptors used in the disclosure may be used to interpret the orientations accordingly.
Silicon (Si) photon technology is a new generation technology based on Si and a silicon substrate material (e.g., SiGe/Si, silicon-on-insulator (SOI), etc.), which uses an existing CMOS process to develop and integrate optical devices. The silicon photon technology combines characteristics of ultra-large scale and ultra-high precision manufacturing of an integrated circuit technology with advantages of ultra-high speed and ultra-low power consumption of a photon technology, which is a disruptive technology to address a failure of Moore's Law. This combination benefits from the scalability of semiconductor wafer manufacturing, and thus reducing costs. As one of core components in a silicon photon architecture, photodetectors have a function of converting optical signals into electrical signals. At present, a structure of a SiGe avalanche photodetector has following disadvantages. Firstly, an epitaxis process of monocrystalline silicon is required, which is complex in manufacturing. Secondly, an absorption region is usually P-type doped or N-type doped, which will cause light absorption loss and then reduce a quantum efficiency of the avalanche photodetector. Thirdly, the absorption region and the avalanche region (also referred to as a multiplication region) are not easily adjustable independently, have a high precision requirement for concentrations in doped regions, and have a low process tolerance, which may easily lead to an unsatisfactory gain bandwidth.
Based on this, the following technical solution in embodiments of the disclosure is proposed.
Embodiments of the disclosure provide an avalanche photodetector, including: a substrate, a surface of the substrate including a first semiconductor layer; and a second semiconductor layer on the first semiconductor layer, a material of the second semiconductor layer being different from a material of the first semiconductor layer.
Here, the first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region arranged sequentially along a first direction. Dopant concentrations decrease sequentially from the first P-type doped region to the third P-type doped region. Dopant concentrations decrease sequentially from the first N-type doped region to the third N-type doped region. The first direction is a flow direction of electrons of the avalanche photodetector.
The second semiconductor layer covers a portion of the second P-type doped region, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction.
The first N-type doped region is connected to a first electrode. The third P-type doped region is connected to a second electrode. The first P-type doped region is connected to a third electrode.
Please refer specifically to
With reference to
The substrate 10 includes a first semiconductor layer 300. An avalanche region of the avalanche photodetector is formed in the first semiconductor layer 300 to realize an avalanche effect.
The second semiconductor layer 400 is formed of a material different from a material of the first semiconductor layer 300.
A layout of each part of the avalanche photodetector of the disclosure is described in detail below.
Here, the substrate may have a multilayer structure. A top of the substrate is a first semiconductor layer. Under the first semiconductor layer, the substrate may include a layer composed of a monoatomic semiconductor material (e.g., Si, and Ge), a composite semiconductor material (e.g., SiGe), and an insulating layer composed of oxides of the monoatomic semiconductor material and the composite semiconductor material. In the embodiment, the substrate 10 may be such as SOI or germanium-on-insulator (GeOI).
The embodiment of the disclosure is described with a layer below the surface of the substrate being SOI as an example. It may be understood that the first semiconductor layer 300 is located at the top of the substrate 10 in the disclosure.
In some embodiments, the material of the first semiconductor layer 300 includes Si. Layers below the first semiconductor layer 300 include an insulating layer 200 and a bottom layer 100 sequentially.
In practical applications, the bottom layer 100 may be a Si wafer or a wafer formed by other materials. Therefore, a material of the bottom layer 100 may be Si, Ge, sapphire or the like.
In some embodiments, the material of the bottom layer 100 is Si, and correspondingly, a material of the insulating layer 200 may be an oxide of Si, such as Si dioxide.
The bottom layer 100 may have a greater thickness than the first semiconductor layer 300. It should be understood that in order to make the structure of each layer clearly shown in the drawings, a dimensional scale relationship of structures in the layers may be inconsistent with actual structures.
It should be noted that, for ease of description, as illustrated in
Here, the substrate 10 may include a top surface at a front side and a bottom surface at a back side opposite to the front side; and a direction perpendicular to the top and bottom surfaces of the substrate is defined as the third direction (Z) in a case of ignoring the flatness of the top and bottom surfaces. The third direction Z is a stacking direction of depositing the structure of each layer on the substrate, or is referred to as a height direction of components. A plane where the top and bottom surfaces of the substrate are located, or a central plane in a thickness direction of the substrate in a strict sense is determined as a plane of the substrate. The first direction (X) and the second direction (Y) intersecting each other (e.g., perpendicular to each other) are defined in a direction of the plane of the substrate. In the embodiment, the first direction X is a flow direction of electrons; and the second direction Y is a propagation direction of optical signals.
In theory, any semiconductor material may be used as a material of the first semiconductor layer 300 in the avalanche photodetector, thus the material of the first semiconductor is not strictly limited herein. In the embodiment where the substrate 10 includes a monoatomic Si bottom layer 100, the material of the first semiconductor is Si.
In order to realize an avalanche effect in the avalanche photodetector, different regions formed in the first semiconductor layer 300 of the avalanche photodetector include differently doped regions, including regions doped with different concentrations of P-type dopants and N-type dopants, and undoped regions (intrinsic regions).
A structure of the first semiconductor layer 300 of the avalanche photodetector according to embodiments of the disclosure is described in detail below. In some embodiments, the first semiconductor layer 300 in the avalanche photodetector includes a first P-type doped region 301, a second P-type doped region 302, a third N-type doped region 303, a first intrinsic region 304, a third P-type doped region 305, a second intrinsic region 306, a second N-type doped region 307, and a first N-type doped region 308 arranged sequentially along the first direction. Dopant concentrations of the first P-type doped region, the second P-type doped region, and the third P-type doped region decrease sequentially, and dopant concentrations of the first N-type doped region, the second N-type doped region, and the third N-type doped region decrease sequentially.
In some embodiments, the first intrinsic region, the third N-type doped region, a portion of the second P-type doped region adjacent to the third N-type doped region, and a portion of the third P-type doped region adjacent to the first intrinsic region in the first semiconductor layer have a first height H1 in a direction perpendicular to the substrate, and remaining zones in the first semiconductor layer have a second height H2. H1 is not equal to H2.
The second semiconductor layer covers a portion of a zone of the second P-type doped region with the second height H2, a zone of the second P-type doped region with the first height H1, the third N-type doped region, the first intrinsic region, a zone of the third P-type doped region with the first height H1, and a portion of a zone of the third P-type doped region with the second height H2 sequentially along the first direction.
In some embodiments, the height H1 of the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region, and the third N-type doped region in the first semiconductor layer in the direction perpendicular to the substrate is greater than the height H2 of the remaining zones in the first semiconductor layer.
In this case, combined with
It may be understood that, compared to the remaining zones in the first semiconductor layer, the portion of the second P-type doped region 302, the portion of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are protruding. From a perspective of the Y direction, the portion of the second P-type doped region 302, the portion of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 form an inverted U shape.
In some embodiments, as illustrated in
In this case, combined with
It may be understood that, compared to the remaining zones in the first semiconductor layer 300, the portion of the second P-type doped region 302, the portion of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are concave. From a perspective of the Y direction, the portion of the second P-type doped region 302, the portion of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 have a U shape.
In some embodiments, the avalanche photodetector further includes an optical waveguide.
The optical waveguide is located on the first semiconductor layer, and includes a front end close to a light incidence end and a tail end away from the light incidence end.
A third height H3 of a portion of the second P-type doped region adjacent to the first P-type doped region in the first semiconductor layer is smaller than a fourth height H4 of remaining zones in the first semiconductor layer, to form a groove extending along a second direction, and the second direction is perpendicular to the first direction and is parallel to the surface of the substrate.
The second semiconductor layer covers a portion of a zone the second P-type doped region with the fourth height H4, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction.
The optical waveguide is located in the groove, and is arranged to extend roughly along the second direction and form a predetermined included angle with the second direction, to enable the front end to be close to the first P-type doped region and to enable the tail end to be close to the zone of the second P-type doped region with the fourth height H4.
In some embodiments, as illustrated in
A portion of the second P-type doped region 302 adjacent to the first P-type doped region 301 in a second direction (Y) has a groove. That is, the second P-type doped region 302 consists of two parts: a second P-type doped I region 3021 and a second P-type doped II region 3022. Reference may be made to
In some embodiments, the P-type dopant may be boron (B), and the N-type dopant may be phosphorus (P) or arsenic (As).
In some embodiments, a dopant concentration in the first P-type doped region 301 or the first N-type doped region 308 is 1×1020/cm3˜5×1020/cm3, a dopant concentration in the second P-type doped region 302 or the second N-type doped region 307 is 2×1017/cm3˜5×1018/cm3, and a dopant concentration in the third P-type doped region 305 or the third N-type doped region 303 is 1.2×1017˜4×1017/cm3.
In practical applications, due to that intrinsic regions are undoped or lightly doped, dopant concentrations of the intrinsic regions are generally smaller than a predetermined value, for example, smaller than 1×1017/cm3.
It should be noted that dopant concentrations of the first P-type doped region and the first N-type doped region may be same or different, as long as the dopant concentrations are within the above range.
Similarly, dopant concentrations of the second P-type doped region and the second N-type doped region may be same or different, and dopant concentrations of the third P-type doped region and the third N-type doped region may be same or different.
The intrinsic regions may be an undoped or lightly doped first semiconductor material. Here, the intrinsic regions are regions where collision ionization occurs to produce electron-hole pairs.
In the first semiconductor layer 300 in the avalanche photodetector of the disclosure, an avalanche region may be the second intrinsic region 306.
It should be understood that the avalanche photodetector is based on that a voltage is applied to the avalanche region to produce an electric field, so as to extract photo-generated carriers by the electric field to form a current. Specifically, a bias voltage is applied between two sides of the avalanche region along the first direction to realize the photodetection.
In embodiments of the disclosure, a second semiconductor layer 400 is provided on the first semiconductor layer 300, and a material of the second semiconductor layer 400 is different from the material of the first semiconductor layer.
In some embodiments, the material of the first semiconductor layer is Si, and the material of the second semiconductor layer is one of Ge, SiGe alloy, a III-V group material, and an alloy of the III-V group material.
In further embodiments, the material of the first semiconductor layer 300 is Si, and the material of the second semiconductor layer is Ge. Therefore, an avalanche photodetector formed is a SiGe photodetector.
Here, due to that the second semiconductor layer 400 as an absorption region in the avalanche photodetector provided by the disclosure is not P-type doped or N-type doped and is not involved in Ohmic contact, light absorption loss can be reduced as much as possible, which is beneficial to improving a quantum absorption efficiency.
In the embodiment, the second semiconductor layer 400 of the avalanche photodetector covers a portion of the second P-type doped region 302, the third N-type doped region 303, the first intrinsic region 304, and a portion of the third P-type doped region 305 sequentially along the first direction. The second semiconductor layer 400 is formed as the absorption region of the avalanche photodetector.
In some embodiments, combining with
In some embodiments, combining with
In the above two cases, due to that a portion of the second P-type doped region, a portion of the third P-type doped region, the first intrinsic region and the third N-type doped region have the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate, and the second semiconductor layer covers a portion of a zone of the second P-type doped region with the second height H2, a zone of the second P-type doped region with the first height H1, the third N-type doped region, the first intrinsic region, a zone of the third P-type doped region with the first height H1, and a portion of a zone of the third P-type doped region with the second height H2 sequentially along the first direction, the second semiconductor layer has a larger contact area with the second P-type doped region and the third P-type doped region, which can improve a transmission efficiency of electrons participating in the avalanche effect subsequently.
Besides, a portion of the second P-type doped region 302 that is not covered by the second semiconductor layer has a groove, and the optical waveguide G is provided in the groove. The optical waveguide G is located at a surface of the second P-type doped I region 3021, that is, in the groove of the second P-type doped region 302. Please refer to
In some embodiments, the optical waveguide is undoped or lightly doped. Due to that the second P-type doped I region 3021 of the second P-type doped region 302 below the optical waveguide is P-type doped, ion implantation is physically blocked by the optical waveguide in practical processes. By setting appropriate doping conditions, P-type doping of the second P-type doped I region 3021 can be realized, while enabling the optical waveguide to be close to an intrinsic state.
By providing a separate optical waveguide G, incident light can be limited to propagate within the optical waveguide G, thus reducing the light propagation loss and improving the optical propagation efficiency. Further, the incident light passes through the optical waveguide G, then passes through the second P-type doped II region 3022 of the second P-type doped region 302, and then couples to the second semiconductor. This process is relatively slow and therefore relatively stable.
Here, when an optical signal is applied to the optical waveguide G of the avalanche photodetector, the optical waveguide G transfers the energy of the light to the second semiconductor layer 400 through the second P-type doped II region 3022 of the second P-type doped region 302. The second semiconductor layer 400 is capable of absorbing photons in the optical signal. According to Einstein's photoelectric effect, a photon produces a photo-generated electron. Therefore, the second semiconductor layer 400 absorbs photons and produces electrons which are photo-generated electrons.
Please refer to
Continuing with reference to
With the first electrode 501, the second electrode 502 and the third electrode 503 electrically connected to the first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301 respectively, by providing a first bias voltage V1 between the first electrode 501 and the third electrode 503, the first bias voltage V1 can be provided between the first N-type doped region 308 and the first P-type doped region 301. Further, by providing a second bias voltage V2 between the first electrode 501 and the second electrode 502, an additional second bias voltage V2 can be provided between the first N-type doped region 308 and the third P-type doped region 305.
As described above, the second semiconductor layer 400 as the absorption region connects the second P-type doped region 302 and the third P-type doped region 305 to form the carrier path. Therefore, by applying the electric field (i.e., by the first bias voltage V1) between the first N-type doped region 308 and the first P-type doped region 301, the energy of the photo-generated electrons above can be adjusted.
With regard to providing the second bias voltage V2 between the third P-type doped region 305 and the first N-type doped region 308, as the third P-type doped region 305 and the first N-type doped region 308 are respectively located between two sides of the second intrinsic region 306 which serves as the avalanche region, the second bias voltage V2 can regulate an electric field distribution in the avalanche region. The avalanche region of the avalanche photodetector refers to a region where carrier (electrons here) multiplication occurs, thus the avalanche region may also be referred to as a multiplication region. The absorption region of the avalanche photodetector can convert the incident optical signal into multiple electrons, and these electron pairs flow under the action of the electric field to form a photocurrent; the avalanche region can further excite a small number of electrons formed in the absorption region by the avalanche effect, to form a large number of electrons to realize amplification; and finally, a pair of metal electrodes conduct the photocurrent to realize the photodetection.
In the presence of the electric field (due to the first bias voltage V1 applied to the avalanche photodetector), the photo-generated electrons are accelerated towards the second intrinsic region 306 for multiplication. When passing through the second intrinsic region 306, the photo-generated electrons collide with other carriers bound in semiconductor atomic lattices, thereby producing more free carriers by a process referred to as “collision ionization”. These new free carriers are also accelerated by the applied electric field and more free carriers are produced.
Furthermore, in the embodiments of the disclosure, the arrangement of the third N-doped region 303, the first intrinsic region 304, and the third P-doped region 305 of the avalanche photodetector, and the concentration range of the dopants in the third N-doped region 303 and the third P-doped region 305 are beneficial to the electric field distribution in the second semiconductor layer 400 as the absorption region. Due to the existence of the first intrinsic region 304, electrons cannot pass through the first intrinsic region 304 even under the action of the first bias voltage V1, and the first intrinsic region 304 acts as a barrier to a certain extent. Electrons from the second P-doped region 302 can pass through the third N-doped region 303, through the second semiconductor layer 400, and then through the third P-doped region 305 towards the avalanche region.
The existing avalanche photodetectors only apply a bias voltage between two sides of the avalanche region, which has some disadvantages. For example, the absorption region and the avalanche region (also referred to as a multiplication region) are not easily adjustable independently, have a high precision requirement for concentrations in doped regions, and have a low process tolerance, which may easily lead to an unsatisfactory gain bandwidth. Therefore, in order to realize the above avalanche effect, the disclosure proposes to set a bias voltage between two sides of the absorption region the avalanche photodetector and also set a bias voltage between two sides of the avalanche region of the avalanche photodetector, that is, the first bias voltage V1 is provided between the first P-doped region 301 and the first N-doped region 308, and the second bias voltage V2 is provided between the first N-doped region 308 and the third P-type doped region 305. Therefore, electric fields corresponding to the absorption region and the avalanche region can be independently adjusted, and the gain bandwidth can be further improved.
It should be noted that the first bias voltage V1 and the second bias voltage V2 are independent from each other. The first bias voltage V1 acts on the absorption region, and a value of the first bias voltage V1 may be 1 to 4 volts. The second bias voltage V2 acts on the avalanche region, and a value of the second bias voltage V2 may be 3 to 20 volts.
In some embodiments, a size of the second intrinsic region 306 in the first direction X is 50 nm to 800 nm, that is, a width of the second intrinsic region 306 is within the above range. Therefore, a large bandwidth is realized while a higher gain is realized. Since the second intrinsic region 306 is an avalanche region of the avalanche photodetector in the embodiments of the disclosure, the size of the second intrinsic region 306 in the first direction X should not be too small. For example, when the size of the second intrinsic region 306 in the first direction X is smaller than 50 nm, electrons moving from the absorption region to the second intrinsic region do not have sufficient avalanche space and thus cannot be absorbed effectively, and the multiplication effect is poor. The size of the second intrinsic region 306 in the first direction X should not be too large, otherwise the voltage required between two sides of the avalanche region is too high, the time for electrons to avalanche is too long, the response is reduced, and the detection effect is affected.
In some embodiments, a size of the second semiconductor layer in the first direction X is 150 nm to 1500 nm, a size of the second semiconductor layer in the second direction Y is 1 μm to 100 μm, and a size of the second semiconductor layer in the third direction Z is 150 nm to 600 nm. The size of the second semiconductor layer in the embodiments of the disclosure is limited within the above range, thus the generated dark current can reduced while the noise is reduced and.
Here, when describing the size of the second semiconductor layer, size differences between the upper and lower surfaces of the second semiconductor layer during the epitaxis process may not be considered.
It should be noted that a shape of the second semiconductor layer 400 in a plane parallel to the substrate 10 may be a regular rectangle, as illustrated in
The avalanche photodetector of the disclosure may further include a cover layer covering the first semiconductor layer 300, the second semiconductor layer 400, the first electrode 501, the second electrode 502, and the third electrode 503 (as illustrated in
It should be noted that the structure of the avalanche photodetector of the disclosure may also be its own mirror structure. For example, referring to
The avalanche photodetector provided by the embodiments of the disclosure includes: a substrate and a second semiconductor layer. A surface of the substrate includes a first semiconductor layer. The second semiconductor layer is located on the first semiconductor layer, and a material of the second semiconductor layer is different from a material of the first semiconductor layer. Here, the first semiconductor layer includes a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region arranged sequentially along a first direction. Dopant concentration decrease sequentially from the first P-type doped region to the third P-type doped region, and dopant concentrations decrease sequentially from the first N-type doped region to the third N-type doped region. The first direction is a flow direction of electrons of the avalanche photodetector. The second semiconductor layer covers a portion of the second P-type doped region, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction. The first N-type doped region is connected to a first electrode, the third P-type doped region is connected to a second electrode, and the first P-type doped region is connected to a third electrode. Since multiple doped charge regions and the second intrinsic region as the avalanche region are all provided in the first semiconductor layer, there is no need for additional epitaxis to fabricate monocrystalline silicon, and the fabrication is relatively simple, which is beneficial to reducing the cos. Further, since the first N-type doped region is connected with the first electrode, the third P-type doped region is connected with the second electrode, and the first P-type doped region is connected with the third electrode, bias voltages may be applied to the three electrodes independently; thus electric fields in the second semiconductor layer as the absorption region and the second intrinsic region as the avalanche region may be independently adjusted, and a tolerance for the concentration accuracy of doped regions is better, which is beneficial to realizing low noise and high gain bandwidth.
Embodiments of the disclosure further provide a method for preparing an avalanche photodetector. As illustrated in
At 201, a substrate is provided. A surface of the substrate includes a first semiconductor layer.
At 202, a selective doping process is performed, to form a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region, and a first N-type doped region sequentially along a first direction on the first semiconductor layer.
At 203, a second semiconductor layer is formed. A material of the second semiconductor layer is different from a material of the first semiconductor layer. The second semiconductor layer covers a portion of the second P-type doped region, the third N-type doped region, the first intrinsic region, and a portion of the third P-type doped region sequentially along the first direction.
At 204, a first electrode, a second electrode and a third electrode that are perpendicular to a direction of a plane of the substrate are formed. The first electrode is electrically connected to the first N-type doped region. The second electrode is electrically connected to the third P-type doped region. The third electrode is electrically connected to the first P-type doped region.
The first direction above is a flow direction of electrons of the avalanche photodetector.
Hereinafter, the avalanche photodetector and the method for preparing same according to the embodiments of the disclosure are described in further detail with reference to the cutaway views of component structures of the avalanche photodetector during preparation in
Firstly, operation 201 is performed. A substrate is provided, and the substrate includes the first semiconductor layer.
Please refer to
The embodiments of the disclosure are described with the substrate 10 being SOI as an example. It may be understood that the first semiconductor layer 300 is located at the surface of the substrate 10 of the disclosure.
The substrate 10 further includes an intermediate layer 200 (which may be an insulating layer in practical applications) and a bottom layer 100 (which may be a Si layer in practical applications) that are located under the first semiconductor layer 300. The insulating layer 200, for example, is a silicon dioxide layer, which may be obtained directly by thermally oxidating the bottom layer 100. The bottom layer 100 may have a greater thickness than the first semiconductor layer 300.
Next, operation 202 is performed. Please refer to
In practical processes, a mask plate lithography process may be to sequentially windowing for regions that need to be doped. Subsequently, ion implantation is performed in the windows, to form the above doped regions with different dopant concentrations.
Specifically, a dopant concentration in the first P-type doped region or the first N-type doped region is 1×1020/cm3˜5×1020/cm3, a dopant concentration in the second P-type doped region or the second N-type doped region is 2×1017/cm3˜5×1018/cm3, and a dopant concentration in the third P-type doped region or the third N-type doped region is 1.2×1017˜4×1017/cm3. In some embodiments, a dopant in the first P-type doped region 301, the second P-type doped region 302, and the third P-type doped region 305 is boron (B); and a dopant of the first N-type doped region 308, the second N-type doped region 307, and the third N-type doped region 303 is the phosphorus (P) element or the arsenic (As) element.
In some embodiments, the method further includes the following operation.
Before performing the selective doping process, in zones where a portion of the second P-type doped region, a portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in a direction perpendicular to the substrate, a height different from a height of remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
In some embodiments, the operation that before performing the selective doping process, in the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed includes the following operation.
In the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, a height H1 greater than a height H2 of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
In other embodiments, the operation that before performing the selective doping process, in the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed includes the following operation.
In the zones where the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed, in the direction perpendicular to the substrate, a height H1 smaller than a height H2 of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate is formed.
Here, in the two embodiments above, the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region in the first semiconductor layer in the avalanche photodetector have the height different from the height of the remaining zones in the first semiconductor layer in the direction perpendicular to the substrate; therefore, the height of the second semiconductor layer covering the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region, and the third N-type doped region is also correspondingly different in the two embodiments. In addition to this, other parts of the two avalanche photodetectors are same. Therefore, the method for preparing the avalanche photodetector provided in the embodiments of the disclosure will be described herein with an example that the height H1 of the portion of the second P-type doped region, the portion of the third P-type doped region, the first intrinsic region and the third N-type doped region in the first semiconductor layer in the direction perpendicular to the substrate is greater than the height H2 of the remaining zones in the first semiconductor layer.
Here, before performing the selective doping process, in the zones where the portion of the second P-type doped region 302, the portion of the third P-type doped region 303, the first intrinsic region 304 and the third N-type doped region 303 are to be formed, in the direction (direction Z) perpendicular to the substrate the height different from the height of the remaining zones in the first semiconductor layer 300 is formed. In practical applications, different heights of different zones may be realized by using a process combination of lithography, etching, etc. The method includes that in the zones where the portion of the second P-type doped region 302, the portion of the third P-type doped region 305, the first intrinsic region 304 and the third N-type doped region 303 are to be formed, in the direction perpendicular to the substrate, the height H1 greater than the height H2 of the remaining zones in the first semiconductor layer is formed.
Next, operation 203 is performed. Please refer to
In some embodiments, an initial second semiconductor layer 400′ (not shown in
Here, a shape of the second semiconductor layer 400 formed is rectangular (the second semiconductor layer 400 in
In some embodiments, a material of the first semiconductor layer is different from a material of the second semiconductor layer. For example, in a case where the material of the first semiconductor layer is Si, the material of the second semiconductor layer is one of Ge, SiGe alloy, a III-V group material and an alloy of the III-V group material.
In a specific embodiment of the avalanche photodetector according to the embodiments of the disclosure, the material of the first semiconductor layer is Si, and the material of the second semiconductor layer is Ge. In other words, the avalanche photodetector according to the embodiments of the disclosure is a SiGe avalanche photodetector.
Processes such as molecular beam epitaxis may be used to grow high-quality polycrystalline germanium materials by epitaxis, that is, forming the second semiconductor layer.
Next, operation 204 is performed. Please refer to
In some embodiments, the operation that the first electrode 501, the second electrode 502 and the third electrode 503 that are perpendicular to the direction of the plane of the substrate are formed includes the following operations.
A cover layer 600 covering the first semiconductor layer 300 and the second semiconductor layer 400 is formed.
A first window, a second window and a third window are formed above the first N-type doped region 308, the third P-type doped region 305, and the first P-type doped region 301 respectively.
The first window, the second window and the third window are filled with metal, to form the first electrode 501, the second electrode 502 and the third electrode 503 respectively.
In an embodiment, the cover layer 600 may be formed directly by an insulating material. Referring to
After the electrodes are formed, an upper surface of the cover layer 600 may further be flattened, which may be realized by a chemical mechanical polishing (CMP) process. In this way, different voltages may be applied between the first electrode 501 and the second electrode 502, and may be applied between the first electrode 501 and the third electrode 503 through external leads, to provide a bias voltage between the first electrode 501 and the second electrode 502 and a bias voltage between the first electrode 501 and the third electrode 503.
Hereinafter, the avalanche photodetector and the method for preparing same provided in the embodiments of the disclosure are further explained with reference to the cutaway views of component structures of the avalanche photodetector during preparation in
Firstly, operation 201 is performed.
As illustrated in
Next, two wedge-shaped grooves C are formed on zones where a portion of the second P-type doped region adjacent to the first P-type doped region is to be formed, referring to
In practical processes, the two wedge-shaped grooves C above may be formed by mask plate combined with etching, thus forming the portion of the first semiconductor layer G between the two wedge-shaped grooves C.
Next, operation 202 is performed. Please refer to
As described above, the portion of the first semiconductor layer G reserved between the two wedge-shaped grooves C is not doped or lightly doped. In practical processes, a mask lithography process may be used to perform windowing for regions that need to be doped subsequently. Subsequently, ion implantation is performed in windows to form doped regions with different dopant concentrations. By utilizing appropriate ion implantation process, the portion of the first semiconductor layer G is undoped or lightly doped.
Next, operation 203 is performed. Please, refer to
Next, operation 204 is performed. Please refer to
In some embodiments, as illustrated in
A cover layer 600 covering the first semiconductor layer 300 and the second semiconductor layer 400 is formed.
A first window, a second window and a third window are formed above the first N-type doped region 308, the third P-type doped region 305 and the first N-type doped region 308 respectively.
The first window, the second window and the third window are filled with a metal material, to form the first electrode 501, the second electrode 502 and the third electrode 503 respectively.
It should be noted that in the above-described method illustrated in
It should be noted that the embodiments of the avalanche photodetector provided in the disclosure belongs to a same concept as the embodiments of the method for manufacturing the avalanche photodetector. Technical features in the technical solution described in various embodiments may be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the avalanche photodetector provided in the embodiment of the disclosure can already solve the technical problems to be solved by the disclosure; therefore, the avalanche photodetector provided in the embodiments of the disclosure may not be limited by the method for manufacturing the avalanche photodetector provided in the embodiments of the disclosure, and avalanche photodetectors prepared by any preparation method capable of forming the avalanche photodetector provided in the embodiments of the disclosure are within the scope of protection of the disclosure.
The above are only preferred embodiments of the disclosure, and are not intended to limit the scope of protection of the disclosure. Any modification, equivalent replacement and improvement made within the spirit and principles of the disclosure should be included within the scope of protection of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 20211633301.4 | Dec 2021 | CN | national |
| 202111633446.4 | Dec 2021 | CN | national |
| 202111643459.X | Dec 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/141400 | 12/23/2022 | WO |
