TREA

BACK-END-OF-LINE VERTICAL-TRANSPORT TRANSISTOR

Follow

Information

  • Patent Application
  • 20230299205
  • Publication Number
    20230299205
  • Date Filed
    March 18, 2022
    2 years ago
  • Date Published
    September 21, 2023
    8 months ago
Information
Abstract
A semiconductor structure including a bottom source drain region arranged above front-end-of-line circuitry, a gate region disposed above and insulated from the bottom source drain region, a top source drain region disposed above and insulated from the gate region, and a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
Description
Claims
  • 1. A semiconductor structure comprising: a bottom source drain region arranged above front-end-of-line circuitry;a gate region disposed above and insulated from the bottom source drain region;a top source drain region disposed above and insulated from the gate region; anda channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
  • 2. The semiconductor structure according to claim 1, further comprising: a bottom contact partially embedded into the bottom source drain region;a top contact partially embedded into the top source drain region; anda gate contact partially embedded into the gate region.
  • 3. The semiconductor structure according to claim 1, further comprising: a gate dielectric separating the gate region from the channel region, the gate dielectric extends vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
  • 4. The semiconductor structure according to claim 1, wherein a width of the bottom source drain region is greater than a width of the top source drain region.
  • 5. The semiconductor structure according to claim 1, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain region; anda top gate spacer above the gate region insulating the gate region from the top source drain region.
  • 6. The semiconductor structure according to claim 1, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain region; anda top gate spacer above the gate region insulating the gate region from the top source drain region,wherein a combined height of the bottom gate spacer, the gate region, and the top gate spacer is equal to a height of both the gate dielectric and the channel region.
  • 7. The semiconductor structure according to claim 1, wherein the channel region comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.
  • 8. A semiconductor structure comprising: bottom source drain regions arranged above front-end-of-line circuitry;a single gate region disposed above and insulated from the bottom source drain regions;top source drain regions disposed above and insulated from the gate region; andchannel regions adjacent to the gate region, each channel region extending vertically from a top surface of one of the bottom source drain regions to a bottom surface of one of the top source drain regions.
  • 9. The semiconductor structure according to claim 1, further comprising: bottom contacts partially embedded into the bottom source drain regions;top contacts partially embedded into the top source drain regions; anda gate contact partially embedded into the gate region.
  • 10. The semiconductor structure according to claim 8, further comprising: gate dielectric separating the gate region from the channel regions, each of the gate dielectric extend vertically from the top surface of one of the bottom source drain regions to the bottom surface of one of the top source drain regions.
  • 11. The semiconductor structure according to claim 8, wherein a width of one of the bottom source drain regions is greater than a width of one of the top source drain regions.
  • 12. The semiconductor structure according to claim 8, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain regions; anda top gate spacer above the gate region insulating the gate region from the top source drain regions.
  • 13. The semiconductor structure according to claim 8, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain regions; anda top gate spacer above the gate region insulating the gate region from the top source drain regions,wherein a combined height of the bottom gate spacer, the gate region, and the top gate spacer is equal to a height of both the gate dielectric and the channel regions.
  • 14. The semiconductor structure according to claim 8, wherein the channel regions comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.
  • 15. A semiconductor structure comprising: a bottom source drain region arranged above front-end-of-line circuitry;a single gate region disposed above and insulated from the bottom source drain region;a top source drain region disposed above and insulated from the gate region; anda channel region surrounding the gate region, the channel region extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
  • 16. The semiconductor structure according to claim 15, further comprising: gate dielectric separating the gate region from the channel region, each of the gate dielectric extend vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.
  • 17. The semiconductor structure according to claim 15, wherein a width of the bottom source drain region is greater than a width of the top source drain region.
  • 18. The semiconductor structure according to claim 15, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain region; anda top gate spacer above the gate region insulating the gate region from the top source drain region.
  • 19. The semiconductor structure according to claim 15, further comprising: a bottom gate spacer directly below the gate region insulating the gate region from the bottom source drain region; anda top gate spacer above the gate region insulating the gate region from the top source drain region,wherein a combined height of the bottom gate spacer, the gate region, and the top gate spacer is equal to a height of both the gate dielectric and the channel region.
  • 20. The semiconductor structure according to claim 15, wherein the channel region comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.