Patent Application
20100327390
The present invention relates generally to image sensors for use in digital cameras and other types of image capture devices, and more particularly to back-illuminated image sensors.
An electronic image sensor captures images using light-sensitive photodetectors that convert incident light into electrical signals. Image sensors are generally classified as either front-illuminated image sensors or back-illuminated image sensors. As the image sensor industry migrates to smaller and smaller pixel designs to increase resolution and reduce costs, the benefits of back-illumination become clearer. In front-illuminated image sensors, the electrical control lines or conductors are positioned between the photodetectors and the light-receiving side of the image sensor. The consequence of this positioning is the electrical conductors block part of the light that should be received by the photodetectors, resulting in poor quantum efficiency (QE) performance, especially for small pixels. For back-illuminated image sensors, the electrical control lines or conductors are positioned opposite the light-receiving side of the sensor and do not reduce QE performance. Back-illuminated image sensors therefore solve the QE performance challenge of small pixel designs.
Pixel size is decreasing in an effort to increase the number of pixels 128 included in an image sensor. One advantage to smaller pixels is the increased resolution of an image for a fixed optical format. Specifically, smaller pixels have a better modulation transfer function (MTF), and can thus discriminate fine details in an image, such as the lines on a thinly striped shirt. However, with a back-illuminated image sensor, reducing the size of pixels 128 does not necessarily improve MTF performance because the electric field within sensor layer 104 near backside 108 is low. Photogenerated carriers that are created within a low electric field region can diffuse laterally. Specifically, at room temperature, photocarriers can diffuse against electric fields of less than 1000 V/cm in magnitude with significant probability. Carriers that diffuse laterally have a significant probability of being collected by the photodetectors 114 in adjacent pixels. Low electric field regions near backside 108 lead to poor MTF performance and therefore poor color crosstalk performance.
MTF performance can be improved in the back-illuminated n-channel metal oxide semiconductor (NMOS) image sensor of
As illustrated in
The triple well design creates more performance related issues than it solves. First, the addition of the triple well increases the footprint of the pixel transistors and shrinks the size of photodetectors 114, thereby reducing photodetector capacity. Second, surrounding the shallow p-well 122 and p-type implants 136, 138 with the n-type photodetector 114 and n-type implant 132 adversely impacts the manufacturability of transfer gates 118. The p+ implants 136 must be pulled back from transfer gates 118 in order to isolate the p+ implant 136 from the p− epitaxial layer of sensor layer 104. The small n-type regions that are part of photodetector 114 disposed between p+ implants 136 and transfer gates 118 create pockets that degrade lag performance. Third, the combination of n− implant 132, p-well 122, and n-type charge-to-voltage conversion mechanism 134 under and adjacent to transfer gate 118 also leads to lag performance issues during manufacturing. This is because of the need to tightly control alignment. Fourth, the region of the triple well where there is a sharp n-p-n junction just under transfer gate 118 creates a high electric field region that enhances bright point generation.
A back-illuminated image sensor includes a sensor layer having a frontside and a backside opposite the frontside. The back-illuminated image sensor includes a plurality of pixels, with each pixel including a photodetector of a first conductivity type disposed in the sensor layer adjacent to the frontside. An insulating layer is disposed over the backside, and one or more contacts are disposed in the insulating layer. A backside well of the second conductivity type is disposed in the sensor layer adjacent to the insulating layer. One or more contact implant regions of the second conductivity type are formed in the backside well and in the sensor layer and electrically connect the backside well to respective contacts. The one or more contact implant regions can have a higher dopant concentration than a dopant concentration of the backside well. At least a portion of the contact implant regions are arranged in a shape that corresponds to one or more pixel edges.
The present invention has the advantage of providing a back-illuminated image sensor with improved cross talk performance.
Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other.
Throughout the specification and claims the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active or passive, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, or data signal.
Additionally, directional terms such as “on”, “over”, “top”, “bottom”, are used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is in no way limiting. When used in conjunction with layers of an image sensor wafer or corresponding image sensor, the directional terminology is intended to be construed broadly, and therefore should not be interpreted to preclude the presence of one or more intervening layers or other intervening image sensor features or elements. Thus, a given layer that is described herein as being formed on or formed over another layer may be separated from the latter layer by one or more additional layers.
Referring to the drawings, like numbers indicate like parts throughout the views.
In digital camera 200, light 202 from a subject scene is input to an imaging stage 204. Imaging stage 204 can include conventional elements such as a lens, a neutral density filter, an iris and a shutter. Light 202 is focused by imaging stage 204 to form an image on image sensor 206. Image sensor 206 captures one or more images by converting the incident light into electrical signals. Digital camera 200 further includes processor 208, memory 210, display 212, and one or more additional input/output (I/O) elements 214. Although shown as separate elements in the embodiment of
Processor 208 may be implemented, for example, as a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), or other processing device, or combinations of multiple such devices. Various elements of imaging stage 204 and image sensor 206 may be controlled by timing signals or other signals supplied from processor 208.
Memory 210 may be configured as any type of memory, such as, for example, random access memory (RAM), read-only memory (ROM), Flash memory, disk-based memory, removable memory, or other types of storage elements, in any combination. A given image captured by image sensor 206 may be stored by processor 208 in memory 210 and presented on display 212. Display 212 is typically an active matrix color liquid crystal display (LCD), although other types of displays may be used. The additional I/O elements 214 may include, for example, various on-screen controls, buttons or other user interfaces, network interfaces, or memory card interfaces.
It is to be appreciated that the digital camera shown in
Referring now to
Image sensor 206 further includes column decoder 304, row decoder 306, digital logic 308, and analog or digital output circuits 310. Image sensor 206 is implemented as a back-illuminated Complementary Metal Oxide Semiconductor (CMOS) image sensor in an embodiment in accordance with the invention. Thus, column decoder 304, row decoder 306, digital logic 308, and analog or digital output circuits 310 are implemented as standard CMOS electronic circuits that are electrically connected to imaging area 302.
Functionality associated with the sampling and readout of imaging area 302 and the processing of corresponding image data may be implemented at least in part in the form of software that is stored in memory 210 and executed by processor 208 (see
Photodetector 402 is configured as a pinned photodiode, charge-to-voltage conversion mechanism 406 as a floating diffusion, and amplifier transistor 410 as a source follower transistor in an embodiment in accordance with the invention. Pixel 300 can be implemented with additional or different components in other embodiments in accordance with the invention. By way of example only, photodetector 402 is configured as an unpinned photodetector in another embodiment in accordance with the invention.
Transfer gate 404 is used to transfer collected photo-generated charges from the photodetector 402 to charge-to-voltage conversion mechanism 406. Charge-to-voltage conversion mechanism 406 is used to convert the photo-generated charge into a voltage signal. Amplifier transistor 410 buffers the voltage signal stored in charge-to-voltage conversion mechanism 406 and amplifies and transmits the voltage signal to output line 412. Reset transistor 408 is used to reset charge-to-voltage conversion mechanism 406 to a known potential prior to readout. Output line 412 is connected to readout and image processing circuitry (not shown). As shown, the embodiment in
Embodiments in accordance with the invention are not limited to the pixel structure shown in
Referring now to
Each pixel 500 includes a photodetector 520 for converting light 522 incident on backside 508 into photo-generated charges 524, 526. Photodetectors 520 are disposed adjacent to frontside 506. In the illustrated embodiment, sensor layer 504 is implemented as an epitaxial layer having a p conductivity type, and photodetectors 520 are formed by implanting one or more dopants having a p conductivity type into the epitaxial layer.
Transfer gate 528 is used to transfer collected photo-generated charges from a respective photodetector 520 to a p conductivity type charge-to-voltage conversion mechanism 530, which is configured as a floating diffusion in the illustrated embodiment. Charge-to-voltage conversion mechanism 530 resides in a shallow well 532 of an n conductivity type.
One or more regions having an n-type conductivity are formed in at least a portion of sensor layer 504 adjacent to frontside 506 and are electrically connected to a voltage terminal 534 for biasing the n-type regions to a predetermined voltage. In the illustrated embodiment, the n-type regions adjacent to frontside 506 include the shallow n-well 532 surrounding charge-to-voltage conversion mechanism 530, the shallow n-well surrounding the p+ nodes of reset and source/follower transistors (not shown), the n-type pinning layer 536 disposed over each photodetector 520, and the n-type pinning layer 538 that lines the shallow trench isolation (STI) 540. The n-type regions adjacent to frontside 506 are biased to a known voltage level VbiasA through voltage terminal 534. Although not shown in
A backside well 542 having an n conductivity type, which is a deep n-well in some embodiments, is formed in sensor layer 504 adjacent to backside 508, and is electrically connected to voltage terminal 544 through n-type connecting regions 546. In most embodiments, voltage terminal 544 is positioned at the edge of the imaging array. Backside well 542 is biased to a known voltage level VbiasB through voltage terminal 544. In one or more embodiments in accordance with the invention, a ground bias between VbiasA 534 and VbiasB 544 is included to eliminate biasing problems during power-up.
For a PMOS image sensor, VbiasB is more positive than VbiasA. This creates an electric field between the backside well 542 and frontside regions 532, 536, 538. This electric field drives photo-induced holes 526 toward the surface of frontside 506, thereby reducing electrical crosstalk. One desirable result of biasing backside well 542 at a higher voltage potential than the frontside regions 532, 536, 538 is the increased size of the depletion region 548 of each photodetector 520.
A few differences between the prior art NMOS configuration in United States Patent Application 2008/0217723 A1 and the embodiment illustrated in
Although the embodiment shown in
Referring now to
Opaque lightshield 600 and contacts 702 are formed from the same material, such as a single metal, in an embodiment in accordance with the invention. Other embodiments in accordance with the invention can fabricate lightshield 600 and contacts 702 from different materials, such as aluminum and tungsten.
The second voltage terminal 544 and connecting regions 542 are not included in the embodiment of
As discussed earlier, VbiasB is greater than VbiasA in a PMOS image sensor. This potential difference creates an electric field between the n-type backside well 542 and n-type contact implant regions 700 and the frontside n-type regions 532, 536, 538. This electric field drives most photoinduced holes 524, 526 toward the surface of frontside 508, reducing electrical crosstalk as well as increasing the size of depletion region 548. Additionally, contact implant regions 700 steer the photoinduced holes 526 in backside well 542 towards the center of each pixel. The fringing electric fields from lightshield 600 also help steer photoinduced holes 526 toward the center of each pixel. This steering improves device MTF and reduces color crosstalk, especially for blue light.
The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, the present invention has been described with reference to a PMOS back-illuminated image sensor. Other embodiments in accordance with the invention can reverse the conductivity types in a back-illuminated image sensor.
Additionally, even though specific embodiments of the invention have been described herein, it should be noted that the application is not limited to these embodiments. In particular, any features described with respect to one embodiment may also be used in other embodiments, where compatible. And the features of the different embodiments may be exchanged, where compatible.
