Battery management system chip and data-accessing method of the same

Abstract

A battery management system includes a flash memory chip having a smart battery management program and a microprocessor. An interface model (I/F module) is installed in the microprocessor as a bridge between the flash chip and the microprocessor. The I/F module includes a data register and an address register as a data buffer and address buffer, respectively, between the CPU and the flash chip. The I/F module also includes a logic control circuit to generate signals for the flash chip to read and program.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which:

FIG. 1 is a block circuit diagram of a preferred battery management system chip in accordance with the present invention;

FIG. 2 shows a typical time sequence of the battery management system in accordance with the present invention; and

FIG. 3 shows a time sequence of a write operation from the battery management system to a flash chip in accordance with the present invention.

Claims

1. A battery management system, comprising: a flash chip for storing learning programs related to battery management; anda battery management microprocessor, further including: a CPU;a ROM for storing application programs related to the battery management; anda flash I/F module, further including a first multiplexer, a data register, an address register, a plurality of control registers, a control logic circuit and a decoder;

2. The battery management system according to claim 1, wherein said control registers, said control logic circuit and said decoder are used to provide signals to remove a write protection of the said flash chip while in writing said flash chip.

3. The battery management system according to claim. 1, wherein said battery management microprocessor further includes an I/O port for inputting data to write into said flash chip.

4. The battery management system according to claim 1, wherein parameters of said learning program are updated by a data from the group of data from said CPU calculating an application program stored in said ROM, data from said CPU calculating another application program stored in said flash chip, and data importing from said I/O port.

5. The battery management system according to claim 1, wherein said device flash chip, said device data bus, said device address bus, and said flash data bus are 8-bit elements, and wherein said flash address bus, said CPU and said ROM are 16-bit elements.

6. The battery management system according to claim 5, wherein said address register is a 16-bit register to receive little endian addresses and big endian addresses transmitted from said 8-bit device data bus.

7. The battery management system according to claim 1, wherein said flash chip needs a write control signal to perform data writing, which the write control signal is generated by said control logic circuit, and wherein said control logic circuit also generates control bits to control operation of said flash I/F module.

8. The battery management system according to claim 1, further including a second multiplexer for determining whether an address to be dumped to said address register is from said instruction address bus or from said device data register.

9. The battery management system according to claim 1, wherein said control logic circuit further includes a pulse generation circuit for adjusting pulse widths of said control signals.