The present disclosure relates to functional verification of a design of a circuit, and more particularly, to localizing constraints that may trigger a designated message during simulation of the design.
Designing a circuit may be an arduous process, particularly for today's complex System-on-Chip (SoC) circuits. The design is commonly thoroughly tested to ensure functionality, specifications, and reliability. The importance of these tests prior to tape out and fabrication is significant as the costs and complexity of tape out and fabrication is substantial. Fabricating a circuit that does not meet the necessary specification, does not operate as intended, and/or is not reliable may result in large wasted costs.
An example is a method. A control binary sequence that was determined during simulating a design under test (DUT) is obtained. Simulating the DUT was based on using a constraint random stimulus generator and a coverage biaser biasing the constraint random stimulus generator. The control binary sequence includes first enabled bits that correspond to respective constraint problems solved by the constraint random stimulus generator and biased by the coverage biaser and from which a designated message was triggered during the simulating the DUT. A reduced control binary sequence that has second enabled bits that are a subset of the first enabled bits is constructed by one or more processors. A simulation result generated by re-simulating the DUT is obtained. Re-simulating the DUT includes selectively, for each constraint problem of the constraint problems, restoring solving steps of the constraint random stimulus generator for the respective constraint problem that were performed during the simulating the DUT when a corresponding bit of the reduced control binary sequence is an enabled bit of the second enabled bits. Whether the simulation result includes the designated message is determined. The reduced control binary sequence is assigned as a triggering control binary sequence that triggered the designated message when the simulation result includes the designated message.
Another example is a non-transitory computer-readable medium. The non-transitory computer-readable medium includes stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain a control binary sequence that was determined during simulating a design under test (DUT), construct a reduced control binary sequence, obtain a simulation result generated by re-simulating the DUT, determine whether the simulation result includes a designated message, and assign the reduced control binary sequence as a triggering control binary sequence that triggered the designated message when the simulation result includes the designated message. Simulating the DUT was based on using a constraint random stimulus generator and a coverage biaser biasing the constraint random stimulus generator. The control binary sequence includes first enabled bits that correspond to respective constraint problems solved by the constraint random stimulus generator and biased by the coverage biaser and from which a designated message was triggered during the simulating the DUT. The reduced control binary sequence has second enabled bits that are a subset of the first enabled bits. Re-simulating the DUT includes selectively, for each constraint problem of the constraint problems, restoring solving steps of the constraint random stimulus generator for the respective constraint problem that were performed during the simulating the DUT when a corresponding bit of the reduced control binary sequence is an enabled bit of the second enabled bits.
A further example is a non-transitory computer-readable medium. The non-transitory computer-readable medium includes stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain an original control binary sequence that was generated during simulating a design under test (DUT); initiate an index range with an upper index and a lower index; and iteratively until (A) an index set is determined such that re-simulating the DUT based on a reduced control binary sequence triggers the designated message, or (B) a termination condition is reached: determine a lowest upper index in the index range and a highest lower index in the index range, collect the lowest upper index and the highest lower index in the index set, and set the upper index to be one less than the lowest upper index and the lower index to be one more than the highest lower index. Simulating the DUT was based on stimulus values generated using a constraint random stimulus generator and a coverage biaser biasing the constraint random stimulus generator. Simulating the DUT generates the original control binary sequence. The original control binary sequence includes first enabled bits that correspond to respective constraint problems solved by the constraint random stimulus generator and from which a designated message was triggered during the simulating the DUT. The reduced control binary sequence has second enabled bits, and each enabled bit of the second enabled bits corresponds to a respective enabled bit of the first enabled bits at a respective index in the index set. In an iteration, the designated message is triggered by a re-simulation of the DUT based on a first control binary sequence. The first control binary sequence has third enabled bits, and each enabled bit of the third enabled bits corresponds to a respective enabled bit of the first enabled bits at a respective index in the index set or at a respective index in a range from the highest lower index to the lowest upper index.
The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale.
Aspects of the present disclosure relate to bias cause reduction for localizing constraints. Functional verification of a design under test (DUT) may be performed during a design process for a circuit or system to test whether the DUT functions as intended. In this functional verification, stimuli may be used as inputs to the DUT during a simulation of operation of the DUT so that a user may observe the functionality of the DUT that results from the stimuli. Generally, a comprehensive functional verification may include simulating operation of the DUT using a large number of sets of stimuli, where the sets of stimuli are diverse to cover many possible scenarios of use. A random number generator may be used to generate a set of random values for a set of stimuli; however, typically, a set of stimuli to be input into a DUT during simulation has to meet some constraints. A constraint solver may use the random values to solve a constraint problem and generate a set of stimuli that is input into a DUT during simulation. The constraints may include an error or may, while not an error, lead to a rare or unwanted outcome, which may be due to an improper constraint definition by a user. During simulation of the DUT, a constraint may trigger an error message or some other message that may be of interest to a user. Due to a large amount of data contained within a trace captured during the simulation (e.g., stimulus values for simulation cycles, where the number of stimulus values and/or simulation cycles may each be large), identifying a root cause of the error message or other message can be a time consuming task. Currently, identifying a root cause is a manual process. An experienced test engineer reviewing trace data might require multiple days' worth of time to identify a constraint that caused the error message or other message. The manual process may require many iterations of replaying a simulation of the DUT to vary one or more of the stimulus values to identify a root cause. However, the speed with which technology is evolving is driving the desire to reduce the time that these tests, and any resulting debug or redesign, use.
As described in more detail below, a constraint solver may also be biased by a coverage biaser to generate sets of stimulus values that expose more of the available stimuli space for simulation. This biasing may expose more rare circumstances, which may result in even more error messages or other messages being triggered. This biasing may create more trace data than an experienced engineer would be able to manually review to identify a root cause.
According to some examples described herein, a triggering control binary sequence is determined, which has enabled bits that are a proper subset of enabled bits of an original control binary sequence. During an original simulation, constraint problems are solved by a constraint solver of a constraint random stimulus generator to generate stimulus values for simulating the DUT. The constraint solver obtains random values from a random number generator of the constraint random stimulus generator for solving the constraint problems and is biased while solving the constraint problems by a coverage biaser. The original control binary sequence may have enabled bits and disabled bits. The original control binary sequence has enabled (disabled) bits that correspond to biasing (not biasing) of the constraint solver by the coverage biaser of the respective constraint problems that result in a designated message being triggered during the original simulation. The original control binary sequence is thus determined during original simulation of the DUT, and the original simulation of the DUT triggered a designated message, which may be an error message or some other message of interest.
A reduced control binary sequence is constructed that has enabled bits that correspond to a subset of the enabled bits of the original control binary sequence. The reduced control binary sequence may be iteratively reconstructed until the reduced control binary sequence has a reduced (e.g., minimal) number of enabled bits that are sufficient to trigger the designated message resulting from simulating the DUT using the reduced control binary sequence to selectively enable restoring solving steps of the constraint random stimulus generator for each constraint problem corresponding to an enabled bit of the reduced control binary sequence and disable restoring the solving steps for each constraint problem corresponding to a disabled bit of the reduced control binary sequence. Restoring solving steps of a constraint random stimulus generator for a given constraint problem includes, in some examples, enabling the coverage biaser to bias the constraint solver and restoring a state of the random number generator (e.g., RNG state) for the respective constraint problem, which state was the state of the random number generator at an outset of solving the respective constraint problem in the original simulation. Disabling the solving steps may include disabling the coverage biaser, disabling restoring the state of the random number generator, or both. The triggering control binary sequence may then be set equal to the reduced control binary sequence, which is the reduced (e.g., minimal) number of enabled bits that are sufficient to trigger the designated message resulting from simulating the DUT using the triggering control binary sequence to selectively enable and disable restoring solving steps.
With the original control binary sequence, a first trace of a simulation of the DUT is obtained triggering the designated message, and a second trace of a simulation of the DUT is obtained without the designated message. The first trace may be obtained from the original simulation. The second trace may be obtained by disabling restoring solving steps of the respective constraint problems corresponding to enabled bits in the triggering control binary sequence. Any difference of a stimulus value in the first trace and second trace for a corresponding simulation cycle may indicate which constraint(s) triggered the designated message. Any constraint affecting the stimulus value that is different may be a root cause of the triggering of the designated message.
In some examples, states of the random number generator before solving the respective constraint problems are stored during the original simulation in storage, such as a database. The random number generator may have its state restored to the stored state before solving a respective constraint problem for any simulation being re-run. Restoring this state may permit the generation of the stimulus values to be deterministic between the original simulation and the re-run of the simulation, which may result in equal stimulus values when all other conditions (e.g., including whether the coverage biaser is enabled) are equal. In some examples, the state of the random number generator is restored for each constraint problem being solved by the constraint solver during a re-run of the simulation. In such examples, the reduced (or triggering) control binary sequence may be used to selectively enable or disable biasing of the constraint solver by the coverage biaser. In some examples, restoring the state of the random number generator is enabled based on the reduced (or triggering) control binary sequence for the constraint problems to be solved by the constraint solver during a re-run of the simulation. In such examples, the constraint solver may be biased by the coverage biaser for each constraint problem to be solved in the re-run of the simulation.
In some examples, a simulation result (e.g., including any triggered message) from simulating the DUT (e.g., re-running a simulation of the DUT) based on a reduced control binary sequence is stored in storage, such as a database. The simulation result is stored with the reduced control binary sequence or an indication thereof. If the simulation result is used for any subsequent processing, the simulation result may be retrieved from the storage rather than redundantly re-running a simulation of the DUT based on a same reduced control binary sequence. This may avoid duplicative and redundant processing.
In some examples, a binary search method is implemented to identify the enabled bits of the reduced control binary sequence. In other examples, other search methods, such as a linear search method, a brute force method, etc., may be implemented.
Technical advantages of the present disclosure include, but are not limited to, an efficient, automated computer system that reduces enabled bits of a control binary sequence such that stimulus values, and thereby constraints, that trigger a designated message may be localized. By localizing the stimulus values and constraints, identifying a constraint that caused the designated message to be triggered may be facilitated. A number of simulation runs, each based on a computed reduced binary sequence, required to identify and localize the message triggering constraints may be significantly reduced. Reducing the number of simulation runs may reduce the amount of computing resources required to identify the constraint and may free up computing resources for other tasks or jobs. The present computer system may easily scale to analyze large control binary sequences. The functionality of the present computer system may be extended beyond failures to other behaviors to achieve various debugging insights. Further, engineering time required to identify the constraint may be greatly reduced. Implementing techniques described herein may be relatively easy to use because the techniques may be seamlessly implemented and may require no additional inputs or infrastructure. These and other benefits and advantages may be achieved by various examples described herein.
Similarly, each of the simulator 122, problem generator 124, random number generator 126, constraint solver 128, coverage biaser 130, simulation monitor 132, and constraint debugger 134 may be embodied as instructions stored on a non-transitory computer-readable medium, which instructions are executable by one or more processors of the computer system 102. Each of the simulator 122, problem generator 124, random number generator 126, constraint solver 128, coverage biaser 130, simulation monitor 132, and constraint debugger 134 may be a subset of the instructions (e.g., an instruction module) of the debug tool 112. The simulator 122, problem generator 124, random number generator 126, constraint solver 128, coverage biaser 130, simulation monitor 132, and constraint debugger 134 may be stored on, and executed in, a same computer system 102 (like illustrated in
The simulator 122 simulates operation of a design under test (DUT). The DUT is a circuit design that is being designed and tested with the objective to manufacture the circuit represented by the circuit design. The simulator 122 receives a DUT file 152, which includes an electronic (e.g., digital) representation of the DUT. The DUT file 152 may include a hardware description language (HDL) description, such as Verilog, etc., a register transfer level (RTL) description, a gate-level description, a layout-level description, or the like of the DUT. The simulator 122 simulates operation of the DUT of the DUT file 152 using stimulus values of signals that are output from the constraint solver 128.
The problem generator 124 produces a constraint problem to be solved. The problem generator 124 receives a constraints file 154. The constraints file 154 includes declaratory statements of constraints for various signals for which stimulus values are to be generated for simulation. Any constraint may, for example, restrict an upper bound and/or lower bound of a given signal, require a logical relation between multiple signals, etc. The constraints may be or include dynamic constraints based on a state of the DUT during simulation. The problem generator 124 may also observe a state of the DUT during simulation by the simulator 122. The problem generator 124 may dynamically unfold constraints based on a state of the DUT during simulation. The problem generator 124 translates the constraints into a form readable by the constraint solver 128 and dynamically unfolds constraints, if any such constraints are included in the constraints file 154, to generate a constraint problem. The problem generator 124 outputs the constraint problem to the constraint solver 128.
The random number generator 126 produces random values that may be used as seed values by the constraint solver 128. The random values are output from the random number generator 126 to the constraint solver 128. The constraint solver 128 may query the random number generator 126 to generate and output the random values. The random number generator 126 may appear to be non-deterministic and randomized. However, if a state of the random number generator 126 is known at the time of a query, the generated random values may be deterministic based on that state. As described subsequently, a state of the random number generator 126 at the time of a query may be stored, and when a simulation is to be re-run, the state may be restored to the random number generator 126. Hence, the random numbers generated by the random number generator 126 may be deterministically reproduced during re-run of a simulation when the state has been restored. As described subsequently, restoring the state of the random number generator 126 may be selectively enabled or disabled for a given constraint problem during a re-run of simulation.
The constraint solver 128 receives the constraint problem and random values. Based on the received constraint problem and random values, the constraint solver 128 produces stimulus values of signals that are within the constraints of the constraints file 154. The constraint solver 128 may solve a constraint problem based on commands in a user testbench. The constraint solver 128 may solve one or multiple constraint problems during a simulation cycle or may not solve a constraint problem for a simulation cycle. The constraint solver 128 may be or include a constraint satisfiability solver. The generated stimulus values are applied to respective drivers to simulate operation of the DUT by the simulator 122.
Although illustrated and described as separate components, the problem generator 124, random number generator 126, and constraint solver 128 may together be referred to as a constraint random stimulus generator 136. A constraint random stimulus generator 136 may perform the functionality described above, or similar functionality, of the problem generator 124, random number generator 126, and constraint solver 128. A constraint random stimulus generator may be implemented differently in other examples.
The coverage biaser 130 operates with the constraint solver 128 to bias the process (e.g., a constraint satisfiability solver process) implemented by the constraint solver 128 to coerce one or more values. The coverage biaser 130 may implement a machine learning process to identify coverage within the mathematical space available to the stimulus values and to bias the process implemented by the constraint solver 128 to coerce the values to diversify generated stimulus values. The coverage biaser 130 biasing the constraint solver 128 may result in the constraint solver 128 exposing more of the mathematical space available to the stimulus values, which may result in increased chances to expose errors, rare behaviors, or other conditions of interest during simulation. In some examples, the coverage biaser 130 implementing a machine learning process may be trained based on multiple simulations (e.g., different simulations) such that the coverage biaser 130 may bias the process implemented by the constraint solver 128 when the coverage biaser 130 determines that, e.g., the constraint solver 128 may be converging on a possible repeated set of stimulus values. During original simulation, biasing by the coverage biaser 130 may be enabled for each constraint problem, and during re-run of simulation, the biasing by the coverage biaser 130 may be selectively enabled or disabled.
The simulation monitor 132 observes the state of the random number generator 126, the generated stimulus values output by the constraint solver 128 (e.g., as input to the simulator 122), and the state of the DUT during simulation by the simulator 122. The simulation monitor 132 creates and writes a record of operations of the debug tool 112 to a debug database 142. The record may include a trace of the simulation, states of the random number generator 126 for respective constraint problems, and a control binary sequence that is determined for the constraint problems. The trace may include the stimulus values for respective simulation cycles and any message generated by the simulation monitor 132 based on observing the simulation. The simulation monitor 132 is configured to observe the state of the DUT during simulation and to create a message when the state of the DUT and/or simulation is in some condition of interest. Such messages may be created when a fatal error message (e.g., a UVM_FATAL message), a non-fatal error message (e.g., a UVM_ERROR message or a SystemVerilog Assertion (SVA) failure message), or any rare condition (e.g., line, branch, cover bins, design states, etc.) or condition of interest to a user has occurred. In some examples, the message may be any regular expression defined and designated by a user, such as part of a testbench.
According to some examples, during an original simulation of the DUT, an original control binary sequence is created and stored. An original control binary sequence includes bits that correspond to respective constraint problems. The original control binary sequence includes enabled bits that correspond to respective constraint problems biased by the coverage biaser 130 and from which a designated message was triggered during original simulation. An original control binary sequence is created during original simulation by determining an enabled bit or a disabled bit for each constraint problem solved by the constraint solver 128 during the original simulation and biased by the coverage biaser 130. Whether a given bit of an original control binary sequence is an enabled bit or a disabled bit is determined by whether the coverage biaser 130 biased the constraint solver 128 during solving the corresponding problem. In some examples, a logical “0” in the control binary sequence may indicate a disabled bit for a respective constraint problem that was solved without bias by the coverage biaser 130, and a logical “1” may indicate an enabled bit for a respective constraint problem that was solved with bias by the coverage biaser 130. The simulation monitor 132 and/or constraint debugger 134 may create the original control binary sequence during original simulation and may store the original control binary sequence in storage, such as the debug database 142.
The constraint debugger 134 generally determines a triggering control binary sequence. The triggering control binary sequence has enabled bits that are a subset (e.g., a proper subset) of the enabled bits of the original control binary sequence. The triggering control binary sequence has enabled bits that are a reduced (e.g., minimal) number of enabled bits relative to the original control binary sequence and that are sufficient to trigger a designated message when simulation of the DUT is re-run using the triggering control binary sequence.
Generally, in some examples, the constraint debugger 134 accesses the original control binary sequence determined and stored during the original simulation and iteratively constructs a reduced control binary sequence until the reduced control binary sequence has a reduced (e.g., minimal) number of enabled bits that are sufficient to trigger the designated message resulting from simulating the DUT using the reduced control binary sequence. Then, the triggering control binary sequence may be set equal to the reduced control binary sequence.
In re-run of simulation, a reduced or triggering control binary sequence may be used to selectively enable or disable restoring solving steps of the constraint random stimulus generator 136 for the respective constraint problem that were performed during the original simulation of the DUT. Selectively enabling/disabling restoring solving steps may affect biasing for solving the respective constraint problems. Selectively enabling/disabling restoring solving steps may include selectively enabling/disabling biasing by the coverage biaser 130 the constraint solver 128, restoring a state of the random number generator 126, or both. In some examples, biasing by the coverage biaser 130 is selectively enabled or disabled for a given constraint problem based on whether the corresponding bit of the reduced or triggering control binary sequence is an enabled bit or a disabled bit. In some examples, biasing may be affected by the state of the random number generator 126 when queried for seed values for the constraint problem, and in such examples, whether a state of the random number generator 126 is restored for the given constraint problem is based on whether the corresponding bit of the reduced or triggering control binary sequence is an enabled bit or disabled bit. Other methodologies of determining the triggering control binary sequence may be implemented.
Constraint problems that have corresponding enabled bits in the triggering control binary sequence indicate a reduced portion of a trace that localizes the cause that triggered the designated message during simulation. For example, the constraint debugger 134 may, to obtain a first trace, access the trace from the original simulation and/or cause a re-run of simulation of the DUT by the simulator 122 using the original control binary sequence. Further, the constraint debugger 134 may, to obtain a second trace, cause a re-run of simulation of the DUT by the simulator 122 using a non-triggering control binary sequence. The non-triggering control binary sequence has disabled bits corresponding to enabled bits of the triggering control binary sequence. Using the non-triggering control binary sequence, the constraint solver 128 generates stimulus values without biasing by the coverage biaser 130 and/or without restoring states of the random number generator 126 for constraint problems corresponding to the disabled bits of the non-triggering control binary sequence. The constraint debugger 134 may compare the first trace and second trace and identify which stimulus values in corresponding simulation cycles differ. The stimulus values that differ indicate which constraint(s) may have caused the designated message. Any constraint that affected the identified stimulus values may be the cause and may be identified by the constraint debugger 134. With the identified stimulus values, and thereby constraints, a user may more easily identify a problem with a randomization constraint that resulted in the designated message being triggered.
To re-run the simulation, the constraint debugger 134 accesses the record in the debug database 142. The constraint debugger 134 reads, from the debug database 142, a control binary sequence (e.g., the reduced control binary sequence and/or triggering control binary sequence) that was constructed. Depending on implementation in some examples, the constraint debugger 134 may then cause the coverage biaser 130 to be selectively enabled or disabled for constraint problems and/or enable or disable restoring states of the random number generator 126 for constraint problems.
In examples in which biasing by the coverage biaser 130 is enabled or disabled, when a constraint problem is to be solved by the constraint solver 128, the constraint debugger 134 reads a stored state of the random number generator 126 and causes the random number generator 126 to be restored to the read state. The stored state of the random number generator 126 was stored at the beginning of the respective constraint problem during the original simulation. With the state of the random number generator 126 restored and the coverage biaser 130 implementing the given control binary sequence for enabling/disabling biasing of the constraint solver 128, the constraint solver 128 outputs generated stimulus values (that are generated in operation with the random number generator 126, the problem generator 124, and the coverage biaser 130) to the simulator 122, and the simulator 122 simulates operation of the DUT using the generated stimulus values.
In examples in which restoring states of the random number generator 126 is enabled or disabled, when a constraint problem is to be solved by the constraint solver 128, the constraint debugger 134 determines whether to restore the state of the random number generator for a given constraint problem based on the given control binary sequence. When a corresponding bit of the control binary sequence is an enabled bit, the constraint debugger 134 reads a stored state of the random number generator 126 and causes the random number generator 126 to be restored to the read state. When a corresponding bit of the control binary sequence is a disabled bit, the constraint debugger 134 does not restore the state of the random number generator 126. Based on the random values output by the random number generator 126 (e.g., with or without the state being restored), the constraint solver 128 outputs generated stimulus values (that are generated in operation with the random number generator 126, the problem generator 124, and the coverage biaser 130 biasing the constraint solver 128) to the simulator 122, and the simulator 122 simulates operation of the DUT using the generated stimulus values.
The simulation monitor 132 communicates any message <Msg> to the constraint debugger 134. The constraint debugger 134 may write any reduced control binary sequence that triggers the designated message to the debug database 142. The simulation monitor 132 and/or the constraint debugger 134 may write a simulation result, including any message that was triggered by the re-run of the simulation, to the debug database 142. The simulation result may be written in a manner that corresponds with the given control binary sequence used for the re-run of the simulation. Subsequently, the constraint debugger 134 may read a simulation result written to the debug database 142 based on a given control binary sequence such that re-running a simulation based on the given control binary sequence may be avoided.
Although a control binary sequence including enable bits and disable bits is described herein, a control binary sequence may be any abstraction to track which constraint problems result in the triggering of a designated message. For example, a control binary sequence may be, instead of being actual bits corresponding to a respective constraint problem, a set of indexes or numbers that correspond to or identify respective constraint problems that result in the triggering of the designated message. A control binary sequence may take many forms.
At 302, a control binary sequence that actually triggered a designated message (ta) is read, such as from a database. For ease hereinafter, the control binary sequence that actually triggered a designated message (ta) is referred to as “actual control binary sequence (ta).” At 302, the actual control binary sequence (ta) may be the original control binary sequence that was generated during original simulation, as described above.
At 304, a determination whether an end condition has been reached is made. The end condition may be or include any of a number of conditions and any logical combination of a number of conditions. For example, the end condition may include whether a status flag of the record indicates that the method 300 is complete (e.g., set to “DONE,” like in
At 306, a control binary sequence that may potentially trigger a designated message (tp) is constructed based on the actual control binary sequence (ta). For ease hereinafter, the control binary sequence that may potentially trigger a designated message (tp) is referred to as “potential control binary sequence (tp).” The enabled bits in the potential control binary sequence (tp), in this example, are a subset (e.g., proper subset) of the enabled bits in the actual control binary sequence (ta). All other bits in the potential control binary sequence (tp) are disabled bits. The potential control binary sequence (tp) is a reduced control binary sequence. The method 300 may implement any of a number of methods at 306 to determine which bits of the potential control binary sequence (tp) to enable and which bits of the potential control binary sequence (tp) to disable in constructing the potential control binary sequence (tp). Such methods include a binary search method, a linear search method, and a brute force (e.g., all possible combinations) method. An example binary search method is described in detail subsequently.
At 308, a simulation result based on the potential control binary sequence (tp) is obtained. In some examples, a simulation based on the potential control binary sequence (tp) may have previously occurred in a prior iteration. In such circumstances, the simulation result may be stored (e.g., cached), such as in a database (e.g., the debug database 142). If the simulation result is stored, the simulation result is read at 308. This may obviate duplication of a previous simulation, which may reduce processing time and reduce resource usage. If the simulation result was not stored (e.g., such as when the method 300 does not store such results or if a simulation based on the potential control binary sequence (tp) has not previously occurred), the simulation result may be obtained by performing a re-run of the simulation of the DUT using the potential control binary sequence (tp) to selectively, for each constraint problem, restore solving steps of the constraint random stimulus generator 136 for the respective constraint problem that were performed during the original simulation of the DUT. Selectively restoring the solving steps may including enabling/disabling the coverage biaser 130 and/or enabling/disabling restoring states of the random number generator 126. As noted previously, when the potential control binary sequence (tp) enables/disables the coverage biaser 130, the states of the random number generator 126 from the original simulation is read, such as from the debug database 142, and the random number generator 126 is restored to the read state for subsequent simulation during 308. When the potential control binary sequence (tp) enables/disables restoring states of the random number generator 126, the coverage biaser 130 is enabled during the simulation. The simulation monitor 132 may create a record, as described previously, and may monitor what, if any, message is triggered during the simulation. Any message observed by the simulation monitor 132 is communicated from the simulation monitor 132 to the constraint debugger 134.
At 310, a determination is made whether a designated message was in the obtained simulation result. The designated message may be designated, for example, in a user testbench, hardcoded in the constraint debugger 134, or by another mechanism. If the determination is that the designated message is not included in the obtained simulation result, the method 300 loops back to 304. If the determination is that the designated message is included in the obtained simulation result, at 312, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). After setting the actual control binary sequence (ta) equal to the potential control binary sequence (tp), the actual control binary sequence (ta) may be written, such as to the debug database 142. The method 300 then loops back to 304.
If the determination that an end condition has been reached at 304, at 314, the actual control binary sequence (ta) is written (e.g., if not written previously). At 314, the actual control binary sequence (ta) is the triggering control binary sequence. Of note, the determination at 304 is shown located in the flow of the loop as an example. Such a determination may be located elsewhere in the logical flow of the loop, such as depending upon the end condition.
On subsequent iterations, at 306, the potential control binary sequence (tp) is attempted to be constructed to be a subset of enabled bits of the actual control binary sequence (ta) that is a different subset of enabled bits of the potential control binary sequence (tp) of the immediately preceding iteration. As noted above, a later iteration may construct a potential control binary sequence (tp) that is the same as a potential control binary sequence (tp) constructed in some previous iteration. In some examples, if a potential control binary sequence (tp) is not able to be constructed at 306, a status flag may be set to indicate that the method 300 should be completed, which may cause the method 300 to be completed as an end condition in 304.
In some examples, conditions and results of each re-run of the simulation that occurs at 308 (e.g., for the iterations of the method 300) may be made available to a user on a video display unit (e.g., via a graphical user interface (GUI)) by the constraint debugger 134. A selectable line item for each re-run of the simulation may be displayed by a GUI generated by the constraint debugger 134. Selecting a line item by a user (e.g., by a cursor control device, such as a mouse) may display, by the GUI, trace information of the respective re-run of the simulation, the potential control binary sequence (tp) used in the respective re-run, and/or the states of the random number generator 126. Hence, in such examples, a re-run of a simulation at 308 includes storing, such as in the debug database 142, a trace, the potential control binary sequence (tp), and states of the random number generator 126. The user may be permitted to modify any stimulus value of the trace, the potential control binary sequence (tp), and/or a state of the random number generator 126 and re-run the simulation of the DUT using the modified data.
The method 400 may rely on a monotone property to identify a reduced (e.g., minimal) subset of enabled bits for a triggering control binary sequence. For a monotone property, it is assumed that if a proper subset of enabled bits of a control binary sequence Y causes the designated message to be triggered, then a superset of enabled bits of a control binary sequence X also causes the designated message to be triggered, where Y⊂X. Conversely, if the superset of enabled bits of the control binary sequence X does not cause the designated message to be triggered, then the proper subset of enabled bits of the control binary sequence Y also does not cause the designated message to be triggered. The monotone property may result in an observation that adding enabled bits in a control binary sequence does not prevent triggering of a designated message and that some enabled bits in a control binary sequence may not be necessary to trigger a designated message. Hence, enabled bits that are not required to trigger a designated message may be disabled such that the designated message is triggered by remaining enabled bits. If a scenario occurs in which this monotone property does not hold true, a reduced control binary sequence may still be determined; however, that reduced control binary sequence may not have a minimal set of enabled bits.
Generally, the method 400 identifies indexes of enabled bits of an original control binary sequence that are sufficient to trigger a designated message from simulation of a DUT using the enabled bits identified by the indexes. The method 400 conceptually searches within iterative ranges. Within a searched range, a respective lowest upper index and a respective highest lower index are determined. The lowest upper index(es) and the highest lower index(es) indicate the enabled bits of the original control binary sequence within the searched range that are sufficient to trigger the designated message from simulation of the DUT. Iteratively, a successive range within the previous iteration lowest upper index and highest lower index is searched until no other range is available to be searched. Of note, a lowest upper index of a range may be equal to a highest lower index of the range. The lowest upper index(es) and highest lower index(es) are collected in a set.
As illustrated, the method 400 initiates a range spanning the indexes of an original control binary sequence (e.g., indicated by a lower index (j) initiated to zero and an upper index (k) initiated to N−1) and initiates an index set (psi) as empty. The method 400 searches for a lowest upper index within the range and searches for a highest lower index in the range. The lowest upper index and the highest lower index that are identified satisfy three conditions:
The iteration of the method 400 continues until the designated message is triggered by a simulation of the DUT using a reduced control binary sequence, where the reduced control binary sequence has enabled bits corresponding to enabled bits of the original control binary sequence at a respective index in the index set. This condition may occur when no other range is available to be searched (e.g., when a highest lower index and a lowest upper index collected in the index set in an iteration are within one) or when a range to be searched in an iteration does not include any enabled bits that trigger the designated message. The method 400 illustrates how this condition may be implemented. When this condition is reached, a status flag in the record may be set to “DONE”, which may trigger completion of iterations of the method 400, although not illustrated. When the iteration(s) are complete, the reduced control binary sequence is the triggering control binary sequence. An additional condition for completion may be included, such as when a threshold for run time or resources used is met or exceeded.
Referring to
At 404, lower index variable (j) is set equal to zero; upper index variable (k) is set equal to N−1; and an index variable set (psi) is defined as empty. The variables j, k, and psi are defined and initialized at lines 503, 504, 505, respectively, of
At 406, a determination is made whether psi is not empty. If psi is empty, the method 400 proceeds to 432 in
The conditional statement at 406 is implemented at line 508 in
Generally, referring to
In reaching 414 and line 511, the method 400 determines that a range of the original control binary sequence to be searched in an iteration does not include any enabled bits that trigger the designated message. If psi includes any index (e.g., is not empty), a determination is made whether a range of the actual control binary sequence (ta) from j to k includes any index of an enabled bit that causes a designated message to be triggered. The potential control binary sequence (tp) is constructed based on psi without regard to j and k, and a simulation result is obtained based on this potential control binary sequence (tp). Hence, if the designated message is obtained or returned, the potential control binary sequence (tp) has enabled bits at the indexes contained in psi that are sufficient to trigger a designated message, and no bits in an range from j to k are required to trigger the designated message. Hence, the method 400 has identified the enabled bits to be in the triggering control binary sequence (e.g., by the index(es) collected in psi) and is to be completed.
Referring to
Continuing with
The definition of the function call rerunSim( ) uses the potential control binary sequence (tp) to selectively enable and disable biasing of the constraint solver 128 by the coverage biaser 130. In such examples, the state of the random number generator 126 is restored, for solving each constraint problem that is to be solved by the constraint solver 128, to the respective state that the random number generator 126 was in when the respective constrain problem was solved during original simulation. In other examples, the definition of the function call rerunSim( ) may enable biasing of the constraint solver 128 by the coverage biaser 130 for each constraint problem to be solved for the simulation. In such examples, the function call rerunSim( ) may use the potential control binary sequence (tp) to selectively enable and disable restoring a state of the random number generator 126 for solving a respective constraint problem.
Referring back to
At 418, psi collects j and k within psi. Psi is the union of psi, j, and k. This union is at line 515 of
When j is equal to neither k nor k−1, at 422, j is incremented by one, and k is decremented by one. Operation then loops back to 406. Incrementing j and decrementing k is at lines 517 and 518 of
Turning to
At 438, a potential control binary sequence (tp) is constructed based on the actual control binary sequence (ta), on psi, and on a range from j to next_check. At 440, a simulation result is obtained based on the potential control binary sequence (tp) that was constructed at 438. At 442, a determination is made whether a designated message was included in the simulation result obtained at 440. If a designated message was included, at 444, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). Then, at 446, upper_check is set equal to next_check−1, and last_check is set equal to next_check. If a designated message was not included as determined at 442, at 448, lower_check is set equal to next_check+1. Following 446 and 448, operation loops back to 434. If the determination is made at 434 that lower_check is greater than upper_check, at 450 k is set equal to last_check, and operation proceeds to 462 in
The operations of
Referring to
At line 564, next_check is set to implement 436 of
Then, at line 566, the function call rerunSim( ) causes a simulation result based on the potential control binary sequence (tp) to be returned, which implements 440 of
Generally, the binary search method illustrated by
Turning to
At 468, a potential control binary sequence (tp) is constructed based on the actual control binary sequence (ta), on psi, and on a range from next_check to k. At 470, a simulation result are obtained based on the potential control binary sequence (tp) that was constructed at 468. At 472, a determination is made whether a designated message was included in the simulation result obtained at 470. If the designated message was included, at 474, the actual control binary sequence (ta) is set equal to the potential control binary sequence (tp). Then, at 476, lower_check is set equal to next_check+1, and last_check is set equal to next_check. If the designated message was not included as determined at 472, at 478, upper_check is set equal to next_check−1. Following 476 and 478, operation loops back to 464. If the determination is made at 464 that lower_check is greater than upper_check, at 470 j is set equal to last_check, and operation proceeds to 418 in
The operations of
Referring to
At line 576, next_check is set to implement 466 of
Then, at line 578, the function call rerunSim( ) causes a simulation result based on the potential control binary sequence (tp) to be returned, which implements 470 of
Generally, the binary search method illustrated by
To illustrate the functionality of
By operation of lines 503 through 505, initially, j is equal to 0; k is equal to 9; and psi is empty. Execution enters the while loop at line 507 and branches to line 513 because psi is empty. Table 1 below shows values of various variables when line 513 is executed in the first iteration of the while loop.
Entry 1 of Table 1 shows the values of j, k, and psi prior to execution of line 513. Entry 2 of Table 1 shows the status of variables when the function call bsrUpper( ) is first called. In the first call, next_check is 4 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 0 to 4. Since the potential control binary sequence (tp) does not include the bits of the actual control binary sequence (ta) at indexes 5 and 6, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the lower half of the range (0:4) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 570) with the lower_check being 5, as shown in entry 3 of Table 1.
In the second call, next_check is 7 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 0 to 7. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the upper half of the range (8:9) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 568) with the upper_check being 6 and last_check being 7, as shown in entry 4 of Table 1.
In the third call, next_check is 5 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 0 to 5. Since the potential control binary sequence (tp) does not include the bits of the actual control binary sequence (ta) at indexes 5 and 6, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the lower half of the range (5:5) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 570) with the lower_check being 6, as shown in entry 5 of Table 1.
In the fourth call, next_check is 6 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 0 to 6. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the range (7:7) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 568) with the upper_check being 5 and last_check being 6, as shown in entry 6 of Table 1.
In the fifth call, lower_check is greater than upper_check, which causes last_check to be returned. Last_check in the fifth call is 6, which causes k to be set equal to 6 at entry 6 of Table 1.
Table 2 below shows values of various variables when line 514 is executed in the first iteration of the while loop.
Entry 1 of Table 2 shows the values of j, k, and psi prior to execution of line 514. Entry 2 of Table 2 shows the status of variables when the function call bsrLower( ) is first called. In the first call, next_check is 3 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 3 to 6. Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 0, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, the upper half of the range (3:6) can be excluded from further searching for the highest lower index, and bsrLower( ) is recursively called (at line 582) with the upper_check being 2, as shown in entry 3 of Table 2.
In the second call, next_check is 1 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 1 to 6. Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 0, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, the upper half of the range (1:2) can be excluded from further searching for the highest lower index, and bsrLower( ) is recursively called (at line 582) with the upper_check being 0, as shown in entry 4 of Table 2.
In the third call, next_check is 0 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 0 to 6. Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, bsrLower( ) is recursively called (at line 580) with the lower_check being 1 and last_check being 0, as shown in entry 5 of Table 2.
In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. Last_check in the fourth call is 0, which causes j to be set equal to 0 at entry 5 of Table 2.
Then, in the first iteration of the while loop, psi collects j and k, such that psi is {0, 6} (at line 515). The if statement at line 516 does not cause a break from the while loop. Then, k is decremented to 5 (at line 517); j is incremented to 1 (at line 518); and a second iteration of the while loop begins.
In the second iteration, psi is not empty, so lines 509 and 510 are executed. The potential control binary sequence (tp) that is constructed (at line 509) includes the bits of the actual control binary sequence (ta) at indexes 0 and 6, since psi equals {0, 6}. Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 5, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 510). Hence, execution of lines 511 and 512 is omitted, and a break (at line 512) from the while loop is not executed.
Table 3 below shows values of various variables when line 513 is executed in the second iteration of the while loop.
Entry 1 of Table 3 shows the values of j, k, and psi prior to execution of line 513. Entry 2 of Table 3 shows the status of variables when the function call bsrUpper( ) is first called. In the first call, next_check is 3 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 1 to 3 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 5, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the lower half of the range (1:3) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 570) with the lower_check being 4, as shown in entry 3 of Table 3.
In the second call, next_check is 4 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 1 to 4 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) does not include the bit of the actual control binary sequence (ta) at index 5, no designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). Accordingly, the lower half of the range (4:4) can be excluded from further searching for the lowest upper index, and bsrUpper( ) is recursively called (at line 570) with the lower_check being 5, as shown in entry 4 of Table 3.
In the third call, next_check is 5 (calculated at line 564) such that the range with which the potential control binary sequence (tp) is constructed (at line 565) is 1 to 5 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 566). bsrUpper( ) is recursively called (at line 568) with the upper_check being 4 and last_check being 5, as shown in entry 5 of Table 3.
In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. Last_check in the fourth call is 5, which causes k to be set equal to 5 at entry 5 of Table 3.
Table 4 below shows values of various variables when line 514 is executed in the second iteration of the while loop.
Entry 1 of Table 4 shows the values of j, k, and psi prior to execution of line 514. Entry 2 of Table 4 shows the status of variables when the function call bsrLower( ) is first called. In the first call, next_check is 3 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 3 to 5 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, the lower half of the range (1:2) can be excluded from further searching for the highest lower index, and bsrLower( ) is recursively called (at line 580) with the lower_check being 4 and last_check being 3, as shown in entry 3 of Table 4.
In the second call, next_check is 4 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 4 to 5 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, the range (3:3) can be excluded from further searching for the highest lower index, and bsrLower( ) is recursively called (at line 580) with the lower_check being 5 and last_check being 4, as shown in entry 4 of Table 4.
In the third call, next_check is 5 (calculated at line 576) such that the range with which the potential control binary sequence (tp) is constructed (at line 577) is 5 to 5 (with indexes contained in psi {0, 6}). Since the potential control binary sequence (tp) includes the bits of the actual control binary sequence (ta) at indexes 0, 5, and 6, a designated message is triggered when simulation based on the potential control binary sequence (tp) is executed (at line 578). Accordingly, the range (4:4) can be excluded from further searching for the highest lower index, and bsrLower( ) is recursively called (at line 580) with the lower_check being 5 and last_check being 4, as shown in entry 5 of Table 4.
In the fourth call, lower_check is greater than upper_check, which causes last_check to be returned. Last_check in the fourth call is 5, which causes j to be set equal to 5 at entry 5 of Table 4.
Then, in the second iteration of the while loop, psi collects j and k, such that psi is {0, 5, 6} (at line 515). The if statement at line 516 cause a break from the while loop since j is equal to k. The actual control binary sequence (ta) is then written at line 520.
To further illustrate the functionality of
Various modifications may be made to the method 400 and pseudocode. For example, a linear search, a brute force search, or another search method may be implemented instead of the binary search described above. For example, a linear search may explore all indexes to a present lower index as a lowest upper index and explore all indexes to a present upper index as a highest lower index. A brute force search may construct all 2N permutations of an N number of bits control binary sequence and search those permutations. Further, a binary search may be implemented different from what is described above. For example, a highest lower index may be identified before a lowest upper index is identified.
The binary search method described above may be executed with a run time on the order of Nlog(N) or less (e.g., O(Nlog(N))). The execution of the function calls bsrUpper( ) and bsrLower( ) at lines 513 and 514 in
At 604, a second trace is obtained from a simulation of the DUT using a non-triggering control binary sequence based on the triggering control binary sequence and not triggering the designated message. The non-triggering control binary sequence is determined based on the triggering control binary sequence. The triggering control binary sequence may be determined by the method 400 of
At 606, one or more stimulus values that differ for respective simulation cycles between the first trace and the second trace are identified. A trace may include values for many stimuli for a given simulation cycle. When respective values of a same stimulus in a same simulation cycle of the first trace and the second trace differ, the stimulus may indicate that a constraint affecting that stimulus is a cause of the designated message generated by the simulation of the DUT. The number of stimuli identified as a result of the method 600 may be reduced, which may facilitate faster debugging of constraints.
Two use cases illustrate the effectiveness of implementing a constraint debugger 134 as described above. A first use case included 110 random problem instances in a failing trace. The methods 400, 600 described above were implemented to identify a triggering control binary sequence that indicates a reduced portion of a trace and to identify one or more constraints that may trigger a designated message. As a benchmark, an upper bound of the run time for identifying a triggering control binary sequence according to the binary search method of
In this use case, the number of enabled bits in the triggering control binary sequence was reduced from 110 (e.g., corresponding to the number of random problems) to 1 by implementing the binary search method of
A second use case included 331 random problem instances in a failing trace. The methods 400, 600 described above were implemented to identify a triggering control binary sequence that indicates a reduced portion of a trace and to identify one or more constraints that may trigger a designated message. As a benchmark, an upper bound of the run time for identifying a triggering control binary sequence according to the binary search method of
In this use case, the number of enabled bits in the actual control binary sequence (ta) was reduced from 331 (e.g., corresponding to the number of random problems) to 1 by implementing the binary search method of
Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. A high-level of representation may be used to design circuits and systems, using a hardware description language (HDL) such as VHDL, Verilog, System Verilog, SystemC, MyHDL or Open Vera. The HDL description can be transformed to a logic-level register transfer level (RTL) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level that is a more detailed description adds more useful detail into the design description, for example, more details for the modules that include the description. The lower levels of representation that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of representation are enabled for use by the corresponding systems of that layer (e.g., a formal verification system). A design process may use a sequence depicted in
During system design 714, functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or lines of code), and reduction of costs, etc. Partitioning of the design into different types of modules or components can occur at this stage.
During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification. Functional verification may include any of the methods 300, 400, 600 described above.
During synthesis and design for test 718, HDL code is transformed to a netlist. In some embodiments, a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.
During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.
During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the circuit components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions can be performed. As used herein, the term ‘cell’ may specify a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop or latch). As used herein, a circuit ‘block’ may refer to two or more cells. Both a cell and a circuit block can be referred to as a module or component and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products.
During analysis and extraction 726, the circuit function is verified at the layout level, which permits refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.
During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for production of lithography masks. During mask data preparation 732, the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits.
A storage subsystem of a computer system (such as computer system 800 of
The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.
Processing device 802 represents one or more processors such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 802 may be configured to execute instructions 826 for performing the operations and steps described herein.
The computer system 800 may further include a network interface device 808 to communicate over the network 820. The computer system 800 also may include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), graphics processing unit 822, video processing unit 828, and audio processing unit 832.
The data storage device 818 may include a machine-readable storage medium 824 (also known as a non-transitory computer-readable storage medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and/or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media.
In some implementations, the instructions 826 include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium 824 is shown in an example implementation to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 802 to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.
The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMS, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.
The present disclosure may be provided as a computer program product, or software, that may include a machine-readable storage medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable storage medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., a computer-readable) storage medium includes a machine-readable (e.g., a computer-readable) storage medium such as a read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.
In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.