Claims
- 1. In a circuit of the type including means connected to a circuit node for applying a data signal to said circuit node, means connected to said circuit node for sensing said data signal and, a transparent latch circuit responsive to a logical control signal for holding said data signal at said circuit node, said transparent latch circuit comprising:
- latch means connected to said circuit node in a T-connection with said data applying means and said sensing means for selectively holding said data signal at said circuit node; and
- actuating means connected to said latch means for delivering said logical control signal to said latch means and actuating said latch means to pass through said data signal or hold said data signal at said circuit node regardless of the state of said data applying means.
- 2. A transparent latch circuit responsive to a logical control signal for holding a data signal applied by an input circuit at a circuit node, comprising:
- a first transistor for providing current from a first terminal to a second terminal in accordance with a signal applied at a control terminal thereof, said first transistor having a first terminal connected to said circuit node and a second terminal coupled to a reference potential;
- means for applying said control signal to the control terminal of said first transistor;
- a second transistor having a first terminal connected to the control terminal of said first transistor and a second terminal connected to said reference potential;
- a resistor connected intermediate said circuit node and a control terminal of said second transistor; and
- means responsive to said logical control signal for generating a second control signal operative to isolate said circuit node from said input circuit when said latch is activated to hold said data signal at said circuit node.
- 3. A transparent latch circuit in accordance with claim 2 wherein said generating means comprises:
- a third transistor;
- means for applying said control signal to a control terminal of said third transistor; and
- a second terminal of said third transistor coupled to a second reference potential;
- said second control signal generated at a first terminal of said third transistor.
- 4. A transparent latch circuit in accordance with claim 3 wherein said input circuit is implemented with NPN bipolar transistors and includes an open collector device connected at said circuit node in common with a pull-up resistor, and said second control signal functions to control said open collector device.
- 5. A transparent latch circuit in accordance with claim 3 and further including a Schottky diode having an anode connected to the base of said third transistor and a cathode connected to the collector of said third transistor.
Parent Case Info
This application is a division of U.S. Ser. No. 07/198,961, filed May 26, 1988, now allowed.
US Referenced Citations (23)
Foreign Referenced Citations (2)
Number |
Date |
Country |
01544330 |
May 1985 |
EPX |
89480053 |
Oct 1991 |
EPX |
Non-Patent Literature Citations (1)
Entry |
Microelectronics: Digital & Analog Circuits and Systems 1979, p. 109, International Student Edition, McGraw-Hill, Inc., Singapore. |
Divisions (1)
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Number |
Date |
Country |
Parent |
198961 |
May 1988 |
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