Patent Application
20090154210
The present invention relates to bidirectional field-effect transistors, which can control a current flowing bi-directionally, and a matrix converter using the transistors.
a is a circuit diagram showing an example of a conventional matrix converter.
A three-phase AC power source PS supplies a three-phase AC power having a frequency Fa through three lines R, S and T. A three-phase AC motor M is driven by another three-phase AC power having another frequency Fb, which is supplied through three lines U, V and W.
The matrix converter CV includes the input lines R, S and T, the output lines U, V and W, and nine switching devices SW, which are arranged in matrix between the respective lines R, S and T and the respective lines U, V and W, for controlling opening and closing between the mutual lines. Each of the switching devices SW is driven by a control circuit (not shown) which can operate PWM (pulse width modulation) with desired timings.
Since each of the switching devices SW must open and close the AC current flowing forward and backward, a common power transistor cannot perform this operation. Hence, certain ingenuity of circuit arrangement is required.
In the conventional matrix converter, as shown in
In the above-described circuitry, however, four power device are needed to constitute the single switching device SW. In the case of three-phase to three-phase conversion shown in
In order to solve these problems, RB (Reverse Blocking)-IGBT devices, as shown in
The RB-IGBT device, which is integrated with a diode area on a side of a semiconductor substrate on which an IGBT device is formed, is equivalent in circuitry to the series circuit having the IGBT device and the diode device shown in
Even in the case of using RB-IGBT devices, however, two RB-IGBT devices must be connected in anti-parallel with each other to control the bidirectional current. Hence, two power devices are needed to constitute the single switching device SW, resulting in larger scale of circuitry and a larger cooling mechanism.
It is an object of the present invention to provide a bidirectional field-effect transistor, which can control a current flowing bi-directionally by means of a single device.
Further, it is another object of the present invention to provide a matrix converter with a smaller size and a larger capacity by using the bidirectional field-effect transistors.
In order to achieve the object, a bidirectional field-effect transistor according to the present invention, includes:
a semiconductor substrate;
a gate region which is formed on the semiconductor substrate, the region including a channel parallel to a principal surface of the substrate, and a gate electrode for controlling conductance of the channel;
a first region which is provided on a first side of the channel; and
a second region which is provided on a second side of the channel;
wherein both of a first current flowing from the first region through the channel to the second region and a second current flowing from the second region through the channel to the first region are controlled by a gate voltage applied to the gate electrode.
It is preferable in the present invention that the gate region is arranged in the center of the first region and the second region.
Further, it is preferable in the present invention that an interval between the gate electrode and a first electrode residing in the first region is substantially equal to another interval between the gate electrode and a second electrode residing in the second region.
Furthermore, it is preferable in the present invention that an interval between the channel of the gate region and a first contact layer residing in the first region is substantially equal to another interval between the channel of the gate region and a second contact layer residing in the second region.
Moreover, it is preferable in the present invention that the transistor is of junction type wherein the gate region includes a p-n junction.
Moreover, it is preferable in the present invention that the transistor is of MIS (Metal-Insulator-Semiconductor) type wherein the gate region includes a metal layer, an insulation layer and a semiconductor layer.
Moreover, it is preferable in the present invention that the transistor is of MES (Metal-Semiconductor) type wherein the gate region includes a Schottky junction of a metal and a semiconductor.
Further, it is preferable in the present invention that the semiconductor substrate is formed of SiC.
A matrix converter according to the present invention, includes:
a plurality of input lines in which alternating currents having a first frequency flow;
a plurality of output lines in which alternating currents having a second frequency flow;
a plurality of switching devices for controlling opening and closing between the respective input lines and the respective output lines;
wherein for the switching devices, the above-described bidirectional field-effect transistors are used.
According to the present invention, on the semiconductor substrate, the gate region including the channel parallel to the principal surface of the substrate is provided, and the first and the second regions are provided on the first and the second sides of the channel, respectively, thereby realizing a bidirectional field-effect transistor which can operate both in a forward mode where the first region acts as a source and the second region acts as a drain, and in a backward mode where the second region acts as a source and the first region acts as a drain. Both the forward current and the backward current can be controlled by the gate voltage applied to the gate electrode. Therefore, an alternating current flowing bi-directionally can be controlled by means of only a single device, and such an AC switching device having a smaller size and a larger capacity can be obtained.
Additionally, in the matrix converter which employs the bidirectional field-effect transistors for the switching devices, the number of such power devices can be remarkably reduced, thereby downsizing scale of circuitry and cooling mechanism and simplifying them as compared to the conventional converter.
a is a circuit diagram showing an example of a matrix converter according to the present invention.
a is a circuit diagram showing an example of a conventional matrix converter.
a is a circuit diagram showing an example of a matrix converter according to the present invention.
A three-phase AC power source PS supplies a three-phase AC power having a frequency Fa through three lines R, S and T. A three-phase AC motor M is driven by another three-phase AC power having another frequency Fb, which is supplied through three lines U, V and W.
The matrix converter CV includes the input lines R, S and T, the output lines U, V and W, and nine switching devices SW, which are arranged in matrix between the respective lines R, S and T and the respective lines U, V and W, for controlling opening and closing between the mutual lines. Each of the switching devices SW is driven by a control circuit (not shown) which can operate PWM (pulse width modulation) with desired timings.
In this embodiment, bidirectional field-effect transistors QA as shown in
On a substrate 1 formed is a buffer layer 2, on which a channel layer 3 is formed. In the channel layer 3, there are a gate region including a channel parallel to the principal surface of the substrate 1, a first region which is provided on a first side of the channel (left side of the drawing), and a second region which is provided on a second side of the channel (right side of the drawing).
In the gate region, provided is a gate electrode 13a for controlling conductance of the channel. In the first region, provided is a first electrode 11a which can act as either source electrode or drain electrode. In the second region, provided is a second electrode 12a which can act as either drain electrode or source electrode in contrast to the first electrode 11a. Both between the gate region and the first region and between the gate region and the second region, formed are drift regions through which majority carriers can pass.
The substrate 1 can be formed of a wafer of semiconductor, such as Si, SiC, GaN, herein, which is formed of an n+ layer having a relatively higher carrier concentration. On the back side of the substrate 1, formed is a common electrode 10a which is typically grounded.
In particular, the substrate 1 and the respective layers 2 and 3 are preferably formed of semiconductor material of SiC, which has excellent physical properties of approximately three times larger energy gap, approximately ten times higher electric breakdown field, approximately twice higher saturation electron velocity, and approximately three times larger thermal conductivity than Si, thereby resulting in a power FET device with a small size and large capacity.
The buffer layer 2 is epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of a p− layer having a relatively lower carrier concentration.
The channel layer 3 is also epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of an n layer having a normal carrier concentration.
In the gate region of the channel layer 3, formed is a p+ layer 13 having a relatively higher carrier concentration by diffusion or ion implantation of a p-type dopant. On the p+ layer 13, the gate electrode 13a is formed. In the first region of the channel layer 3, formed is an n+ contact layer 11 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 11, the first electrode 11a is formed. In the second region of the channel layer 3, formed is an n+ contact layer 12 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 12, the second electrode 12a is formed.
Next, operation of this device will be described below.
When a positive voltage +V is applied to the first electrode 11a and a negative voltage −V is applied to the second electrode 12a with a reference voltage (=0 volt) of the common electrode 10a, a forward current flows through the path from the first electrode 11a via the n+ contact layer 11, the left drift region, the channel within the gate region, the right drift region and the n+ contact layer 12 to the second electrode 12a. In this state, a negative gate voltage is applied to the gate electrode 13a, so that a depletion layer emerges around the p—n junction of the p+ layer 13 and the n-type channel layer 3 to reduce conductance of the channel within the gate region, thereby increasing resistance of the path and suppressing the forward current.
Meanwhile, when a negative voltage −V is applied to the first electrode 11a and a positive voltage +V is applied to the second electrode 12a, a backward current flows through the path from the second electrode 12a via the n+ contact layer 12, the right drift region, the channel within the gate region, the left drift region and the n+ contact layer 11 to the first electrode 11a. In this state, a negative gate voltage is applied to the gate electrode 13a, so that a depletion layer emerges around the p-n junction of the p+ layer 13 and the n-type channel layer 3 to reduce conductance of the channel within the gate region, thereby increasing resistance of the path and suppressing the backward current.
Thus, the first and second electrodes 11a and 12a can alternately act as source electrode or drain electrode, and an AC current flowing bi-directionally can be controlled by changing the gate voltage.
In a case of controlling an AC power as in the above-mentioned matrix converter, it is preferable that forward characteristics and backward characteristics of the bidirectional field-effect transistor (for example, drain current vs. drain-source voltage, drain current vs. gate-source voltage, on-resistance, gate-source capacitance, reverse voltage, etc) are substantially equal to each other.
For an approach, the gate region including the gate electrode 13a is preferably arranged in the center of the first region including the first electrode 11a and the second region including the second electrode 12a. Thus, the length L1 of the left drift region is equal to the length L2 of the right drift region, thereby substantially equalizing forward and backward characteristics with each other.
For another approach an interval between the gate electrode 13a and the first electrode 11a is preferably substantially equal to another interval between the gate electrode 13a and the second electrode 12a, thereby substantially equalizing forward and backward characteristics with each other.
For yet another approach, an interval between the channel of the gate region and the n+ contact layer 11 is preferably substantially equal to another interval between the channel of the gate region and the n+ second contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, the carrier concentration of the n+ contact layer 11 is preferably substantially equal to the carrier concentration of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, a depth of the n+ contact layer 11 is preferably substantially equal to a depth of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
On a substrate 1 formed is a buffer layer 2, on which a channel layer 3 is formed. A RESURF layer 4 is formed on the channel layer 3. In the channel layer 3 and the RESURF layer 4, there are a gate region including a channel parallel to the principal surface of the substrate 1, a first region which is provided on a first side of the channel (left side of the drawing), and a second region which is provided on a second side of the channel (right side of the drawing).
In the gate region, provided is a gate electrode 13a for controlling conductance of the channel. In the first region, provided is a first electrode 11a which can act as either source electrode or drain electrode. In the second region, provided is a second electrode 12a which can act as either drain electrode or source electrode in contrast to the first electrode 11a. Both between the gate region and the first region and between the gate region and the second region, formed are drift regions through which majority carriers can pass.
The substrate 1 can be formed of a wafer of semiconductor, such as Si, SiC, GaN, herein, which is formed of an n+ layer having a relatively higher carrier concentration. On the back side of the substrate 1, formed is a common electrode 10a which is typically grounded.
In particular, the substrate 1 and the respective layers 2 and 3 are preferably formed of semiconductor material of SiC, which has excellent physical properties of approximately three times larger energy gap, approximately ten times higher electric breakdown field, approximately twice higher saturation electron velocity, and approximately three times larger thermal conductivity than Si, thereby resulting in a power FET device with a small size and large capacity.
The buffer layer 2 is epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of a p− layer having a relatively lower carrier concentration.
The channel layer 3 and the RESURF layer 4 are also epitaxially grown using chemical vapor deposition (CVD) or the like. Herein, the channel layer 3 is formed of an n layer having a normal carrier concentration.
The RESURF layer 4 is formed of a p layer having a normal carrier concentration by diffusion or ion implantation of a p-type dopant. Hence, the drift regions may also contain p-n junctions to relax concentration of electric fields near the surface, thereby improving reverse voltage property.
In the gate region, formed is a p+ layer 13 having a relatively higher carrier concentration by diffusion or ion implantation of a p-type dopant. On the p+ layer 13, the gate electrode 13a is formed. In the first region, formed is an n+ contact layer 11 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 11, the first electrode 11a is formed. In the second region, formed is an n+ contact layer 12 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 12, the second electrode 12a is formed.
Next, operation of this device will be described below. When a positive voltage +V is applied to the first electrode 11a and a negative voltage −V is applied to the second electrode 12a with a reference voltage (=0 volt) of the common electrode 10a, a forward current flows through the path from the first electrode 11a via the n+ contact layer 11, the left drift region, the channel within the gate region, the right drift region and the n+ contact layer 12 to the second electrode 12a. In this state, a negative gate voltage is applied to the gate electrode 13a, so that a depletion layer emerges around the p-n junction of the p+ layer 13 and the n-type channel layer 3 to reduce conductance of the channel within the gate region, thereby increasing resistance of the path and suppressing the forward current.
Meanwhile, when a negative voltage −V is applied to the first electrode 11a and a positive voltage +V is applied to the second electrode 12a, a backward current flows through the path from the second electrode 12a via the n+ contact layer 12, the right drift region, the channel within the gate region, the left drift region and the n+ contact layer 11 to the first electrode 11a. In this state, a negative gate voltage is applied to the gate electrode 13a, so that a depletion layer emerges around the p-n junction of the p+ layer 13 and the n-type channel layer 3 to reduce conductance of the channel within the gate region, thereby increasing resistance of the path and suppressing the backward current.
Thus, the first and second electrodes 11a and 12a can alternately act as source electrode or drain electrode, and an AC current flowing bi-directionally can be controlled by changing the gate voltage.
In a case of controlling an AC power as in the above-mentioned matrix converter, it is preferable that forward characteristics and backward characteristics of the bidirectional field-effect transistor (for example, drain current vs. drain-source voltage, drain current vs. gate-source voltage, on-resistance, gate-source capacitance, reverse voltage, etc) are substantially equal to each other.
For an approach, the gate region including the gate electrode 13a is preferably arranged in the center of the first region including the first electrode 11a and the second region including the second electrode 12a. Thus, the length L1 of the left drift region is equal to the length L2 of the right drift region, thereby substantially equalizing forward and backward characteristics with each other.
For another approach, an interval between the gate electrode 13a and the first electrode 11a is preferably substantially equal to another interval between the gate electrode 13a and the second electrode 12a, thereby substantially equalizing forward and backward characteristics with each other.
For yet another approach, an interval between the channel of the gate region and the n+ contact layer 11 is preferably substantially equal to another interval between the channel of the gate region and the n+ second contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, the carrier concentration of the n+ contact layer 11 is preferably substantially equal to the carrier concentration of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, a depth of the n+ contact layer 11 is preferably substantially equal to a depth of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
On a substrate 1 formed is a buffer layer 2, on which a channel layer 3 is formed. In the channel layer 3, there are a gate region including a channel parallel to the principal surface of the substrate 1, a first region which is provided on a first side of the channel (left side of the drawing), and a second region which is provided on a second side of the channel (right side of the drawing).
In the gate region, provided are an insulation layer 14, which is formed on the channel layer 3, and a gate electrode 13a for controlling conductance of the channel. In the first region, provided is a first electrode 11a which can act as either source electrode or drain electrode. In the second region, provided is a second electrode 12a which can act as either drain electrode or source electrode in contrast to the first electrode 11a. Both between the gate region and the first region and between the gate region and the second region, formed are drift regions through which majority carriers can pass.
The substrate 1 can be formed of a wafer of semiconductor, such as Si, SiC, GaN, herein, which is formed of an n+ layer having a relatively higher carrier concentration. On the back side of the substrate 1, formed is a common electrode 10a which is typically grounded.
In particular, the substrate 1 and the respective layers 2 and 3 are preferably formed of semiconductor material of SiC, which has excellent physical properties of approximately three times larger energy gap, approximately ten times higher electric breakdown field, approximately twice higher saturation electron velocity, and approximately three times larger thermal conductivity than Si, thereby resulting in a power FET device with a small size and large capacity. In addition, when the channel layer 3 is formed of SiC, the insulation layer 14 can be formed of SiO2, similarly to a Si-based MOS-FET, by an oxidation process using a mask having a predetermined opening.
The buffer layer 2 is epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of a p− layer having a relatively lower carrier concentration.
The channel layer 3 is also epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of an n layer having a normal carrier concentration.
In the gate region, formed is a p layer 15 having a normal carrier concentration by diffusion or ion implantation of a p-type dopant. On the p layer 15, the gate electrode 13a is formed. In the first region, formed is an n+ contact layer 11 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 11, the first electrode 11a is formed. In the second region, formed is an n+ contact layer 12 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 12, the second electrode 12a is formed.
Next, operation of this device will be described below. When a positive gate voltage is applied to the gate electrode 13a with a reference voltage (=0 volt) of the common electrode 10a, the inversion layer which can act as a channel is induced. In this state, when a positive voltage +V is applied to the first electrode 11a and a negative voltage −V is applied to the second electrode 12a, a forward current flows through the path from the first electrode 11a via the n+ contact layer 11, the left drift region, the channel within the gate region, the right drift region and the n+ contact layer 12 to the second electrode 12a. Next, a negative gate voltage is applied to the gate electrode 13a, so that the inversion layer disappears to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the forward current.
Meanwhile, in a state of applying a positive gate voltage to the gate electrode 13a, when a negative voltage −V is applied to the first electrode 11a and a positive voltage +V is applied to the second electrode 12a, a backward current flows through the path from the second electrode 12a via the n+ contact layer 12, the right drift region, the channel within the gate region, the left drift region and the n+ contact layer 11 to the first electrode 11a. Next, a negative gate voltage is applied to the gate electrode 13a to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the backward current.
Thus, the first and second electrodes 11a and 12a can alternately act as source electrode or drain electrode, and an AC current flowing bi-directionally can be controlled by changing the gate voltage. Incidentally, a range of the gate voltage to be changed may be optionally designed depending on an enhancement or depression mode of characteristics of MOS-FET.
In a case of controlling an AC power as in the above-mentioned matrix converter, it is preferable that forward characteristics and backward characteristics of the bidirectional field-effect transistor (for example, drain current vs. drain-source voltage, drain current vs. gate-source voltage, on-resistance, gate-source capacitance, reverse voltage, etc) are substantially equal to each other.
For an approach, the gate region including the gate electrode 13a is preferably arranged in the center of the first region including the first electrode 11a and the second region including the second electrode 12a. Thus, the length L1 of the left drift region is equal to the length L2 of the right drift region, thereby substantially equalizing forward and backward characteristics with each other.
For another approach, an interval between the gate electrode 13a and the first electrode 11a is preferably substantially equal to another interval between the gate electrode 13a and the second electrode 12a, thereby substantially equalizing forward and backward characteristics with each other.
For yet another approach, an interval between the channel of the gate region and the n+ contact layer 11 is preferably substantially equal to another interval between the channel of the gate region and the n+ second contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, the carrier concentration of the n+ contact layer 11 is preferably substantially equal to the carrier concentration of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, a depth of the n+ contact layer 11 is preferably substantially equal to a depth of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
On a substrate 1 formed is a buffer layer 2, on which a channel layer 3 is formed. In the channel layer 3, there are a gate region including a channel parallel to the principal surface of the substrate 1, a first region which is provided on a first side of the channel (left side of the drawing), and a second region which is provided on a second side of the channel (right side of the drawing).
In the gate region, provided is a gate electrode 13a for controlling conductance of the channel. In the first region, provided is a first electrode 11a which can act as either source electrode or drain electrode. In the second region, provided is a second electrode 12a which can act as either drain electrode or source electrode in contrast to the first electrode 11a. Both between the gate region and the first region and between the gate region and the second region, formed are drift regions through which majority carriers can pass.
The substrate 1 can be formed of a wafer of semiconductor, such as Si, SiC, GaN, herein, which is formed of an n+ layer having a relatively higher carrier concentration. On the back side of the substrate 1, formed is a common electrode 10a which is typically grounded.
In particular, the substrate 1 and the respective layers 2 and 3 are preferably formed of semiconductor material of SiC, which has excellent physical properties of approximately three times larger energy gap, approximately ten times higher electric breakdown field, approximately twice higher saturation electron velocity, and approximately three times larger thermal conductivity than Si, thereby resulting in a power FET device with a small size and large capacity.
The buffer layer 2 is epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of a p− layer having a relatively lower carrier concentration.
The channel layer 3 is also epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of an n layer having a normal carrier concentration.
In the gate region, the gate electrode 13a is formed directly on the channel layer 3. In the first region, formed is an n+ contact layer 11 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 11, the first electrode 11a is formed. In the second region, formed is an n+ contact layer 12 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 12, the second electrode 12a is formed.
Next, operation of this device will be described below. When a positive gate voltage is applied to the gate electrode 13a with a reference voltage (=0 volt) of the common electrode 10a, the depletion layer in the gate region is reduced. In this state, when a positive voltage +V is applied to the first electrode 11a and a negative voltage −V is applied to the second electrode 12a, a forward current flows through the path from the first electrode 11a via the n+ contact layer 11, the left drift region, the channel within the gate region, the right drift region and the n+ contact layer 12 to the second electrode 12a. Next, a negative gate voltage is applied to the gate electrode 13a, so that the depletion layer is increased to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the forward current.
Meanwhile, in a state of applying a positive gate voltage to the gate electrode 13a, when a negative voltage −V is applied to the first electrode 11a and a positive voltage +V is applied to the second electrode 12a, a backward current flows through the path from the second electrode 12a via the n+ contact layer 12, the right drift region, the channel within the gate region, the left drift region and the n+ contact layer 11 to the first electrode 11a. Next, a negative gate voltage is applied to the gate electrode 13a to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the backward current.
Thus, the first and second electrodes 11a and 12a can alternately act as source electrode or drain electrode, and an AC current flowing bi-directionally can be controlled by changing the gate voltage.
In a case of controlling an AC power as in the above-mentioned matrix converter, it is preferable that forward characteristics and backward characteristics of the bidirectional field-effect transistor (for example, drain current vs. drain-source voltage, drain current vs. gate-source voltage, on-resistance, gate-source capacitance, reverse voltage, etc) are substantially equal to each other.
For an approach, the gate region including the gate electrode 13a is preferably arranged in the center of the first region including the first electrode 11a and the second region including the second electrode 12a, i.e., as shown in
For another approach, an interval between the gate electrode 13a and the first electrode 11a is preferably substantially equal to another interval between the gate electrode 13a and the second electrode 12a, thereby substantially equalizing forward and backward characteristics with each other.
For yet another approach, an interval between the channel of the gate region and the n+ contact layer 11 is preferably substantially equal to another interval between the channel of the gate region and the n+ second contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, the carrier concentration of the n+ contact layer 11 is preferably substantially equal to the carrier concentration of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, a depth of the n+ contact layer 11 is preferably substantially equal to a depth of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
On a substrate 1 formed is a buffer layer 2, on which a channel layer 3 is formed. In the channel layer 3, there are a gate region including a channel parallel to the principal surface of the substrate 1, a first region which is provided on a first side of the channel (left side of the drawing), and a second region which is provided on a second side of the channel (right side of the drawing).
In the gate region, provided is a gate electrode 13a for controlling conductance of the channel. In the first region, provided is a first electrode 11a which can act as either source electrode or drain electrode. In the second region, provided is a second electrode 12a which can act as either drain electrode or source electrode in contrast to the first electrode 11a. Both between the gate region and the first region and between the gate region and the second region, formed are drift regions through which majority carriers can pass.
The substrate 1 can be formed of a wafer of semiconductor, such as Si, SiC, GaN, herein, which is formed of an n+ layer having a relatively higher carrier concentration. On the back side of the substrate 1, formed is a common electrode 10a which is typically grounded.
In particular, the substrate 1 and the respective layers 2 and 3 are preferably formed of semiconductor material of SiC, which has excellent physical properties of approximately three times larger energy gap, approximately ten times higher electric breakdown field, approximately twice higher saturation electron velocity, and approximately three times larger thermal conductivity than Si, thereby resulting in a power FET device with a small size and large capacity.
The buffer layer 2 is epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of a p− layer having a relatively lower carrier concentration.
The channel layer 3 is also epitaxially grown using chemical vapor deposition (CVD) or the like, herein, which is formed of an n layer having a normal carrier concentration. On the channel layer 3, an insulation layer 16 of SiO2 is formed except for each location of the electrodes.
In the gate region, the gate electrode 13a is formed directly on the channel layer 3, and an electrically conductive field plates 13b are provided on the insulation layer 16 so as to surround the peripheral edge of the gate electrode 13a. Since concentration of electric fields takes place near the edge of the gate electrode 13a inside the channel layer 3, the field plates 13b can function so as to relax concentration of electric fields near the edge.
In the first region, formed is an n+ contact layer 11 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 11, the first electrode 11a is formed. In the second region, formed is an n+ contact layer 12 having a relatively higher carrier concentration by diffusion or ion implantation of an n-type dopant. On the n+ contact layer 12, the second electrode 12a is formed.
Next, operation of this device will be described below. When a positive gate voltage is applied to the gate electrode 13a with a reference voltage (=0 volt) of the common electrode 10a, the depletion layer in the gate region is reduced. In this state, when a positive voltage +V is applied to the first electrode 11a and a negative voltage −V is applied to the second electrode 12a, a forward current flows through the path from the first electrode 11a via the n+ contact layer 11, the left drift region, the channel within the gate region, the right drift region and the n+ contact layer 12 to the second electrode 12a. Next, a negative gate voltage is applied to the gate electrode 13a, so that the depletion layer is increased to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the forward current.
Meanwhile, in a state of applying a positive gate voltage to the gate electrode 13a, when a negative voltage −V is applied to the first electrode 11a and a positive voltage +V is applied to the second electrode 12a, a backward current flows through the path from the second electrode 12a via the n+ contact layer 12, the right drift region, the channel within the gate region, the left drift region and the n+ contact layer 11 to the first electrode 11a. Next, a negative gate voltage is applied to the gate electrode 13a to reduce conductance of the channel, thereby increasing resistance of the path and suppressing the backward current.
Thus, the first and second electrodes 11a and 12a can alternately act as source electrode or drain electrode, and an AC current flowing bi-directionally can be controlled by changing the gate voltage.
In a case of controlling an AC power as in the above-mentioned matrix converter, it is preferable that forward characteristics and backward characteristics of the bidirectional field-effect transistor (for example, drain current vs. drain-source voltage, drain current vs. gate-source voltage, on-resistance, gate-source capacitance, reverse voltage, etc) are substantially equal to each other.
For an approach, the gate region including the gate electrode 13a is preferably arranged in the center of the first region including the first electrode 11a and the second region including the second electrode 12a, i.e., as shown in
For another approach, an interval between the gate electrode 13a and the first electrode 11a is preferably substantially equal to another interval between the gate electrode 13a and the second electrode 12a, thereby substantially equalizing forward and backward characteristics with each other.
For yet another approach, an interval between the channel of the gate region and the n+ contact layer 11 is preferably substantially equal to another interval between the channel of the gate region and the n+ second contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, the carrier concentration of the n+ contact layer 11 is preferably substantially equal to the carrier concentration of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
For still yet another approach, a depth of the n+ contact layer 11 is preferably substantially equal to a depth of the n+ contact layer 12, thereby substantially equalizing forward and backward characteristics with each other.
Incidentally, in each of the above-described embodiments, the substrate 1 and the channel layer 3 are of n-conductivity type and the buffer layer 2, the RESURF layer 4 (
The present invention proposes new bidirectional field-effect transistors, which are very useful in downsizing and upgrading in capacity various AC power control equipments, such as matrix converter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-356947 | Dec 2004 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2005/018137 | 9/30/2005 | WO | 00 | 5/18/2007 |
