Binary Number Multiplying Method and Circuit

Abstract

A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn−i·yi], wherein the initial matrix [Eni=xn−i·yi] is transformed into a matrix [Eni=(xn−i⊕yi)·(yi−1⊕yi)=(xn−i⊕y1)·Yi] with Yi=yi−1⊕yi or [Eni=eni·Yi] with eni=xn−i⊕yi. A first approximation Un0 and Rn−1i−1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following Yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni−1 is carried out over the zero Yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Description

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

None.

THE NAMES OF PARTIES TO A JOINT RESEARCH AGREEMENT

None.

FIELD OF THE DISCLOSURE

This disclosure relates to a binary number multiplying method and circuit using an array of adders.

It finds a particularly important, although not exclusive, application in the field of computer systems implementing algorithms requiring many multiplications to be carried out quickly such as for example in the digital signal processing field.

It can therefore be used, more simply and more efficiently, instead of known multipliers implemented by coding or with counters.

BACKGROUND OF THE DISCLOSURE

Multipliers of the type based on a dot matrix scheme are already known.

Here the multiplicand is shifted, multiplied by a multiplier bit and added with the intermediate sum from the previous calculation.

The operation is then repeated to the last bit, addition of the shifted multiplicand values being performed either by coding using simplifying algorithms considering the successive elements as multiples, (coding of the type known by the name “Booth” coding), which makes it possible to reduce the number of multiplicands to be added, or by using an array of half-adders arranged as counters.

Such multipliers can however be further improved; this is because they prove to be expensive in terms of power and are also difficult to test beforehand perfectly reliably.

SUMMARY

An aspect of the disclosure starts with a new arrangement with successive approximations organised in three stages, which does not use the matrix generated by the known logical ANDs of multipliers and multiplicands, but the EXCLUSIVE OR, which is much easier to test.

With an embodiment of the invention, the calculation matrix is re-expressed in a different form, by transforming it so that it expresses the actual structure of the number sought.

With this aim, an embodiment of the invention essentially proposes a method for multiplying, using an array of adders, two binary numbers X and Y of N and M bits respectively, namely:

$\hspace{1em}\{\begin{array}{c}X=x_N·2^N+x_{N-1}·2^{N-1}+\dots +x_n·2^n+\dots +x_1·2^1+x_0·2^0\\ Y=y_M·2^M+y_{M-1}·2^{M-1}+\dots +y_n·2^n+\dots +y_1·2^1+y_0·2^0\end{array}$

defining an initial matrix [E_nⁱ=x_n−i·y_i], characterised in thatthe initial matrix [E_nⁱ=x_n−i·y_i] is transformed into a matrix [E_nⁱ=(x_n−i⊕y_i)·(y_i−1 ⊕y_i)=(x_n−i⊕y_i)·Y_i] with Y_i=y_i−1⊕y, or [E_nⁱ=e_nⁱ·Y_i] with e_nⁱ=x_n−i⊕y_i, wherein the step of multiplying comprises:forming a first approximation U_n⁰ and R_n+1⁰ of a sum and carry of the first two rows y₀ and y₁ of this matrix thus transformed over the entire length of said numbers,using this first approximation as an input for a following estimation step which is repeated for all the following rows, successively carrying out an addition of the following Y_i+1 rows up to the last non-zero row, according to a first given series of propagation equations,carrying-out a propagation of the carries R_nⁱ⁻¹ over the zero Y_i+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product: P=p_M+N+1·2^M+N+1+p_M+N·2^M+N+ . . . +p_n·2^N+ . . . +p₁·2¹+p₀·2⁰

In advantageous embodiments, one and/or another of the following provisions are also used:

• • The first approximation of the bits of the sum U_n⁰ is determined by performing a calculation using the signal corresponding to the value E_n⁰ of the matrix corrected by the signal corresponding to the value Y₁=y₀⊕y_1′,and in that the first approximation of the bits of the carry R_n+i⁰ is determined by performing a calculation using the signals corresponding to the values E_n−1⁰ and E_n¹ of the matrix corrected by the signal corresponding to the value Y₁=y₀⊕y₁;
  • The first approximation is given by the formula:

$\hspace{1em}\{\begin{array}{c}{U}_n^0=y_1\oplus y_0·x_n\\ R_n^0=y_1·\stackrel{\_}{y_0}·x_{n-1}\end{array}$

called EI1;

• • By re-expressing it as a function of Y₁, Y₀, E_n⁰, E_n−1⁰ the first approximation is then given by the formulae:

$\hspace{1em}\{\begin{array}{c}{U}_n^0=Y_1\oplus E_n^0\\ R_n^0=Y_1·\left(\stackrel{\_}{E_n^1\oplus E_{n-1}^0}\right)\end{array}$

called E′I1

with the following carry look-ahead hypotheses: if the second row is not zero (Y₁=1), a carry is anticipated irrespective of the value of the first row (Y₀=0 or Y₀=1)

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=y_1·y_0\oplus y_0·x_n\\ R_n^0=y_1·\stackrel{\_}{y_0}·\left(x_{n-1}\oplus 1\right)\end{array}$

called EI2with: Y₀=0⊕y₀=y₀ and Y₁=y₀⊕y₁;

• • By re-expressing it as a function of Y₁, Y₀, E_n⁰, E_n−1⁰, it becomes

$\{\hspace{1em}\begin{array}{c}{U}_n^0=Y_1·Y_0\oplus E_n^0\\ R_n^0=Y_1·\left(\stackrel{\_}{E_n^1\oplus E_{n-1}^0}\right)\oplus Y_1·\stackrel{\_}{Y_0}\end{array}$

called E′I2with the following carry look-ahead hypotheses: if the two rows are not zero (Y₀=1 and Y₁=1), a carry is anticipated;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=\stackrel{\_}{y_0}\oplus y_0·x_n\\ R_n^0=\stackrel{\_}{y_1}·\stackrel{\_}{y_0}\oplus y_1·x_{n-1}\end{array}$

called EI3;

• • By re-expressing it as a function of Y₁, Y₀, E_n⁰, E_n−1⁰ the first approximation is given by the formulae:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=1\oplus E_n^0\\ R_n^0=\left(\stackrel{\_}{E_n^1\oplus E_{n-1}^0}\right)\end{array}$

called E′I3 with the following carry look-ahead hypotheses: irrespective of the values of Y₀ and Y₁, a carry is anticipated;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=y_1.\stackrel{\_}{y_0}\oplus y_0·x_n\\ R_n^0=y_1·x_{n-1}\end{array}$

called EI4;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=y_1\oplus \stackrel{\_}{y_1}·\stackrel{\_}{y_0}\oplus y_0·x_n\\ R_n^0=\stackrel{\_}{y_1}·\stackrel{\_}{y_0}\oplus y_1·\stackrel{\_}{y_0}·x_{n-1}\end{array}$

called EI5;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=\stackrel{\_}{y_1}·\stackrel{\_}{y_0}\oplus y_0·x_n\\ R_n^0=\stackrel{\_}{y_0}\oplus y_1·x_{n-1}\end{array}$

called EI6;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=y_1·x_n\\ R_n^0=y_1·\stackrel{\_}{y_0}\oplus y_1·x_{n-1}\end{array}$

called EI7;

• • The first approximation is given by the formula:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=y_1\oplus \stackrel{\_}{y_0}\oplus y_0·x_n\\ R_n^0=\stackrel{\_}{y_0}\oplus y_1·\stackrel{\_}{y_0}·x_{n-1}\end{array}$

called EI8;

• • The first series of equations is written:

$\{\hspace{1em}\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-i}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=\left(\stackrel{\_}{U_{n-1}^{i-1}\oplus R_{n-1}^{i-1}\oplus E_{n}^{i+1}}\right)·Y_{i+1}\oplus \left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}$

called EEP1with E_nⁱ⁺¹=(x_n⊕y_i+1)·Y_i+1 and Y_i+1=y_i⊕y_i+1;

• • The first series of equations is written

$\{\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=Y_{i+1}·\stackrel{\_}{R_n^{i-1}}·\left(\stackrel{\_}{E_{n+1}^{i+1}\oplus U_n^{i-1}}\right)\oplus \stackrel{\_}{Y_{i+1}}·R_n^{i-1}·\left(U_n^{i-1}\oplus U_{n-1}^{i-1}\right)\end{array}$

called EEP2;

• • The first series of equations is written

$\{\hspace{1em}\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=\left(Y_{i+1}\oplus R_n^{i-1}\right)·\left(\stackrel{\_}{e_{n+1}^{i+1}\oplus U_n^{i-1}}\right)\end{array}$

called EEP3with e_n+1ⁱ⁺¹=x_n−i⊕y_i+1;

• • The second series of equations is written:

$\{\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_{n+1}^i=\left(U_n^{i-1}\oplus U_{n-1}^{i-1}\right)·R_n^{i-1}\end{array}$

called EP1;

• • The second series of equations is written:

$\{\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_{n+1}^i=\left(\stackrel{\_}{e_{n+1}^{i+1}\oplus U_n^{i-1}}\right)·R_n^{i-1}\end{array}$

called EP2;

• • The second series of equations is performed with Carry-Look-Ahead type adders.

An embodiment of the invention also proposes a multiplying system comprising calculation means implementing the above-mentioned method.

It also proposes more precisely a multiplier making it possible to multiply input signals comprising a first N-bit binary number (X) and a second M-bit binary number (Y), namely:

$\{\hspace{1em}\begin{array}{c}X=x_N·2^N+x_{N-1}·2^{N-1}+\dots +x_n·2^n+\dots +x_1·2^1+x_0·2^0\\ Y=y_M·2^M+y_{M-1}·2^{M-1}+\dots +y_n·2^n+\dots +y_1·2^1+y_0·2^0\end{array}$

defining an initial matrix [E_nⁱ=x_n−i·y_i],wherein the multiplier comprises:calculation means for transforming the initial matrix [E_nⁱ=x_n−i·y_i] into a matrix [E_nⁱ=(x_n−i⊕y_i)·(y_i−1⊕y_i)=(x_n−i⊕y_i)·Y_i] with Y_i=y_i−1⊕y_i or [E_nⁱ=e_nⁱ·Y_i] with e_nⁱ=x_n−i⊕y_i,initial estimation module (MEO_i) arranged to provide a first approximation U_n⁰ and R_n+1⁰ of the sum and carry of the first two rows y₀ and y₁ over an entire length N of said numbers, comprising N estimation blocks (MI_i) connected in parallel, each estimation block being capable of performing said sums and said carries,an estimation/propagation module (MEEP_i) arranged to successively carry out the addition of the following Y_i+1 rows up to the last non-zero row, according to a first given series of propagation equations, comprising estimation/propagation blocks (MEP_i) connected in cascade, each estimation/propagation block being capable of performing said sums and said carries,and a propagation module (MP_i), propagating the carries R_nⁱ⁻¹ on the zero y_i+1 rows according to a second given series of propagation equations.

Advantageously, the means (MPi) of propagating the carries R_nⁱ⁻¹ comprise estimation blocks in inverse cascade, each estimation block being capable of performing said carries.

Also advantageously and in order to speed up the operation of the means (Mpi) of propagating the carries R_nⁱ⁻¹, a Carry-Look-Ahead type form of adder is used.

The disclosure will be better understood from a reading of the following description of embodiments given hereinafter for information only and non-limitatively.

BRIEF DESCRIPTION OF THE DRAWINGS

This refers to the accompanying figures, wherein:

FIG. 1 shows the initial calculation matrix of a 5×5-bit multiplier;

FIG. 2 shows the transformation of an expression of a known matrix of the type in FIG. 1, into a new matrix for use with an embodiment of the invention;

FIG. 3A shows an example matrix obtained according to the invention after transformation and

FIG. 3B shows the values taken during successive iterations;

FIGS. 4 to 7 show graphically, by way of example, the development and operation of the first series of equations;

FIGS. 8 to 10 are example representations of logic circuits corresponding respectively to embodiments of the first approximation (EI1), the first series of equations (EEP3) and the second series of equations (EP1);

FIG. 11 is a general diagram of a multiplier according to an embodiment of the invention more particularly described here, with a detail (FIG. 11A);

FIG. 12 shows a multiplier variant whereof the last stage is replaced by a “Carry-Look-Ahead” type stage, with a detail (FIG. 12A);

FIG. 13 gives a functional diagram of the multiplier of an embodiment of the invention more particularly described here; and

FIGS. 14 and 15 are schematic and functional representations of the steps or modules for initial estimation and estimation/propagation by virtue of the first series and/or second series of equations, according to one embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 shows the initial calculation matrix for the multiplication of two binary numbers of five bits each, namely:

$\{\hspace{1em}\begin{array}{c}X=x_4·2^4+x_3·2^3+x_2·2^2+x_1·2^1+x_0·2^0\\ Y=y_4·2^4+y_3·2^3+y_2·2^2+y_1·2^1+y_0·2^0\end{array}$

The product will therefore be expressed in 10 bits:

P=p₉·2⁹+p₈·2⁸+ . . . +p₁·2¹+p₀·2⁰ (see row 1 of FIG. 1).

For the known form the values E_nⁱ are furthermore such that E_nⁱ=x_n−i·y_i and the values E_nⁱ outside the hatched area 2 of FIG. 1 are zero.

According to an embodiment of the invention, a new expression of this initial matrix is used with values E_nⁱ such that:

E _n ⁱ=(x_n−i⊕y_i)·(y_i−1⊕y_i)=(x_n−1⊕y_i)·Y_i

with Y_i=y_i−1⊕y_i or E_nⁱ=e_nⁱ·Y_i with e_nⁱ=x_n−i⊕y_i.

The equivalence between the two forms of matrix {the known form (referenced 3 in FIG. 2) and that used with an embodiment of the invention, referenced 4 in FIG. 2)} is shown hereinafter with reference to said FIG. 2.

It has already been noted that the new matrix 4 has a row 5 more than the standard matrix 3 (with E_nⁱ=x_n−i·y_i), since the last row 6 of this matrix 4 contains the values:

E_n⁵=(x_n−5⊕y₅)·Y₅=x_n−5·Y₅ and Y₅=y₄⊕y₅=y₄ which can therefore be non-zero.

More precisely, the known matrix expressed as a function of E_nⁱ=x_n−i·y_i is transformed into a new matrix expressed as a function of E_nⁱ=(x_n−i⊕y_i)·(y_i−1⊕y_i) by re-expression of the sets of bits at 1 of the known matrix.

This transformation is done on the basis of the following considerations.

Let there be a set of bits having the value 1.

This set is generated by the bits x_k to x_k+n−1 having the value 1 multiplied by the bits y₁ to y_1+m−1 having the value 1. The result S is expressed thus:

S=(x_k+n−1·2^k+n−1+ . . . +x_k+1·2^k+1+x_k·2^k)·(y_1+ω−1·2^i+m−1+ . . . +y_i+1·2ⁱ⁺¹+y₁·2¹)

By assigning the values x_i=1, y_i=1 and factorising 2^k and 2¹, it becomes:

S=2^k+1·(2ⁿ⁻¹+ . . . +2¹+2⁰)·(2^m−1+ . . . +2¹+2⁰)

S=2^k+1·(2ⁿ−2⁰)·(2^m−2⁰)=2^k+1·(2^n+m−2^m−2ⁿ+2⁰)

S=2^k+1·[(2^n+m−2^m)+(2^+∞−2ⁿ−2^∞)+(2⁰−2^−∞+2^−∞)]

S=2^k+1·(2^n+m−2^m)+(2^+∞−2^k+1+n−2^+∞)+(2^k+1−2^−∞+2^−∞)

with:2^k+1·(2^n+m−2^m): portion referenced 7 in dot-and-dash lines in FIG. 2;(2^+∞−2^k+1+n−2^+∞): portion referenced 8 and 8′ in FIG. 2 in dot-and-dash lines;(2^k+1−2^−∞+2^−∞): portion referenced 9 and 9′ in FIG. 2 in dot-and-dash lines.

Thus and in a numerical example with a multiplier y=63669=1111100010110101 and a multiplicand x=40119=1001110010110111 the initial matrix is expressed according to Table I below.

TABLE I
																	1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1	<--	1
																0	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0	<--	0
															1	0	0 1 1 1 0 0 1 0 1 1 0 1 1 1	<--	1
														0	0	0	0 0 0 0 0 0 0 0 0 0 0 0 0	<--	0
													1	0	0	1	1 1 0 0 1 0 1 1 0 1 1 1	<--	1
												1	0	0	1	1	1 0 0 1 0 1 1 0 1 1 1	<--	1
											0	0	0	0	0	0	0 0 0 0 0 0 0 0 0 0	<--	0
										1	0	0	1	1	1	0	0 1 0 1 1 0 1 1 1	<--	1
									0	0	0	0	0	0	0	0	0 0 0 0 0 0 0 0	<--	0
								0	0	0	0	0	0	0	0	0	0 0 0 0 0 0 0	<--	0
							0	0	0	0	0	0	0	0	0	0	0 0 0 0 0 0	<--	0
						1	0	0	1	1	1	0	0	1	0	1	1 0 1 1 1	<--	1
					1	0	0	1	1	1	0	0	1	0	1	1	0 1 1 1	<--	1
				1	0	0	1	1	1	0	0	1	0	1	1	0	1 1 1	<--	1
			1	0	0	1	1	1	0	0	1	0	1	1	0	1	1 1	<--	1
		1	0	0	1	1	1	0	0	1	0	1	1	0	1	1	1	<--	1
Product =	1	0	0	1	1	0	0	0	0	1	0	0	0	0	0	0	0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1
Product =	2554336611 to the base 10
Multiplier = 63669 = 1111100010110101
Multiplicand = 40119 = 1001110010110111

And after transformation according to an embodiment of the invention, the matrix 10 of FIG. 3A is obtained.

Bits 11, 12, 13, 14 and 15 surrounded by a double frame represent the 2^∞ values and bits 16, 17, 18, 19 and 20 the 2^+∞ values.

It should therefore be noted that an additional row 21 is necessary for the matrix transformed into 2^1+m.

It can also be seen that, in the multiplication described, it is not necessary to add the 2^−∞ values since it is carried out with adders that always assume a carry.

Neither is it necessary to propagate the carries beyond the parallelogram for the same reason.

There will now be described in greater detail the principle of the multiplication (applied to the above numerical example) implemented in the embodiment of the invention more particularly described here, with reference to FIG. 3B, the formula E′I1 for the first approximation, the formula EEP1 for the first series of equations and the formula EP1 for the second series of equations.

First of all the first approximation U_n⁰ and R_n+1⁰ of the sum of the first 2 rows of the matrix is calculated.

Let E₀⁰ to E₉⁰ and E₀¹ to E₉¹ be the rows to be added:

• • If the row E₀¹ to E₉¹ is zero (i.e. Y₁=y₀⊕y₁=0_, then U_n⁰=E_n⁰;
  • If the row E₀¹ to E₉¹ is not zero, an initial estimate of the sum is: U_n⁰= E_n⁰.

The estimate is: U_n⁰= Y₁·E_n⁰⊕Y₁· E_n^o that is: U_n⁰=Y₁⊕E_n⁰.

As regards the refinement in n, this is:

• • If the row is zero (Y₁=0, R_n⁰=0;
  • If the row is not zero, R_n⁰= E_n¹⊕E_n−1⁰.

The refinement is therefore: R_n⁰=Y₁·(E_n¹⊕E_n−1⁰).

At the next row (row 23 in FIG. 3B), the row E₀² to E₉² is added to the rows U₀⁰ to U₉⁰ and R₀⁰ to R₉⁰ in order to estimate U₀¹ to U₉¹ and R₀¹ to R₉¹.

• • If row 23 is zero (Y₂=0, E₀² to E₉²=0), it is necessary to correct the initial estimates and propagate the refinements thus:

$\{\hspace{1em}\begin{array}{c}{U}_n^1=U_n^0\oplus R_n^0\\ R_n^1=\left(U_{n-1}^0\oplus U_{n-2}^0\right)·R_{n-1}^0\end{array}$

This algorithm is shown by FIG. 4.

Here, R_n¹ comprises only one propagation component.

• • If row 25 is not zero (Y₂=1), the initial estimates are corrected (calculation of U_n⁰⊕R_n⁰) and a new estimate U_n¹ is generated using this corrected value: U_n¹= U_n⁰⊕R_n⁰.

An R_n¹ refinement component is calculated with the corrected value (U_n−1⁰⊕R_n−1⁰) and E_n² such that R_n¹= E_n²⊕(U_n−1⁰⊕R_n−1⁰).

This is shown in FIG. 5.

For this case also it is necessary to generate the propagation component (U_n−1⁰⊕U_n−2⁰)·R_n−1⁰. Synthesis of the two cases (Y₂=0 and Y₂=1) gives the following formulae:

$\{\hspace{1em}\begin{array}{c}{U}_n^1=\stackrel{\_}{Y_2}·\left[U_n^0\oplus R_n^0\right]\oplus Y_2·\left[\stackrel{\_}{U_n^0\oplus R_n^0}\right]\\ R_n^1=\stackrel{\_}{Y_2}·\left[\left(U_{n-1}^0\oplus U_{n-2}^0\right)·R_{n-1}^0\right]\oplus Y_2·\left[\begin{array}{c}\stackrel{\_}{E_n^2\oplus \left(U_{n-1}^0\oplus R_{n-1}^0\right)}\oplus \\ \left(U_{n-1}^0\oplus U_{n-2}^0\right)·R_{n-1}^0\end{array}\right]\end{array}$

That is after simplification:

$\{\hspace{1em}\begin{array}{c}{U}_n^1=U_n^0\oplus R_n^0\oplus Y_2\\ R_n^1=Y_2·\left[\stackrel{\_}{E_n^2\oplus \left(U_{n-1}^0\oplus R_{n-1}^0\right)}\right]\oplus \left(U_{n-1}^0\oplus U_{n-2}^0\right)·R_{n-1}^0\end{array}$

For the following rows 24 to 37, the previous formulae are generalised.

• • If row (i+1) is zero

$\left(Y_{i+1}=0,E_0^i\mathrm{to}E_9^i=0\right),\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_n^i=\left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}$

If row (i+1) is not zero (Y_i+1=1),

$\{\hspace{1em}\begin{array}{c}{U}_n^i=\stackrel{\_}{U_n^{i-1}\oplus R_n^{i-1}}\\ R_n^i=\stackrel{\_}{E_n^{i+1}\oplus \left(U_{n-1}^{i-1}\oplus R_{n-1}^{i-1}\right)}\oplus \left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}$

(See FIG. 7).

Synthesis of the two cases (Y_i+1=0 and Y_i+1=1 then gives the following formulae:

$\{\hspace{1em}\begin{array}{c}{U}_n^i=\stackrel{\_}{Y_{i+1}}·\left[U_n^{i-1}\oplus R_n^{i-1}\right]\oplus Y_{i+1}·\left[\stackrel{\_}{U_n^{i-1}\oplus R_n^{i-1}}\right]\\ R_n^i=\stackrel{\_}{Y_{i+1}}·\left[\left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\right]\oplus Y_{i+1}·\left[\begin{array}{c}\stackrel{\_}{E_n^{i+1}\oplus \left(U_n^{i-1}\oplus R_{n-1}^{i-1}\right)}\oplus \\ \left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}\right]\end{array}$

That is after simplification:

$\hspace{1em}\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_n^i=Y_{i+1}·\left[\stackrel{\_}{E_n^{i+1}\oplus \left(U_{n-1}^{i-1}\oplus R_{n-1}^{i-1}\right)}\right]\oplus \left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}$

When all the rows E₀ⁱ to E₃₁ⁱ have been added (result of row 37 in FIG. 3B), it is necessary to propagate the refinements of the result obtained: rows U₀¹⁵ to U₃₁¹⁵ and R₀¹⁵ to R₃₁¹⁵ in order to obtain the product P₀ to P₃₁ when all of R₀ⁱ to R₃₁ⁱ are all zero.

To do this, and according to the embodiment of the invention more particularly described here, propagation is done with the following equations:

$\{\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_n^i=\left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1},\end{array}$

that is according to EP1 (row 39).

It should be noted here that this corresponds to additions with zero rows.

Finally the result at row 39 of FIG. 3B is obtained, reproducing the row also referenced 39 in FIG. 3A.

More precisely, and in order to show in logic circuit form the first approximation used above, it should be noted that the initial approximation U_n⁰ and R_n+1⁰ of the sum of the first two rows of the matrix is calculated with so-called “initial estimation” modules implementing the following equations:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=Y_1\oplus E_n^0\\ R_n^0=Y_1·\left(\stackrel{\_}{E_n^1\oplus E_{n-1}^0}\right)\end{array}$

For implementation in modules, the signals to be generated are grouped together so as to minimise the inputs. The equations arranged by module then instead calculate U_n⁰ and R_N+1⁰ with the following initial estimation/refinement equations or formulae:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=Y_1\oplus E_n^0\\ R_{n+1}^0=Y_1·\left(\stackrel{\_}{E_{n+1}^1\oplus E_n^0}\right)\end{array}$

By substituting the values E_n⁰=(x_n⊕y₀)·Y₀ and E_n+1^1=(x_n⊕y₁)·Y₁ in the above equations, this gives:

$\{\begin{array}{c}{U}_n^0=Y_1\oplus x_n·Y_0\oplus Y_0=Y_1\oplus Y_0·\left(x_n\oplus 1\right)=Y_1\oplus Y_0·\stackrel{\_}{x_n}\\ \begin{array}{c}{R}_{n+1}^0=Y_1·\left(x_n·Y_0\oplus Y_0\oplus x_n·Y_{1}\oplus y_1·Y_1\oplus 1\right)\\ =Y_1·\left(x_n·Y_0\oplus x_n\oplus Y_0\oplus y_1\oplus 1\right)\end{array}\end{array}\mathrm{With}\text{:}Y_1=y_0\oplus y_1\mathrm{and}Y_0=y_0\{\begin{array}{c}{U}_n^0=Y_1\oplus Y_0·\stackrel{\_}{x_n}\\ R_{n+1}^0=Y_1·\left(x_n·\stackrel{\_}{Y_0}\oplus y_0\oplus y_1\oplus 1\right)=Y_1·x_n·\stackrel{\_}{Y_0}\oplus Y_1·\left(\stackrel{\_}{y_0\oplus y_1}\right)\end{array}$

The following is obtained:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=\stackrel{\_}{x_n}·Y_0\oplus Y_1\\ R_{n+1}^0=x_n·\stackrel{\_}{Y_0}·Y_1\end{array}$

This can also be expressed as:

$\{\hspace{1em}\begin{array}{c}{U}_n^0=x_n·Y_0\oplus y_1\\ R_{n+1}^0=x_n·\stackrel{\_}{Y_0}·y_1\end{array}$

These equations are set out in diagram 40 of FIG. 8.

FIG. 9 furthermore shows an example embodiment of the estimation/propagation module (MEP) 41 implementing the equation EEP3.

The addition of the following rows of the matrix is in fact calculated with the so-called “estimation/propagation” modules implementing the following equations:

$\{\hspace{1em}\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_n^i=Y_{i+1}·\left[\stackrel{\_}{E_n^{i+1}\oplus \left(U_{n-1}^{i-1}\oplus R_{n-1}^{i-1}\right)}\right]\oplus \left(U_{n-1}^{i-1}\oplus U_{n-2}^{i-1}\right)·R_{n-1}^{i-1}\end{array}$

As previously, the signals are grouped together in order to minimise the inputs and therefore the equations arranged by module instead calculate a system that is a function of U_nⁱ and R_n+1ⁱ:

$\begin{array}{cc}\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=Y_{i+1}·\left[\stackrel{\_}{E_{n+1}^{i+1}\oplus \left(U_n^{i-1}\oplus R_n^{i-1}\right)}\right]\oplus \left(U_n^{i-1}\oplus U_{n-1}^{i-1}\right)·R_n^{i-1}\end{array}& \mathrm{EEP1}\end{array}$

As regards the expression of R_n+1ⁱ, this can be broken down as a function of the terms and Y_i+1 and R_nⁱ⁻¹ as follows:

R _n+1 ⁱ =Y _i+1 ·R _n ⁱ⁻¹·[ E_n+1ⁱ⁺¹⊕(U_nⁱ⁻¹⊕R_nⁱ⁻¹)]⊕Y_i+1· R_nⁱ⁻¹·[ E_n+1ⁱ⁺¹⊕(U_nⁱ⁻¹⊕R_nⁱ⁻¹)]⊕(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)·R_nⁱ⁻·Y_i+1⊕(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)·R_nⁱ⁻¹·Y_i+1

Then, with grouping together of the two terms in Y_i+1·R_nⁱ⁻¹ and simplification, it becomes:

R _n+1 ⁱ =Y _i+1 ·R _n ⁱ⁻¹·[ E_M+1ⁱ⁺¹⊕(U_nⁱ⁻¹⊕R_nⁱ⁻¹)⊕U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹]⊕Y_i+1· R_nⁱ⁻¹[ E_n+1ⁱ⁺¹⊕(U_nⁱ⁻¹⊕R_nⁱ⁻¹)]⊕(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹⁾·R_nⁱ⁻¹ · Y

R _n+1 ⁱ =Y _i+1 ·R _n ⁱ⁻¹ ·[E _n+1 ⁱ⁺¹⊕ R_nⁱ⁻¹⊕U_n−1ⁱ⁻¹]⊕Y_i+1· R_nⁱ⁻¹·(E_n+1ⁱ⁺¹⊕U_nⁱ⁻¹⊕ R_nⁱ⁻¹)⊕(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)·R_nⁱ⁻¹· Y_i+1

R _n+1 ⁱ =Y _i+1 ·R _n ⁱ⁻¹·(E_n+1ⁱ⁺¹⊕U_n−1ⁱ⁻¹)⊕Y_I+1· R_nⁱ⁻¹(E_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)⊕R_nⁱ⁻¹· Y_i+1·(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)

A recursive equation discovered by the inventor furthermore shows that: Y_i+1·R_nⁱ⁻¹·(E_n+1ⁱ⁺¹⊕U_n−1ⁱ⁻¹)=0.

The following system of equations is thus obtained:

$\begin{array}{cc}\hspace{1em}\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=Y_{i+1}·\stackrel{\_}{R_n^{i-1}}·\left(\stackrel{\_}{E_{n+1}^{i+1}\oplus U_n^{i-1}}\right)\oplus \stackrel{\_}{Y_{i+1}}·R_n^{i-1}·\left(U_n^{i-1}\oplus U_{n-1}^{i-1}\right)\end{array}& \mathrm{EEP}2\end{array}$

which is the one implemented in one embodiment of the invention.

The system of equations EEP2 can also be simplified by the following transformations:

The following is written: E_n+1ⁱ⁺¹=(x_n−i⊕y_i+1)·Y_i+1=e_n+1ⁱ⁺¹·Y_i+1 with

e _n+1 ⁱ⁺¹ =x _n−i ⊕y _i+1

or in general terms e_K^J=x_K−J⊕y_J.

The second equation of EEP2 is then written:

R _n+1 ⁱ =Y _i+1· R_nⁱ⁻¹·(e_n+1ⁱ⁺¹·Y_i+1⊕U_nⁱ⁻¹)⊕ Y_i+1·R_nⁱ⁻¹·(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)

That is:

R _n+1 ⁱ =Y _i+1· R_nⁱ⁻¹·(e_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)⊕ Y_i+1·R_nⁱ⁻¹·(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)

Factorisation of a term (Y_i+1⊕R_nⁱ⁻¹):

R _n+1 ⁱ =Y _i+1·(Y_i+1⊕R_nⁱ⁻¹)·( e_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)⊕ Y_i+1·(Y_i+1⊕R_nⁱ⁻¹)·(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)

By grouping together the factor term of Y_i+1,

This gives:

R _n+1 ⁱ=(Y_i+1⊕R_nⁱ⁻¹)·[(e_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)⊕ Y_i+1·(e_n+1ⁱ⁺¹⊕U_n−1ⁱ⁻¹)]

However another recursive equation discovered by the inventor furthermore shows that:

(Y_i+1⊕R_nⁱ⁻¹)·[ Y_i+1·(e_n+1ⁱ⁺¹⊕U_n−1ⁱ⁻¹)]= Y_i+1·R_nⁱ⁻¹·(e_n+1ⁱ⁺¹⊕U_n−1ⁱ⁻¹)=0

Hence: R_n+1ⁱ=(Y_i+1⊕R_nⁱ⁻¹)·( e_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)

The following system of equations is then obtained:

$\begin{array}{cc}\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\oplus Y_{i+1}\\ R_{n+1}^i=\left(Y_{i+1}\oplus R_n^{i-1}\right)·\left(\stackrel{\_}{e_{n+1}^{i+1}\oplus U_n^{i-1}}\right)\end{array}& \mathrm{EEP}3\end{array}$

with: e_n+1ⁱ⁺¹=x_n−i⊕y_i+1

which is the one more particularly implemented in one embodiment of the invention.

As indicated above, one possible arrangement of this system 41 is shown in FIG. 9.

Several other gate arrangements are possible.

Either using the expression:

R _n+1 ⁱ =Y _i+1· R_nⁱ⁻¹·(E_n+1ⁱ⁺¹⊕U_nⁱ⁻¹)⊕ Y_i+1·R_nⁱ⁻¹·(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)

or using the expression:

R _n+1 ⁱ =U _i+1·[ E_n+1ⁱ⁺¹⊕(U_nⁱ⁻¹⊕R_nⁱ⁻¹)]⊕(U_nⁱ⁻¹⊕U_n−1ⁱ⁻¹)·R_nⁱ⁻¹

Finally, according to the embodiment of the invention more particularly described here, a second series of equations is used which therefore implement the equations:

$\begin{array}{cc}\{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_{n+1}^i=\left(U_n^{i-1}\oplus U_{n-1}^{i-1}\right)·R_n^{i-1}\end{array}\mathrm{or}& \mathrm{EP}1\\ \{\begin{array}{c}{U}_n^i=U_n^{i-1}\oplus R_n^{i-1}\\ R_{n+1}^i=\left(\stackrel{\_}{e_{n+1}^{i+1}\oplus U_n^{i-1}}\right)·R_n^{i-1}\end{array}& \mathrm{EP}2\end{array}$

For this a final propagation module (referred to as MP) (see FIG. 10) is for example implemented.

FIG. 11 shows the general diagram of a 5-bit×5-bit multiplier 43 implementing the arrangements described above according to the embodiment of the invention more particularly described. This device 43 consists of three stages:

the first stage 44 comprises a row of initial estimation modules (MI0 to MI4),

the second stage 45 comprises four rows of estimation/propagation modules (MEP10 to MEP15, MEP20 to MEP26, MEP30 to MEP37, MEP40 to MEP48),

the third stage 46 comprises an array of propagation modules (MPxx).

As regards the most significant bit, this is generated by an EXCLUSIVE OR cascade 47.

Finally, there is shown at 48 (FIG. 11A) the logic diagrams for obtaining the values Yi, Y0 from the values y_i using the EXCLUSIVE OR gates according to the advantageous embodiment of the invention.

A description has also been given with reference to FIG. 12 of another embodiment of the invention using a Carry-Look-Ahead type final propagation as the third stage.

In order to reduce the propagation time, the last propagation module stage can in fact be replaced by a “Carry-Look-Ahead” type stage 49 taking as an input the form of expression in U_nⁱ⁻¹, U_n−1ⁱ⁻¹ and R_nⁱ⁻¹ or the form of expression in U_nⁱ⁻¹, e_n+1ⁱ⁺¹ and R_nⁱ⁻¹.

Here again, and as for FIG. 11A, the logic diagrams 48 have been shown using the EXCLUSIVE OR gates according to an embodiment of the invention.

As regards FIG. 13, this gives a functional description of the multiplier 50 according to the embodiment of the invention more particularly described here, showing the modularity of the structure.

A first stage 51 comprising the initial estimation modules ME0_i 52 is provided, which feeds the second stage 53 of estimation and propagation modules MEP1_i 54, which itself feeds the third stage 55 of propagation modules MEPmi to give the product P.

One functional interpretation of the initial estimation modules 52 and estimation/propagation modules 54 is described in FIGS. 14 and 15.

These interpretations are a function of one way of expressing the equations implemented.

Other interpretations are of course possible for other expressions of the equations.

More precisely, FIG. 14 shows the initial estimation module 52.

Using an estimation input E_n⁰ which feeds a multiplexer 60, on the one hand directly (link 58) and on the other hand via an estimation calculator 59, mixing is performed with the input y₁, in order to obtain the initial estimate U_n⁰.

As regards the carry R_n⁰, this is obtained using the inputs E_n−1⁰ and E_n¹ which feed a refinement calculation unit 61 as described above before activating a multiplexer 62 into which the input y₁ is also introduced, in order to obtain in the end the carry R_n⁰.

As regards FIG. 15, this shows the estimation/propagation module 54 making it possible to modify the values U_nⁱ and the carries R_n+1ⁱ according to an embodiment of the invention by implementing the above-mentioned algorithms.

Using the inputs U_nⁱ⁻¹ and R_nⁱ⁻¹ the correction in n of the values is performed (block 63) by application of the refinement.

The output 64 then feeds, on the one hand an estimation calculator 65, itself connected to the multiplexer 66, on the other hand (line 67) the same multiplexer (bit 0) into which the value y_i+1 is also introduced, and finally a refinement calculator 67. The multiplexer 66 gives the value U_nⁱ.

As regards the carry R_n+1, this is obtained by means of a multiplexer 69 fed by the values Y_i+1 and R_n−1ⁱ⁻¹ and by the output of the calculator 68, and the propagation/refinement calculation circuit 70, a circuit itself having as inputs U_n−1ⁱ⁻¹, U_nⁱ⁻¹ and R_nⁱ⁻¹.

As is self-evident and established by what has gone before, this invention is not limited to the embodiments more particularly described. On the contrary it encompasses all the variants thereof and in particular those where the logic circuits are constituted differently for obtaining the same result.

An embodiment of this invention provides a multiplying method and circuit satisfying practical requirements better than those known previously, in particular in that it permits a particular property not present in the prior art, on account of the intermediate expression of the number calculated in a form of approximations with successive refinements. Such a form facilitates operational tests of the proposed circuit, and for a cost in general lower and a speed at the very least equivalent.

Although the present disclosure has been described with reference to one or more examples, workers skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the disclosure and/or the appended claims.

Claims

1. A method comprising: multiplying, using an array of adders, two binary numbers X and Y of N and M bits respectively, namely:

2. The method according to claim 1, wherein the first approximation of the bits of the sum Un0 is determined by performing a calculation using a signal corresponding to the value En0 of the matrix corrected by a signal corresponding to the value Y1=y0⊕y1, and wherein the first approximation of the bits of the carry Rn+10 is determined by performing a calculation using signals corresponding to the values En−10 and En1 of the matrix corrected by the signal corresponding to the value Y1=y0⊕y1.

3. The method according to claim 2, wherein the first approximation is given by the formulae:

4. The method according to claim 3, wherein by re-expressing the first approximation as a function of Y1, Y0, En0, En−10 the first approximation is then given by the formulae:

5. The method according to claim 1, wherein the first approximation is given by the formulae:

6. The method according to claim 5, wherein by re-expressing as a function of Y1, Y0, En0, En−10, it becomes:

7. The method according to claim 1, wherein the first approximation is given by the formulae:

8. The method according to claim 3, characterised in that by re-expressing the first approximation as a function of Y1, Y0, En0, En−10 the first approximation is given by the formulae:

9. The method according to claim 1, wherein the first approximation is given by the formula:

10. The method according to claim 1, wherein the first approximation is given by the formula:

11. The method according to claim 1, wherein the first approximation is given by the formula:

12. The method according to claim 1, wherein the first approximation is given by the formula:

13. The method according to claim 1, wherein the first approximation is given by the formula:

14. The method according to claim 1, wherein the first series of equations is written:

15. The method according to claim 1, wherein the first series of equations is written

16. The method according to claim 1, wherein the first series of equations is written:

17. The method according to claim 1, wherein the second series of equations is written:

18. The method according to claim 1, wherein the second series of equations is written:

19. The method according to claim 1, wherein the second series of equations is performed with Carry-Look-Ahead type adders.

20. A multiplier making it possible to multiply input signals comprising a first binary number (X) and a second binary number (Y) of N and M bits respectively, namely:

21. The multiplier according to claim 20, wherein the propagating module comprises estimation blocks in inverse cascade, each estimation block being capable of performing said carries.

22. The multiplier according to claim 20, wherein the module comprises Carry-Look-Ahead type adders.

23. The multiplier according to claim 20, wherein the initial approximation module comprises means for calculating Un0 comprising an “EXCLUSIVE OR” type logic gate capable of receiving as inputs the bit corresponding to y1 and a bit coming from a first “AND” logic gate producing the product of the bits Xn and Y0, and means for calculating the carry Rn+10 comprising a second “AND” type logic gate capable of receiving as inputs the bits corresponding to y1, Y0 and xn.

24. The multiplier according to claim 20, wherein the initial approximation module implements the formulae:

25. The multiplier according to claim 20, wherein the initial approximation module implements the formulae:

26. The multiplier according to claim 20, wherein the initial approximation module implements the formulae:

27. The multiplier according to claim 20, wherein the estimation/propagation module arranged to successively carry out the addition of the following yi+1 rows up to the last non-zero row implements the first series of following equations:

28. The multiplier according to claim 20, wherein the estimation/propagation module arranged to successively carry out the addition of the following yi+1 rows up to the last non-zero row implements the first series of following equations:

29. The multiplier according to claim 20, wherein the estimation/propagation module arranged to successively carry out the addition of the following yi+1 rows up to the last non-zero row implements the first series of following equations:

30. The multiplier according to claim 29, wherein the estimation/propagation module arranged to successively carry out the addition of the following yi+1 rows up to the last non-zero row comprises a circuit for calculating Uni comprising a first “EXCLUSIVE OR” type logic gate capable of receiving as inputs the bit corresponding to Rni−1 and the bit corresponding to Yi+1, said gate delivering a signal to the input of a second “EXCLUSIVE OR” type gate in order, in combination with a second input corresponding to the previously calculated bit Uni−1, to give the signal Uni,and means for calculating Rn+1i comprising a third “Inverse EXCLUSIVE OR” type gate capable of receiving as inputs the bit corresponding to xn−i and the bit corresponding to yi+1, said gate delivering a signal to the input of a fourth “EXCLUSIVE OR” type gate furthermore receiving as the second input the bit corresponding to Uni−1,the output signals of said fourth and first “EXCLUSIVE OR” type logic gates forming the inputs of an “AND” type gate adapted to deliver the bit corresponding to the value of Rn+1i.

31. The multiplier according to claim 20, wherein the propagating module for propagating the carries Rni−1 on the zero yi+1 rows according to a second series of propagation equations implements the formulae:

32. The Multiplier according to claim 31, the propagating module for propagating the carries Rni−1 on the zero yi+1 rows according to a second series of zero propagation equations comprises: a circuit for calculating Uni comprising a first <<EXCLUSIVE OR” type logic gate capable of receiving as inputs the bit corresponding to Rni−1 and bit corresponding to Uni−1 and a circuit for calculating Rn+1i comprising a second <<EXCLUSIVE OR” type logic gate receiving as the first input the bit value corresponding to Uni−1 and as the second input the bit corresponding to Un−1i−1, in order to generate a signal that feeds, in combination with the bit corresponding to Rni−1, an “AND” logic gate adapted to give the value of Rn+1i.

33. The multiplier according to claim 20, wherein the propagating module for propagating the carries Rni−1 on the zero yi+1 rows according to a second series of propagation equations implements the formulae: