Bit mapping scheme for an LDPC coded 32APSK system

Abstract

A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 32APSK system with FEC coding, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.

Description

RELATED APPLICATIONS

This application relates to application Ser. No. 12/717,815, titled “A Bit Mapping Scheme for an LDPC Coded 16APSK System” filed on Mar. 4, 2010, and application Ser. No. 12/710,276 titled “An Interleaving Scheme for an LDPC Coded 32APSK System” filed on Feb. 22, 2010.

FIELD OF THE INVENTION

The invention relates to digital communications and in particular to a bit mapping scheme for an LDPC coded 32APSK System.

BACKGROUND OF THE INVENTION

Forward Error Control (FEC) coding is used by communications systems to ensure reliable transmission of data across noisy communication channels. Based on Shannon's theory, these communication channels exhibit a fixed capacity that can be expressed in terms of bits per symbol at a given Signal to Noise Ratio (SNR), which is defined as the Shannon limit. One of the research areas in communication and coding theory involves devising coding schemes offering performance approaching the Shannon limit while maintaining a reasonable complexity. It has been shown that LDPC codes using Belief Propagation (BP) decoding provide performance close to the Shannon limit with tractable encoding and decoding complexity.

In a recent paper Yan Li and William Ryan, “Bit-Reliability Mapping in LDPC-Codes Modulation systems”, IEEE Communications Letters, vol. 9, no. 1, January 2005, the authors studied the performance of LDPC-coded modulation systems with 8PSK. With the authors' proposed bit reliability mapping strategy, about 0.15 dB performance improvement over the non-interleaving scheme is achieved. Also the authors show that gray mapping is more suitable for high order modulation than other mapping scheme such as natural mapping.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the present invention are directed to a bit mapping scheme in a 32APSK modulation system. The techniques of these embodiments are particularly well suited for use with LDPC codes.

LDPC codes were first described by Gallager in the 1960s. LDPC codes perform remarkably close to the Shannon limit. A binary (N, K) LDPC code, with a code length N and dimension K, is defined by a parity check matrix H of (N-K) rows and N columns. Most entries of the matrix H are zeros and only a small number the entries are ones, hence the matrix H is sparse. Each row of the matrix H represents a check sum, and each column represents a variable, e.g., a bit or symbol. The LDPC codes described by Gallager are regular, i.e., the parity check matrix H has constant-weight rows and columns.

Regular LDPC codes can be extended to form irregular LDPC codes, in which the weight of rows and columns vary. An irregular LDPC code is specified by degree distribution polynomials v(x) and c(x), which define the variable and check node degree distributions, respectively. More specifically, the irregular LDPC codes may be defined as follows:

$\begin{array}{cc}v\left(x\right)=\sum _{j=1}^{d_{v\max }}{v}_j{x}^{j-1},\mathrm{and}& \left(1\right)\\ c\left(x\right)=\sum _{j=1}^{d_{c\max }}{c}_j{x}^{j-1},& \left(2\right)\end{array}$

where the variables d_{v max} and d_{c max} are a maximum variable node degree and a check node degree, respectively, and v_j(c_j) represents the fraction of edges emanating from variable (check) nodes of degree j. While irregular LDPC codes can be more complicated to represent and/or implement than regular LDPC codes, it has been shown, both theoretically and empirically, that irregular LDPC codes with properly selected degree distributions outperform regular LDPC codes. FIG. 1 illustrates a parity check matrix representation of an exemplary irregular LDPC code of codeword length six.

LDPC codes can also be represented by bipartite graphs, or Tanner graphs. In Tanner graph, one set of nodes called variable nodes (or bit nodes) corresponds to the bits of the codeword and the other set of nodes called constraints nodes (or check nodes) corresponds the set of parity check constrains which define the LDPC code. Bit nodes and check nodes are connected by edges, and a bit node and a check node are said to be neighbors or adjacent if they are connected by an edge. Generally, it is assumed that a pair of nodes is connected by at most one edge.

FIG. 2 illustrates a bipartite graph representation of the irregular LDPC code illustrated in FIG. 1.

LDPC codes can be decoded in various ways such as majority-logic decoding and iterative decoding. Because of the structures of their parity check matrices, LDPC codes are majority-logic decodable. Although majority-logic decoding requires the least complexity and achieves reasonably good error performance for decoding some types of LDPC codes with relatively high column weights in their parity check matrices (e.g., Euclidean geometry LDPC and projective geometry LDPC codes), iterative decoding methods have received more attention due to their better performance versus complexity tradeoffs. Unlike majority-logic decoding, iterative decoding processes the received symbols recursively to improve the reliability of each symbol based on constraints that specify the code. In a first iteration, an iterative decoder only uses a channel output as input, and generates reliability output for each symbol.

Subsequently, the output reliability measures of the decoded symbols at the end of each decoding iteration are used as inputs for the next iteration. The decoding process continues until a stopping condition is satisfied, after which final decisions are made based on the output reliability measures of the decoded symbols from the last iteration. According to the different properties of reliability measures used during each iteration, iterative decoding algorithms can be further divided into hard decision, soft decision and hybrid decision algorithms. The corresponding popular algorithms are iterative bit-flipping (BF), belief propagation (BP), and weighted bit-flipping (WBF) decoding, respectively. Since BP algorithms have been proven to provide maximum likelihood decoding when the underlying Tanner graph is acyclic, they have become the most popular decoding methods.

BP for LDPC codes is a type of message passing decoding. Messages transmitted along the edges of a graph are log-likelihood ratio

${\left(\mathrm{LLR}\right)}^{\log \frac{p_0}{p_1}}$ associated with variable nodes corresponding to codeword bits. In this expression p₀ and p₁ denote the probability that the associated bit value becomes either a 0 or a 1, respectively. BP decoding generally includes two steps, a horizontal step and a vertical step. In the horizontal step, each check node c_m sends to each adjacent bit b_n a check-to-bit message which is calculated based on all bit-to-check messages incoming to the check c_m except one from bit b_n. In the vertical step, each bit node b_n sends to each adjacent check node c_m a bit-to-check message which is calculated based on all check-to-bit messages incoming to the bit b_n except one from check node c_m. These two steps are repeated until a valid codeword is found or the maximum number of iterations is reached.

Because of its remarkable performance with BP decoding, irregular LDPC codes are among the best for many applications. Various irregular LDPC codes have been accepted or being considered for various communication and storage standards, such as DVB-S2/DAB, wireline ADSL, IEEE 802.11n, and IEEE 802.16.

The threshold of an LDPC code is defined as the smallest SNR value at which, as the codeword length tends to infinity, the bit error probability can be made arbitrarily small. The value of threshold of an LDPC code can be determined by analytical tool called density evolution.

The concept of density evolution can also be traced back to Gallager's results. To determine the performance of BF decoding, Gallager derived formulas to calculate the output BER for each iteration as a function of the input BER at the beginning of the iteration, and then iteratively calculated the BER at a given iteration. For a continuous alphabet, the calculation is more complex. The probability density functions (pdf's) of the belief messages exchanged between bit and check nodes need to be calculated from one iteration to the next, and the average BER for each iteration can be derived based on these pdf's. In both check node processing and bit node processing, each outgoing belief message is a function of incoming belief messages. For a check node of degree d_c, each outgoing message U can be expressed by a function of d_c−1 incoming messages,U=F_c(V₁, V₂, . . . , V_dc-1),

where F_c denotes the check node processing function which is determined from BP decoding. Similarly, for bit node of degree d_v, each outgoing message V can be expressed by a function of d_v−1 incoming messages and the channel belief message U_ch,V=F_V(U_ch, U₁, U₂, . . . , U_dv-1),

where F_v denotes the bit node processing function. Although for both check and bit node processing, the pdf of an outgoing message can be derived based on the pdf's of incoming messages for a given decoding algorithm, there may exist an exponentially large number of possible formats of incoming messages. Therefore the process of density evolution seems intractable. Fortunately, it has been proven in that for a given message-passing algorithm and noisy channel, if some symmetry conditions are satisfied, then the decoding BER is independent of the transmitted sequence x. That is to say, with the symmetry assumptions, the decoding BER of all-zero transmitted sequence x=1 is equal to that of any randomly chosen sequence, thus the derivation of density evolution can be considerably simplified. The symmetry conditions required by efficient density evolution are channel symmetry, check node symmetry, and bit node symmetry. Another assumption for the density evolution is that the Tanner graph is cyclic free.

According to these assumptions, the incoming messages to bit and check nodes are independent, and thus the derivation for the pdf of the outgoing messages can be considerably simplified. For many LDPC codes with practical interests, the corresponding Tanner graph contains cycles. When the minimum length of a cycle (or girth) in a Tanner graph of an LDPC code is equal to 4×l, then the independence assumption does not hold after the l-th decoding iteration with the standard BP decoding. However, for a given iteration number, as the code length increases, the independence condition is satisfied for an increasing iteration number. Therefore, the density evolution predicts the asymptotic performance of an ensemble of LDPC codes and the “asymptotic” nature is in the sense of code length.

A bit mapping scheme is provided for low density parity check (LDPC) encoded bits in 32APSK modulation systems. The disclosed bit mapping scheme provides good threshold of LDPC codes. Furthermore the bit mapping scheme can facilitate design of interleaving arrangement in 32APSK modulation system.

To propose a bit mapping approach for LDPC coded 32APSK systems. The disclosed bit mapping offers good performance of LDPC coded 32APSK system and simplifies interleaving arrangement in 32APSK systems.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the corresponding drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 is a parity check matrix representation of an exemplary irregular LDPC code of codeword length six.

FIG. 2 illustrates a bipartite graph representation of the irregular LDPC code illustrated in FIG. 1.

FIG. 3 illustrates the bit mapping block in 32APSK modulation, according to various embodiments of the invention.

FIG. 4 illustrates a bit map for 32APSK symbol, according to various embodiments of the invention.

FIG. 5 depicts an exemplary communications system which employs LDPC codes and 32APSK modulation, according to various embodiments of the invention.

FIG. 6 depicts an exemplary transmitter employing 32APSK modulation in FIG. 5, according to various embodiments of the invention.

FIG. 7 depicts an exemplary receiver employing 32APSK demodulation in FIG. 5, according to various embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the accompanying drawings, a detailed description will be given of exemplary encoded bit mapping methods using LDPC codes according to various embodiments of the invention.

Although the invention is described with respect to LDPC codes, it is recognized that the bit mapping approach can be utilized with other codes. Furthermore, it is recognized that this approach can be implemented with uncoded systems.

FIG. 5 is a diagram of a communications system employing LDPC codes with 32APSK modulation, according to an embodiment of the present invention. A communications system includes a transmitter 501 which generates signal waveforms across a communication channel 502 to a receiver 503. The transmitter 501 contains a message source producing a discrete set of possible messages. Each of these messages corresponds a signal waveform. The waveforms enter the channel 502 and are corrupted by noise. LDPC codes are employed to reduce the disturbances introduced by the channel 502 and a 32APSK modulation scheme is employed to transform LDPC encoded bits to signal waveforms.

FIG. 6 depicts an exemplary transmitter in the communications system of FIG. 5 which employs LDPC codes and 32APSK modulation. The LDPC encoder 602 encodes information bits from source 601 into LDPC codewords. The mapping from each information block to each LDPC codeword is specified by the parity check matrix (or equivalently the generator matrix) of the LDPC code. The LDPC codeword is interleaved and modulated to signal waveforms by the interleaver/modulator 603 based on a 32APSK bit mapping scheme. These signal waveforms are sent to a transmit antenna 604 and propagated to a receiver shown in FIG. 7.

FIG. 7 depicts an exemplary receiver in FIG. 5 which employs LDPC codes and 32APSK demodulator. Signal waveforms are received by the receiving antenna 701 and distributed to demodulator/deinterleavor 702. Signal waveforms are demodulated by demodulator and deinterleaved by deinterleavor and then distributed to a LDPC decoder 703 which iteratively decodes the received messages and output estimations of the transmitted codeword. The 32APSK demodulation rule employed by the demodulator/deinterleaver 702 should match with the 32APSK modulation rule employed by the interleaver/modulator 603.

According to various embodiments of the invention, as shown in FIG. 3, the 32APSK bit-to-symbol mapping circuit may utilize five bits (b5i, b5i+1, b5i+2, b5i+3, b5i+4) each iteration and map them into an I value and a Q value, with i=0, 1, 2, . . . . The bit mapping logic is shown in FIG. 4. The bit mapping according to various embodiments of the invention is defined as follows:

$\left(I\left(i\right),Q\left(i\right)\right)=(\begin{array}{cc}\left(R_2\cos \left(\pi /4\right),R_2\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,0,0,0\right)\\ \left(R_2\cos \left(\pi /12\right),R_2\sin \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,0,0,1\right)\\ \left(R_3\cos \left(\pi /8\right),R_3\sin \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,0,1,0\right)\\ \left(R_3,0\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,0,1,1\right)\\ \left(R_2\sin \left(\pi /12\right),R_2\cos \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,1,0,0\right)\\ \left(R_1\cos \left(\pi /4\right),R_1\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,1,0,1\right)\\ \left(R_3\sin \left(\pi /8\right),R_3\cos \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,1,1,0\right)\\ \left(R_3\cos \left(\pi /4\right),R_3\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,0,1,1,1\right)\\ \left(R_2\cos \left(\pi /4\right),-R_2\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,0,0,0\right)\\ \left(R_2\cos \left(\pi /12\right),-R_2\sin \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,0,0,1\right)\end{array}\{\begin{array}{cc}\left(R_3\cos \left(\pi /4\right),-R_3\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,0,1,0\right)\\ \left(R_3\cos \left(\pi /8\right),-R_3\sin \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,0,1,1\right)\\ \left(R_2\sin \left(\pi /12\right),-R_2\cos \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,1,0,0\right)\\ \left(R_1\cos \left(\pi /4\right),-R_1\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,1,0,1\right)\\ \left(0,-R_3\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,1,1,0\right)\\ \left(R_3\sin \left(\pi /8\right),-R_3\cos \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(0,1,1,1,1\right)\\ \left(-R_2\cos \left(\pi /4\right),R_2\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,0,0,0\right)\\ \left(-R_2\cos \left(\pi /12\right),R_2\sin \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,0,0,1\right)\\ \left(-R_3\cos \left(\pi /4\right),R_3\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,0,1,0\right)\\ \left(-R_3\cos \left(\pi /8\right),R_3\sin \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,0,1,1\right)\end{array}(\begin{array}{cc}\left(-R_2\sin \left(\pi /12\right),R_2\cos \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,1,0,0\right)\\ \left(-R_1\cos \left(\pi /4\right),R_1\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,1,0,1\right)\\ \left(0,R_3\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,1,1,0\right)\\ \left(-R_3\sin \left(\pi /8\right),R_3\cos \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,0,1,1,1\right)\\ \left(-R_2\cos \left(\pi /4\right),-R_2\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,0,0,0\right)\\ \left(-R_2\cos \left(\pi /12\right),-R_2\sin \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,0,0,1\right)\\ \left(-R_3\cos \left(\pi /8\right),-R_3\sin \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,0,1,0\right)\\ \left(-R_3,0\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,0,1,1\right)\\ \left(-R_2\sin \left(\pi /12\right),-R_2\cos \left(\pi /12\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,1,0,0\right)\\ \left(-R_1\cos \left(\pi /4\right),-R_1\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,1,0,1\right)\\ \left(-R_3\sin \left(\pi /8\right),-R_3\cos \left(\pi /8\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,1,1,0\right)\\ \left(-R_3\cos \left(\pi /4\right),-R_3\sin \left(\pi /4\right)\right),& \left(b_{5i},b_{5i+1},b_{5i+2},b_{5i+3},b_{5i+4}\right)=\left(1,1,1,1,1\right)\end{array}$

According to various embodiments of the invention, the bit mapping scheme of FIG. 4 may use gray mapping which means the binary representations of adjacent points differ by only one bit. Density evolution analysis shows that given an LDPC coded 32APSK system, gray mapping scheme can provide the best threshold. The bit mapping scheme of FIG. 4 also arranges bit in an order based on the values of log likelihood ratio from communications channel. This arrangement simplifies the design of interleaving scheme for 32APSK system. It is also appreciated that bit mapping scheme of the invention may be implemented on a computer readable medium and executed by a processor or computer, as understood by the skilled artisan.

Although the invention has been described by the way of examples of preferred embodiments, it is to be understood that various other adaptations and modifications may be made within the spirit and scope of the invention. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Claims

1. A method of bit mapping in a 32APSK system, the method comprising: transmitting a digital signal from a transmitter; andreceiving the digital signal at a receiver;wherein the digital signal utilizes a 32APSK system, and the signal is bit-mapped prior to the transmitting according to the following formula:

2. The method of claim 1, wherein an FEC code is used.

3. The method of claim 2, wherein the FEC code is regular LDPC code.

4. The method of claim 2, wherein the FEC code is irregular LDPC code.

5. The method of claim 2, wherein the FEC code is regular repeat-accumulate code.

6. The method of claim 2, wherein the FEC code is irregular repeat-accumulate code.

7. A digital communications system, comprising: a transmitter to modulate at least one mapping group having five bits (b5i, b5i+1, b5i+2, b5i+3, b5i+4), for i=0, 1, 2, . . . , to 32APSK symbols based on formula:

8. A digital communications system, comprising: a receiver to demodulate at least one mapped 32APSK symbol to an estimating message group having five bits (b5i, b5i+1, b5i+2, b5i+3, b5i+4), for i=0, 1, 2, . . . , based on a 32APSK constellation specification:

9. A non-transitory computer readable medium to store a computer program, executable by a processor, to map at least one group of five bits (b5i, b5i+1, b5i+2, b5i+3, b5i+4), for i=0, 1, 2, . . . , to a 32APSK symbol based on a formula: