BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a configuration of an image scanner according to a first embodiment of the present invention;
FIG. 2 is a block diagram of a configuration of a signal processing IC incorporated in an image scanner;
FIG. 3 is a block diagram of a configuration of a set value calculator;
FIG. 4 is a graph of a threshold level of a tracking-speed determining unit;
FIG. 5 is a flowchart of a black-level correction process as an operation example of a black-level feedback control;
FIG. 6 is a block diagram of a configuration of a set value calculator according to a second embodiment of the present invention;
FIG. 7 is a graph of a threshold level of a tracking-speed determining unit;
FIG. 8 is a flowchart of a black-level correction process as an operation example of a black-level feedback control;
FIG. 9 is a graph of a threshold level of a tracking-speed determining unit according to a third embodiment of the present invention;
FIG. 10 is a block diagram of a configuration of a set value calculator according to a fourth embodiment of the present invention;
FIG. 11 is a graph of a threshold level of a tracking-speed determining unit;
FIG. 12 is a graph of a threshold level of a tracking-speed determining unit according to a fifth embodiment of the present invention;
FIG. 13 is a block diagram of a configuration of a set value calculator according to a sixth embodiment of the present invention;
FIG. 14 is a timing chart of timings of an XSLSYNC signal and a DAC_opcnt signal;
FIG. 15 is a block diagram of a configuration of a signal processing IC incorporated in an image scanner according to a seventh embodiment of the present invention;
FIG. 16 is a timing chart of timings of an XSLSYNC signal and a BLKCLP signal;
FIG. 17 is a block diagram of a configuration of a signal processing IC incorporated in an image scanner according to an eighth embodiment of the present invention;
FIG. 18 is a timing chart of timings of an XSLSYNC signal, a DAC_opcnt signal, and an ave_clr signal;
FIG. 19 is a block diagram of a configuration of a set value calculator according to a ninth embodiment of the present invention;
FIG. 20 is a schematic of an “H” period of a BLKCLP signal according to a tenth embodiment of the present invention;
FIG. 21 is a block diagram of a configuration of a signal processing IC incorporated in a conventional image reading device;
FIG. 22 is a schematic of an image format of image data output from a CCD;
FIG. 23 is graph of frequency spread by an SSCG;
FIG. 24 is a graph of occurrence of high and low image levels; and
FIG. 25 is a schematic of a process in which a sub-scanning image level variation occurs.