Claims
- 1. A method of operating a data processing device comprising the steps of:
- generating pulses establishing instruction cycles;
- accessing a storage circuit by assertion of addresses;
- performing an arithmetic operation on data;
- decoding a program instruction providing control signals to control the operations of the data processing device within each instruction cycle;
- accessing said storage circuit by the contents of a program register to obtain a program instruction; and
- initiating a block sequence responsive to an instruction code having a block instruction wherein said block sequence comprises the steps of:
- generating a block end address by combining the contents of the program register and data decoded from the block instruction;
- storing the block end address in an end register;
- storing the contents of the program register in a repeat start register; and
- accessing said storage circuit with the program register containing a program address of a first instruction of a block of instructions.
- 2. The method of claim 1 further comprising the step of executing instructions in the block until the contents of the program register are equal to the block end address.
- 3. The method of claim 1 further comprising the step of counting how many times a block of instructions is executed.
Parent Case Info
This is a division of application Ser. No. 08/326,677, filed Oct. 20, 1994 which is a continuation under 37 CFR 1.60 of application Ser. No. 07/590,372 filed on Sep. 28, 1990, now U.S. Pat. No. 5,390,304.
US Referenced Citations (4)
Divisions (1)
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Number |
Date |
Country |
Parent |
326677 |
Oct 1994 |
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Continuations (1)
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Number |
Date |
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Parent |
590372 |
Sep 1990 |
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