In a conventional computer system, a block storage device including non-volatile memory can be communicably coupled to a block storage device controller, which, in turn, can be communicably coupled to a processor by a system bus. Such a system bus is typically implemented as a Peripheral Component Interconnect express (PCIe) bus, allowing the processor to access block data storable within the block storage device by issuing one or more input/output (I/O) commands to the block storage device controller over the PCIe bus. Having received an I/O command from the processor over the PCIe bus, the block storage device controller can perform I/O processing including one or more direct memory access (DMA) operations to access the block data storable in the block storage device, and ultimately send a signal to the processor over the PCIe bus to signal completion of the I/O processing. However, such I/O processing performed by the block storage device controller in conjunction with the PCIe bus can cause latency in the processing of block write/read operations in such a conventional computer system.
The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate one or more embodiments described herein, and, together with the Detailed Description, explain these embodiments. In the drawings:
Apparatus and methods are disclosed for accessing at least one non-volatile memory (NVM) device computer system that includes it least one host processor and at least one memory bus. In the disclosed apparatus and methods, the NVM device is communicably coupleable to the memory bus through an NVM device controller, thereby allowing the host processor to access persistent data storable within the NVM device by issuing one or more memory load/store commands to the NVM device controller over the memory bus. The computer system in conjunction with the host processor can implement a block storage driver, and the NVM device in conjunction with the NVM device controller can be collectively viewed by the computer system as a block storage device. Because the NVM device controller includes at least one block window (such a block window is also referred to herein as an “aperture”) that defines at least one address range for accessing one or more blocks of the persistent data storable within the NVM device, the computer system can as exploit, with reduced la envy full capacity of the NVM device without being unduly constrained by physical addressing limits imposed by the host processor, or by limits imposed by an operating system (OS) executed by the host processor.
In the exemplary apparatus 100 of
In the exemplary NVM controller 202 of
The address translation component 214 is operative to translate one or more logical addresses within the address range defined by the aperture 208 to actual physical addresses within a valid address range for a block write to (or a block read front) the NVM device 204, based at least on information provided by the host processor 101. The NVM controller 202 can employ the media management translation table 216 for performing wear leveling operations and/or enforcing endurance limits for the NVM device 204 (e.g., an NVM device including flash memory). The NVM controller 202 can further employ the encryption component 218 for encrypting block data to be written to the NVM device 204, as well as the decryption component 220 for decrypting block data to be read from the NVM device 204.
In an exemplary mode of operation, the host processor 101 (see
Having configured the NVM controller 202 for performing the desired block write operation to the NVM device 204, the host processor 101 can issue a memory store command over the memory bus 203 to the NVM controller 202. The memory store command provides at least the logical SW base address and the logical SW offset address, which defines a relative offset from the logical SW base address. The host processor 101 writes the memory store command to a selected one of the plurality of command registers 0-q, based at least on the logical BW base/offset address provided via the memory store command. In response to the memory store command issued. by the host processor 101, the NVM controller 202 selects the memory-mapped base address register 0, 1, . . . q associated with the status register/command register pair 0,0, 1,1, . . . q,q that includes the selected command register 0, 1, . . . q. Further, the NVM controller 202 receives block data to be written to the NVM device 204 at the relative offset from the logical SW base address within the address range of the aperture 208.
The address translation component 214 (see
The NVM controller 202 can employ the media management translation table 216 to perform wear-leveling operations, and to enforce endurance limits for the NVM device 204, as desired and/or required. The NVM controller 202 can further employ the encryption component 218 to encrypt the block data to be written to the block 204a of the NVM device 204, as desired and/or required. The NVM controller 202 can then write the block data to the actual physical address of the block 204a. At the completion of the block write to the NVM device 204, the host processor 101 can read, over the memory bus 203, the status register 0, 1, . . . , q associated with the selected command register 0, 1, . . . , q to check the error status of the block write Operation.
In this exemplars mode of operation, the host processor 101 (see
Having configured the NVM controller 202 for performing the desired block read operation from the NVM device 204, the host processor 101 can issue a memory load command over the memory bus 203 to the NVM controller 202. The memory load command provides at least the logical BR base address and the logical BR offset address, which defines a relative offset from the logical BR base address. The host processor 101 writes the memory load command to a selected one of the plurality of command registers 0-q, based at least on the logical BR base/offset address provided via the memory load command. In response to the memory load command issued by the host processor 101, the NVM controller 202 selects the memory-mapped base address register 0, 1, . . . , q associated with the status register/command register pair 0,0, 1,1, . . . , q,q that includes the selected command register 0, 1, . . . , q.
The address translation component 214 receives the logical base address from the selected base address register 0, 1, . . . , q, receives the logical BR offset address provided via the memory load command, and translates the logical base address and logical BR offset address to an actual physical address of a block (e.g., the block 204a) within the NVM device 204. The NVM controller 202 can check the translated address to determine whether it conforms to a valid address range for a block read from the NVM device 204. In the event the translated address does not conform to is valid address range for a block read from the NVM device 204, the NVM controller 202 can set an error flag in the status register 0, 1, . . . , q associated with the selected command register 0, 1, . . . , q. In the event the translated address conforms to a valid address range for a block read from the NVM device 204, the NVM controller 202 is successfully configured for performing the desired block read operation from the NVM device 204.
The NVM controller 202 can employ the decryption component 220 to decrypt the block data to be read from the block 204a of the NVM device 204, as desired and/or required.
The NVM controller 202 can then read the block data from the actual physical address of the block 204a. At the completion of the block read from the NVM device 204, the host processor 101 can read, over the memory bus 203, the status register 0, 1, . . . , q associated with the selected command register 0, 1, . . . , q to check the error status of the block read operation.
By allowing the host processor 101 to access persistent data storable within the
NVM device 204 by issuing one or more memory load/store commands to the NVM controller 202 over the memory bus 203, in which the NVM controller 202 includes the aperture 208 that defines an address range for accessing one or more blocks of the persistent data storable within the NVM device 204, a computer system can advantageously exploit, with reduced latency, the full capacity of the NVM device 204 without being unduly constrained by physical addressing limits of the host processor 101, or by limits imposed by the OS executed by the host processor 101.
The operation of an NVM controller for translating one or more logical addresses within an address range defined by an aperture to actual physical addresses of one or more blocks within an NVM device will he further understood with reference to the following illustrative example and
In this illustrative example, the aperture 308 is configured to support a block size of 256 kilobytes (KB). It is noted, however, that the aperture 308 may alternatively be configured to support a block size of 16 KB, 64 KB, 128 KB, 512 KB, 1 megabyte (MB), 2 MB, 4 MB, or any other suitable block size. Each sub-block within the block size of 256 KB is defined herein as 1/32 of the block size of 256 KB (i.e., 8 KB), or any other suitable sub-block size. Each of the plurality of memory-mapped base address registers 0-31 is therefore configured to correspond to 8 KB of the address range 0-256 KB) defined by the aperture 308. Specifically, the base address register 0 is configured to contain a 0th logical base address covering 0-8 KB of the address range defined b the aperture 308, the base address register 1 is configured to contain a logical base address covering 8-16 KB of the address range defined by the aperture 308, the base address register 2 is configured to contain a 2nd logical base address covering 16-24 KB of the address range defined by the aperture 308, and so on up to the base address register 31, which is configured to contain a logical base address covering 248-256 KB of the address range defined by the aperture 308.
With reference to this illustrative example, a memory load/store command issued by the host processor 101 (see
For example, the host processor 101 can configure the N \TM controller 302 for performing a block write. (BW) to the NVM device 204 by issuing an exemplary command that conforms to the following format:
Accordingly, the memory load/store command issued by the host processor 101 to the NVM controller 302 over the memory bus 303 can provide a logical base/offset address that can be represented by the term “X+8 KB” (plus a cache line offset, if any), which conforms to the address range, “X” to “X+256 KB”, defined by the aperture 308. The host processor 101 can write the memory load/store command to a selected one of the plurality or command registers 0-31, e.g., the command register 1, based at least on the logical base offset address, X+8 KB (plus a cache line offset if any), provided via the memory load/store command.
The address translation component 314 receives the 1st logical base address from the selected base address register 1, receives an indication of the cache line offset, if any, from the aperture 308, and translates the 1st logical base address and the cache line offset, if any, to the actual physical address of the block within the NVM device 204. The NVM controller 302 can then write the block data to, or read the block data from, the actual physical address of the respective block.
An exemplary method of operating an NVM controller for writing block data to, or reading block data from, one or more blocks within NVM device is described below with reference to
It is noted that
Having described the above exemplary embodiments of the disclosed apparatus and methods, other alternative embodiments or variations may be made. For example, it was described herein that an NVM device controller can include at least one block window (aperture) that defines at least one address range for accessing persistent data storable in one or more blocks within an NVM device. In an alternative embodiment, such an aperture can be implemented as a block window for reading block data from the NVM device, a block window for writing block data to the NVM device, and/or a write combining buffer for writing data to the NVM device with atomic write support.
It was also described herein that an NVM device controller can be configured to perform a block write operation to an NVM device by translating a logical block write address within an address range defined by an aperture to an actual physical address of a block within the NVM device. In an alternative embodiment, such a block write operation can be performed to copy data from volatile in such as dynamic random access memory (DRAM) to the NVM device over a memory bus with reduced latency.
It was further described herein that a host processor could access persistent data storable within an NVM device by issuing one or more memory load/store commands to an NVM device controller over a memory bus. As depicted in
An exemplary method of issuing a memory load/store command and monitoring completion of the memory load/store command, by a host processor using a mailbox, is described below with reference to
As depicted in block 702 (see
While the NVM device controller 620 executes the memory load/store command, the input payload is copied by the NVM device controller 620 to its internal memory, the mailbox status register 610.2 is updated by the NVM device controller 620 using the status code format 670 to indicate that the input payload is being processed (e.g., the command progress status 670.2 indicates that the command has started), and the write protect bit 662 is cleared by the NVM device controller 620, as depicted in block 710. It is noted that, once the write protect bit 662 is cleared by the NVM device controller 620. the input payload register(s) are no longer write-protected from being written to by the host processor 101, thereby allowing the host processor 101 to issue another command, over the memory bus 603 to the NNW device controller 620 using the op-code format 660, before the execution of the current command has completed.
As depicted in block 712, the status of the execution of the memory load/store command is monitored by the host processor 101 by reading the mailbox status register 610.2, using the status code format 670. In the event the mailbox status register 610.2 has been updated by the NVM device controller 620 to indicate that the execution of the memory load/store command has completed (e.g., the command progress status 670.2 indicates that the command has completed), a determination is made, by the host processor 101 using the output payload format 672, as to whether the memory load/store command requires data (e.g., block data) to be accessed from the NVM device 204 via the NVM device controller 620, as depicted in block 714. In the event the memory load/store command requires data to be accessed by the host processor 101 via the NVM device controller 620, such data is accessed, by the host processor 101 over the memory bus 603 using the output payload format 672, from at least a portion of the mailbox address range 607 defined by the payload mailbox 608, as depicted in block 716. As depicted in block 718, a determination is made, by the host processor 101, as to whether the execution of the memory load/store command has completed successfully (e.g., the command progress status 670.2 indicates that the command was successful). In the event the memory load/store command has completed successfully, the data accessed using the output payload format 672 is processed by the host processor 101, as depicted in block 720. As depicted in block 722, upon completion of the processing of the data by the host processor 101, the processor 609 within the NVM device controller 620 exits the SMM.
Although illustrative examples of various embodiments of the disclosed subject matter are described, herein, one of ordinary skill in the relevant art will appreciate that other manners of implementing the disclosed subject matter may alternatively be used. In the preceding description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific systems, apparatus, methods, and configurations were set forth in order to provide a thorough understanding of the disclosed subject matter. However, it will be apparent to one skilled in the relevant art having the benefit of this disclosure that the subject matter may he practiced without the specific details described herein. In other instances, well-known features, components, and/or modules were omitted, simplified, or combined in order not to obscure the disclosed subject matter.
It is noted that the term “operative to”, as employed herein, means that a corresponding device, system, apparatus, etc., is able to operate, or is adapted to operate, for its desired functionality when the device, system, or apparatus is in its powered-on state. Moreover, various embodiments of the disclosed subject matter may be implemented in hardware, firmware, software, or some combination thereof, and may be described by reference to, or in conjunction with, program code such as instructions, functions, procedures, data structures, logic, application programs, design representations, and/or formats for simulation, emulation, and/or fabrication of a design, which when accessed by a machine results in the machine performing tasks, defining abstract data types or low-level hardware contexts, or producing a result.
It is further noted that the techniques illustrated in the drawing figures can be implemented using code and/or data. stored and/or executed on one or more computing de ices, such as general-purpose computers or computing devices. Such computers or computing devices store and communicate code and/or data (internally and/or with other computing devices over a network) using machine-readable media such as machine readable storage media (e.g., magnetic disks, optical disks, random access memory (RAM), read only memory (ROM), flash memory devices, phase-change memory) and machine readable communication media (e.g., electrical, optical, acoustical, or other form of propagated signals such as carrier waves, infrared signals, digital signals, etc.).
No element, operation, or instruction employed herein should be construed as critical or essential to the application unless explicitly described as such. Also, as employed herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is employed. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise.
It is intended that the invention not be limited to the particular embodiments disclosed herein, but that the invention will include any and all particular embodiments and equivalents falling within the scope of the following appended claims.
Filing Document | Filing Date | Country | Kind |
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PCT/US2013/061841 | 9/26/2013 | WO | 00 |