Number | Name | Date | Kind |
---|---|---|---|
4442484 | Childs, Jr. et al. | Apr 1984 | |
4725947 | Shonai et al. | Feb 1988 | |
4777587 | Case et al. | Oct 1988 | |
4847753 | Matsuo et al. | Jul 1989 | |
4864493 | Kishi | Sep 1989 | |
4876639 | Mensch, Jr. | Oct 1989 | |
4881170 | Morisada | Nov 1989 | |
4926323 | Baror et al. | May 1990 | |
4974154 | Matsuo | Nov 1990 | |
5127091 | Boufarah et al. | Jun 1992 | |
5214770 | Ramanujan et al. | May 1993 | |
5226130 | Favor et al. | Jul 1993 | |
5265213 | Weiser et al. | Nov 1993 |
Entry |
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Sohi et al., "Instruction Issue Logic for High-Performance Interruptable Pipelined Processors", Association of Computing Machinery, pp. 27-34, 1987. |
John H. Crawford, "The i486 CPU: Executing Instructions in One Clock Cycle", IEEE Micro., Feb. 1990, pp. 27-36. |
Lee et al., "Branch Prediction Strategies and Branch Target Buffer Design", Computer, Jan. 1984, pp. 6-22. |
David J. Lilja, "Reducing the Branch Penalty in Pipelined Processors", Computer, Jul. 1988, pp. 47-55. |