BRIDGE SENSOR WITH DUMMY RESISTOR STRUCTURE

FIELD OF THE INVENTION

The invention relates to the field of magnetic field sensors. More specifically it relates to the field of biasing systems of these magnetic field sensors.

BACKGROUND OF THE INVENTION

Hall elements for measuring a magnetic field are well known, and are used inter alia in current sensors, or in angular position sensors, where a magnetic field (e.g. generated by a permanent magnet) is measured at several locations of the sensor device, and is converted into an angular position, as described for example in WO9854547 (published in 1998).

Hall elements are passive resistive structures and need to conduct a current before an output-signal can be retrieved from them. The term “biasing” is used for applying a voltage or current to such a structure. The term “readout” is used for retrieving a sensor signal or a sensor value from such a structure.

A basic Hall element (also referred to as “Hall plate”) consist of a conducting material provided with at least four electrical contacts. To make use of the “Hall effect”, a current has to flow through the element. A bias current I is supplied via two of the contacts. Two other contacts are typically placed on an equipotential line, to make the voltage difference between the sense contacts zero in the absence of a magnetic field and in the absence of an offset.

Due to process imperfections there will always be an offset present, meaning the voltage difference between the sense contacts can be non-zero even in the absence of a magnetic field. For small magnetic fields this offset can be substantially bigger than the actual useful output signal so some methods need to be applied to extract the useful signal. Current spinning is an effective way to do this. The sensing time gets divided in at least 2 phases (4 is better for 4 contact hall plates). In each phase the current is flowing in another direction.

In each phase the offset is roughly equal but the signal (due to the magnetic field) has an opposite polarity in half the phases (positive phases versus negative phases). The signal is modulated to a higher frequency and the offset remains at DC. Taking the difference of the sum of the positive phases and the sum of the negative phases gives you a signal where the offset is almost fully gone except for a smaller residual offset (due to the offset not being exactly the same in all phases) and a signal proportional to magnetic field.

The residual offset is what needs to be reduced further by improved biasing techniques. Alternatively, the offset may be modulated, and the signal may be kept at DC. In this case, taking the average of all the phases will result in a signal proportional to a magnetic field and a residual offset.

Hall plate sensors suffer from offset problems and stress sensitivity. The simplest 2 forms of biasing each have their own problems. Pure voltage biasing maximizes the sensitivity but results in a bigger offset, pure current biasing improves the offset (due to having the same current in each phase) but suffers from a lower sensitivity at low to medium-high temperatures. Temperatures may for example range between −40° C. and 125° C. With current biasing the circuit gets optimized at a maximum temperature and any lower temperature will suffer from a sub-optimal sensitivity. If the maximum temperature is for example 150° C. then 125° C. would for example be medium-high. But if 125° C. is the maximum temperature, the circuit can be optimized for 125° C., in which case for example 100° C. would be medium-high. In this last case the current will no longer be constant at a temperature higher than 125° C. The advantages of current biasing disappear at temperatures higher than the trimmed temperature. When applying current biasing, the voltage over the plate is not exactly known, but depends on the electrical resistance of the plate. In the case of voltage biasing, the current flowing through the plate is not exactly known but is determined by the electrical resistance of the plate. This electrical resistance of the Hall plate varies with temperature and stress (e.g. through piezo-resistive effects) and constitutes another source of drift. The sensor resistance also affects the dynamic response of the sensor structure to changes in the applied biasing, as is needed when applying current spinning.

In U.S. Pat. No. 9,638,764 an electronic circuit is provided that can compensate for and correct changes in the sensitivity of a differential output signal generated by a Hall effect element that can result from stresses. The biasing method used in U.S. Pat. No. 9,638,764 combines the voltage biasing and current biasing and offers a quasi-constant voltage over the plates while keeping the current in each phase constant.

US2014/0103921 discloses a circuit and method for biasing a plate-shaped sensor element. The common mode is kept constant over temperature and stress. However, a separate current source is needed and using current biasing reduces the maximum sensitivity at lower temperatures.

In view of the changes in sensitivity caused by stress and temperature differences, there is a need for magnetic field sensors comprising biasing circuitry which allows to compensate for temperature changes and stress changes.

SUMMARY OF THE INVENTION

It is an object of embodiments of the present invention to provide a magnetic field sensor comprising good biasing circuitry and a good method for biasing a magnetic field sensor.

The above objective is accomplished by a method and device according to the present invention.

In a first aspect embodiments of the present invention relate to a bridge sensor. The bridge sensor comprises at least one dummy resistor structure, at least one sensor structure, a first regulator and a second regulator. The first regulator is adapted to apply a predefined bias voltage on bias contacts (Vtop, Vbottom) of the at least one dummy resistor structure and a related voltage on bias contacts of the at least one sensor structure. The related voltage may for example be the predefined bias voltage times a predefined scaling factor. The second regulator is adapted to regulate a common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) between the bias contacts (Vtop, Vbottom) of the at least one dummy resistor structure and on sense contacts (Vn, Vp) of the at least one sensor structure such that the common mode voltage on the at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure is the same as the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure.

It is an advantage of embodiments of the present invention that the common mode voltage of the dummy resistor structure (having the same technology as the sensor structure; e.g. a dummy Hall plate for a Hall sensor) can be regulated to be the same as the common mode voltage of the sensor structures (e.g. sensor plates). By having the same common mode voltage, the resistivity and normalized sensitivity of the sensor structure (e.g. Hall plate) is the same as the resistivity and normalized sensitivity (i.e. sensitivity per unit of bias voltage) of the dummy resistor structure. It is advantageous that this improves the stress performance. This in comparison with a bridge sensor (e.g. Hall sensor) wherein the dummy resistor structure has a significantly different common mode than the sensor structure (e.g. Hall plates). A different common mode voltage results in a difference in resistivity, normalized sensitivity, temperature and stress behavior.

It is an advantage of embodiments of the present invention that a quasi-constant voltage is applied over the sensor structures (e.g. Hall plates) over temperature. With an increased voltage level over the sensor structures an improved noise performance can be obtained. By keeping the voltage level at a quasi-constant level, it is possible to maintain the noise performance for different temperatures. The voltage over the sensor structures may for example be maximized for optimizing the noise performance.

It is an advantage of embodiments of the present invention that the current remains the same within each phase, which minimizes the residual offset of the sensor structures (e.g. hall plates).

In embodiments of the present invention the predefined scaling factor may be equal to one or at least 2 or at least 4 or at least 8. In embodiments of the present invention the at least one dummy resistor structure is made of the same material and/or using a same technology as the at least one sensor structure.

It is an advantage of embodiments of the present invention that resistivity changes due to stress are the same for the dummy resistor structure as for the at least one sensor structure (e.g. Hall plate).

It is an advantage of embodiments of the present invention that normalized sensitivity changes due to stress are the same for the dummy resistor structure as for the at least one sensor structure (e.g. Hall plate).

In embodiments of the present invention the sensor structure comprises switching circuitry adapted for spinning the sense contacts and the bias contacts.

It is an advantage of embodiments of the present invention that the common mode voltage on the at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure is the same as the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure. As the dummy resistor structures are not switched, a stable common mode voltage can be obtained, even when spinning the sense contacts and the bias contacts of the sensor structure. A settling time may be foreseen at the beginning of each phase before measuring the common mode voltage in order to improve the stability of the common mode voltage even more.

It is moreover advantageous that a predefined bias voltage is applied on the bias contacts of the at least one dummy resistor structure and the predefined bias voltage times a predefined scaling factor is applied on the bias contacts of the at least one sensor structure. Thus, a stable current can be achieved through the sensor structure, even when spinning the sense contacts and the bias contacts of the sensor structure.

In embodiments of the present invention the second regulator is adapted to regulate the common mode voltage to a predefined value.

It is an advantage of embodiments of the present invention that the common mode voltage on the at least one intermediate contact of the at least one dummy resistor structure and the common mode voltage on the sense contacts of the at least one sensor structure (e.g. sensor Hall plate) is a stable voltage.

In embodiments of the present invention the first regulator comprises a first operational amplifier, a first transistor connected with a bias contact of the at least one dummy resistor structure for biasing the at least one dummy resistor structure, and a second transistor connected with a bias contact of the at least one sensor structure for biasing the at least one sensor structure, wherein gates of the first transistor and of the second transistor are controlled by an output of the first operational amplifier.

In embodiments of the present invention the second regulator comprises a second operational amplifier, a third transistor connected with a bias contact of the at least one dummy resistor structure to regulate the common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure, and a fourth transistor connected with a bias contact of the of the at least one sensor structure to regulate the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure, wherein gates of the third transistor and of the fourth transistor are controlled by an output of the second operational amplifier.

In embodiments of the present invention the second regulator comprises a second operational amplifier, a third operational amplifier, a third transistor connected with a bias contact of the at least one dummy resistor structure to regulate the common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure, and a fourth transistor connected with a bias contact of the of the at least one sensor structure to regulate the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure, wherein a gate of the third transistor is controlled by an output of the second operational amplifier and wherein a gate of the fourth transistor is controlled by an output of the third operational amplifier.

In embodiments of the present invention the bridge sensor comprising a first average block which is adapted for averaging the voltages on intermediate contacts of the dummy resistor structure and outputting the obtained average and wherein the output of the average block is connected with an input of the second regulator.

It is an advantage of embodiments of the present invention that the output of the common mode voltage on the sense contacts (Vndum, Vpdum) of the at least one dummy resistor structure (e.g. dummy Hall plate) can be obtained using the average block. In embodiments of the present invention the average block may be integrated in the second regulator. More specifically, it may be integrated in the second amplifier. In embodiments of the present invention the common mode voltage is approximately the voltage between the voltage on the bias contacts (i.e. the average of the voltages Vtop and Vbottom). For example, if Vtop is 3V and Vbottom is 1V, the common mode voltage may be approximately 2V. In a typical Hall plate, the common mode voltage may be approximately the average of the top and bottom voltage, whilst smaller than the average (e.g. 1.9V instead of 2V). This may for example be caused by a resistivity of the top-half of the Hall plate which is bigger than the resistivity of the bottom-half.

In embodiments of the present invention the bridge sensor comprises a second average block which is adapted for averaging the voltages on the sense contacts (Vn, Vp) of the at least one sensor Hall plate and for outputting the obtained average and the output of the second average block is connected with an input of the second regulator.

In embodiments of the present invention the output of the second average block may be connected with the input of the third amplifier. The third amplifier thereby controls the gate of the fourth transistor such that the common mode voltage on the sense contacts of the at least one sensor structure is regulated to a predefined voltage. In embodiments of the present invention the second average block may be integrated in the second regulator (e.g. more specifically the third amplifier).

In embodiments of the present invention the predefined scaling factor is an integer larger than one.

It is an advantage of embodiments of the present invention that a smaller current can be flowing through the dummy resistor structure than through the at least one sensor structure. As, in embodiments of the present invention, the dummy resistor structure is not used for measuring the magnetic field a smaller current is allowed.

In embodiments of the present invention the at least one sensor structure is a Hall plate.

In embodiments of the present invention the dummy resistor structure comprises a dummy Hall plate. The Hall plate has two intermediate contacts (Vndum, Vpdum) which are sense contacts of the dummy resistor structure.

In embodiments of the present invention the dummy resistor structure comprises two or more dummy Hall plates.

These may for example be connected in parallel, or in anti-parallel. The bridge sensor may comprise two dummy Hall plates in series, wherein the intermediate contact (Vmid) is the contact in between the first and the second dummy Hall plate.

In embodiments of the present invention the number of sensor structures is at least two.

The number of sensor structures may for example be four or eight.

In embodiments of the present invention the at least one sensor structure is a magnetic sensor structure.

The at least one sensor structure may for example comprise XMR (extremely large magnetoresistance) elements configured in a bridge configuration. The bridge can for example be a bridge of at least 2 XMR elements or for example 4 XMR elements. They may be sensitive to at least one or at least 2 directions of a magnetic field.

In a second aspect embodiments of the present invention relate to a method for biasing a bridge sensor which comprises at least one dummy resistor structure and at least one sensor structure. The method comprises:

applying a predefined bias voltage on bias contacts (Vtop, Vbottom) of the at least one dummy resistor structure and applying a related voltage on bias contacts of the at least one sensor structure,

regulating a common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure and on sense contacts (Vn, Vp) of the at least one sensor structure such that the common mode voltage on the at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure is the same as the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure.

In embodiments of the present invention the related voltage corresponds with the predefined bias voltage times a predefined scaling factor.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic drawing of an exemplary embodiment of the present invention comprising one dummy Hall plate and 4 sensor Hall plates.

FIG. 2 shows a similar bridge sensor as in FIG. 1, wherein the Hall plates have 8 contacts, in accordance with embodiments of the present invention.

FIG. 3 shows an implementation as in FIG. 1 which additionally comprises cascode transistors and spinning and dummy switches, in accordance with embodiments of the present invention.

FIG. 4 shows a similar implementation as FIG. 3 but without the switches, in accordance with embodiments of the present invention.

FIG. 5 shows a similar implementation as FIG. 3 but without the cascode transistors.

FIG. 6 shows a similar implementation as FIG. 5 but without the dummy switches, in accordance with embodiments of the present invention.

FIG. 7 shows a schematic drawing of an exemplary embodiment of the present invention wherein the current through the dummy Hall plate is reduced.

FIG. 8 shows a schematic drawing of an exemplary embodiment of the present invention wherein the common mode of the dummy Hall plate is regulated to the common mode of the sensing Hall plate.

FIG. 9 shows a schematic drawing of a similar implementation as in FIG. 1 except with 2 dummy hall plates in parallel instead of just 1 dummy hall plate.

FIG. 10 shows a schematic drawing of a similar implementation as in FIG. 7 except with 2 dummy hall plates in parallel instead of just 1 dummy hall plate.

FIG. 11 shows a schematic drawing of a similar implementation as in FIG. 8 except with 2 dummy hall plates in parallel instead of just 1 dummy hall plate.

FIG. 12 shows a schematic drawing of a similar implementation as in FIG. 1 except with 2 dummy hall plates in series instead of just 1 dummy hall plate.

FIG. 13 shows a schematic drawing of a similar implementation as in FIG. 7 except with 2 dummy hall plates in series instead of just 1 dummy hall plate.

FIG. 14 shows a schematic drawing of a similar implementation as in FIG. 8 except with 2 dummy hall plates in series instead of just 1 dummy hall plate.

FIG. 15 shows a regulating amplifier for a Hall sensor in accordance with embodiments of the present invention.

FIG. 16 shows a regulating amplifier adapted for averaging two inputs in accordance with embodiments of the present invention.

FIG. 17 shows 4 parallel sensor Hall plates during 1 phase for a Hall sensor in accordance with embodiments of the present invention.

FIG. 18 shows a single dummy Hall plate for a Hall sensor in accordance with embodiments of the present invention.

FIG. 19 shows two dummy Hall plates connected in parallel for a Hall sensor in accordance with embodiments of the present invention.

FIG. 20 shows two dummy Hall plates connected in anti-parallel for a Hall sensor in accordance with embodiments of the present invention.

FIG. 21 shows a Hall plate structure comprising 8 sensing Hall plates, each having 8 contacts, during 1 phase, in accordance with embodiments of the present invention.

FIG. 22 shows four dummy Hall plates, each comprising 8 contacts, connected in parallel, in accordance with embodiments of the present invention.

FIG. 23 shows four dummy Hall plates, each comprising 8 contacts, connected in anti-parallel, in accordance with embodiments of the present invention.

FIG. 24 shows a connection scheme of a dummy Hall plate comprising 8 contacts, in accordance with embodiments of the present invention.

FIG. 25 shows a connection scheme of a single sensor Hall plate comprising 8 contacts, in accordance with embodiments of the present invention.

FIG. 26 shows a schematic drawing of switching circuitry in accordance with embodiments of the present invention.

FIG. 27 shows a spatial spinning scheme, spinning the sense contacts and the bias contacts of the sensor structure, in accordance with embodiments of the present invention.

FIG. 28 shows a temporal spinning scheme, spinning the sense contacts and the bias contacts of the sensor structure, in accordance with embodiments of the present invention.

Any reference signs in the claims shall not be construed as limiting the scope.

In the different drawings, the same reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

In a first aspect embodiments of the present invention relate to a bridge sensor 100. The bridge sensor comprises at least one dummy resistor structure 110 at least one sensor structure 120, a first regulator 130 and a second regulator 140.

The first regulator 130 is adapted to apply a predefined bias voltage on bias contacts Vtop, Vbottom of the at least one dummy resistor structure 110 and to apply a related voltage on bias contacts of the at least one sensor structure 120. The related voltage may for example be the predefined bias voltage times a predefined scaling factor.

The second regulator 140 is adapted to regulate a common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) between the bias contacts (Vtop, Vbottom) of the at least one dummy resistor structure 110 and on sense contacts (Vn, Vp) of the at least one sensor structure 120 such that the common mode voltage on the at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure 110 is the same as the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure.

In embodiments of the present invention the bridge sensor may for example be a resistive sensor or a Hall sensor. In case of a Hall sensor, the sensor structure 120 may be a Hall plate.

In embodiments of the present invention the second regulator 140 is adapted to regulate the common mode voltage to a predefined value.

In a second aspect embodiments of the present invention relate to a method for biasing a bridge sensor. The bridge sensor comprises at least one dummy resistor 110 structure and at least one sensor structure 120.

The method comprises applying a predefined bias voltage on bias contacts (Vtop, Vbottom) of the at least one dummy resistor structure 110 and applying the predefined bias voltage times a predefined scaling factor on bias contacts of the at least one sensor structure 120.

The method moreover comprises regulating a common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure 110 and on sense contacts (Vn, Vp) of the at least one sensor structure 120 such that the common mode voltage on the at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure 110 is the same as the common mode voltage on the sense contacts (Vn, Vp) of the at least one sensor structure.

In case the bridge sensor is a Hall sensor the dummy resistor structure may be a dummy Hall plate similar to the sensor Hall plates (e.g. made of the same material and having the same shape).

In embodiments of the present invention 2 regulators are used to regulate both the bias voltage and the common mode of at least one dummy resistor structure (e.g. Hall plate) and one or more sensor structures (e.g. sensor Hall plates). By doing this the voltage over the dummy resistor structure and over the sensor structures will be fixed over temperature to a quasi-constant voltage and the dummy resistor structure (e.g. Hall plate) will be more similar in performance to the sensor structure (e.g. the sensor Hall plates).

In embodiments of the present invention the first regulator 130 is adapted for regulating the voltage over the dummy resistor structure 110 (e.g. Hall plate) to a quasi-constant bias voltage Vbiasref. It may therefore comprise a first operational amplifier 131 or any other regulator adapted for doing so.

FIG. 1 shows a schematic drawing of an exemplary embodiment of the present invention. In this example there are 4 measuring Hall plates 120 and there is one dummy Hall plate 110. The dummy Hall plate may or may not be present in a magnetic field. In z-mode measurement the dummy Hall plate may for example measure the magnetic field. The voltage present over the dummy Hall plate (Vndum, Vpdum) may change, but the voltages (Vndum, Vpdum) at the terminals are only used to calculate the common mode of the signal. The common mode of (Vndum, Vpdum) will be independent of the magnetic field. In embodiments of the present invention these terminals of the dummy Hall plate are not used for sensing. The common mode of Vndum and Vpdum can be obtained by taking the average of Vndum and Vpdum. This may for example be achieved by an averaging circuitry 144 as symbolically illustrated in FIG. 1. This may for example be achieved by an amplifier of which the positive input is split in two parallel inputs. Instead of having an amplifier with two inputs, a negative input and a positive input, two positive inputs are applied and one negative. Each positive input has only half the gain as the negative one. Vpdum and Vndum are connected to the positive inputs. By doing so the reference is equal to (Vpdum+Vndum)/2.

The dummy Hall plate 110 is preferably centered around the common mode. This is achieved by Vtop. If for example the common mode reference voltage Vcmref is for example taken to be 1.5V, it will guarantee that the center of the Hall plate is 1.5V.

In the example the dummy Hall plate 110 is connected between two transistors 142, 132. In this exemplary embodiment of the present invention the configuration comprising the Hall plate and the transistors is mirrored k times (with k a natural number which is one or greater). Thus, k measurement Hall plates are obtained.

In embodiments of the present invention the second regulator 140 is adapted to regulate a common mode voltage on at least one intermediate contact (Vndum, Vpdum, Vmid) of the at least one dummy resistor structure 110 and on sense contacts (Vn, Vp) of the at least one sensor Hall plate 120. It may therefore comprise a second operational amplifier 141 or any other type of regulator for achieving this. The second operational amplifier 141 is controlled by the common mode voltage and the common mode reference voltage. If, for example, the common mode voltage increases above the common mode reference voltage Vcmref the gate of the third transistor 142 will be closed thereby lowering Vtop and reducing the common mode voltage.

The first operational amplifier 131 is regulating the voltage over the dummy resistive structure, i.e. the voltage difference between Vtop and Vbot. Vbiasref+Vbot is applied to the positive input terminal of the second amplifier and Vtop is applied to the negative input terminal of the first operational amplifier 131. By doing so Vtop−Vbottom equals Vbiasref. The same Vbiasref will be present over the sensor Hall plate 120 and the same common mode will be present over the sensor Hall plate 120.

It is an advantage of embodiments of the present invention that the dummy Hall plate 110 and the sensor Hall plate 120 have the same common mode voltage. Thus, a same resistivity and a same normalized sensitivity of the sensor Hall plate and the dummy Hall plate can be obtained. As the resistivity of the Hall plate is not the same over the full voltage domain due to the bulk source effect, it is advantageous that during operation the Hall plates have the same common mode voltage.

In the exemplary embodiment illustrated in FIG. 1 a first transistor 132 (which in this example is an nMOS transistor) is connected at one side (e.g. the bottom side) of the dummy plate 110. In this exemplary embodiment the output of the first operational amplifier (signal Vout,A) is connected to the gate of the first transistor 132. The source of the first transistor 132 is connected to ground and the drain to one of the contacts of the hall plate 110. In the exemplary embodiment illustrated in FIG. 1 this is the bottom contact with associated signal Vbot. The invention is, however, not limited thereto (the drain may also be connected to another contact).

The dummy hall plate contact Vtop at the opposite side of the contact where the first transistor 132 is connected, is connected to the drain of a third transistor 142 (in this example this is a pMOS transistor, the invention is, however, not limited thereto. The drain of the third transistor 142 is connected to the supply and its gate is driven by a second operational amplifier 142 (signal Vout,B).

In embodiments of the present invention the negative input of the first operational amplifier 131 may be connected to Vtop-Vbot and the positive input to the voltage bias reference level Vbiasref Another way is to connect the negative input to Vtop and the positive input to Vbiasref+Vbot. This is illustrated in FIG. 1. In FIG. 1 the first operational amplifier 131 is adapted for performing the following function:

Vout,A=Ga*(Vbiasref−(Vtop−Vbot)),

with Ga a high gain (f.e. more than 60 dB).

The second operational amplifier 141 is regulating the common mode of the dummy hall plate 110, by regulating the common mode of the sense contacts (Vndum, Vpdum). In FIG. 1 this is done by regulating the average of the voltages of the remaining contacts (sense contacts) to a predefined value which is the reference level Vcmref.

A first average block 144 takes as inputs the 2 sense contacts of the dummy Hall plate 110 (Vpdum and Vndum) and has as output the average (and thus common mode) of these signals (Vcmdum). The output is connected to the positive input of the second operational amplifier 141 and the reference level (Vcmref) is connected to the negative input. It is not necessary to have a separate average block 144 as the combined functionality of the average block 144 and the second operational amplifier 141 can be done by a modified regulator with 2 positive inputs (Vpdum and Vndum) and 1 negative input with double weight (Vcmref). An example of such a modified regulator is illustrated in FIG. 16. In embodiments of the present invention the output of the second operational amplifier 141 performs the following function:

Vout,B=Gb*((Vpdum+Vndum)/2−Vcmref)=Gb*(Vcmdum−Vcmref),

with Gb a high gain (f.e. more than 60 dB). Vcmdum thereby corresponds with (Vpdum+Vndum)/2, i.e. the average.

In embodiments of the present invention the current flowing in the dummy Hall plate 110 (or a multiple of the current) is mirrored to the at least one sensor Hall plate 120.

In the exemplary embodiment illustrated in FIG. 1 the signals Vout,A and Vout,B of the first operational amplifier 131 and the second operational amplifier 141 are used to drive a second transistor 133 and a fourth transistor 143 respectively. The second transistor 133 is connected between a bias contact of the at least one Hall plate 120 and the ground and the fourth transistor 143 is connected between another bias contact of the at least one Hall plate 120 and the supply voltage. There may also be switches present between any of the transistors (133, 143) and the at least one Hall plate 120 (see for example FIG. 3, FIG. 5 and FIG. 6). In this exemplary embodiment of the present invention the second 133 and fourth 143 transistor driving the sensor Hall plates are n times bigger than the first transistors 132 and the third transistor 142 respectively. The size may thereby be measured as the W/L ratio. They are connected with their drains to opposite contacts of n parallel hall plates (the n sensor hall plates) in a manner similar to transistors 132, 142 to opposite contacts of the dummy Hall plate transistor. n is the mirroring factor and can be any integer bigger than or equal to 1, although practical limitations will limit the maximum mirroring factor. As the sensing Hall plates are n, with n a positive integer (e.g. 4), in parallel their resistance is n times lower than that of a dummy Hall plate, if the dummy Hall plate is similar to the sensing Hall plates.

In this implementation the sensor Hall plates 120 biasing voltage Vbias will be the same as the dummy hall plate 110 biasing voltage Vbiasdum (and equal to the reference Vbiasref), also the common mode voltage Vcm of the sensor plates 120 will be the same as the common mode voltage Vcmdum of the dummy plate 110 (and equal to the reference Vcmref). As such there will be a better matching between the dummy plate and the sensor plates compared to the prior art.

The idea of the implementation illustrated in FIG. 7 is to save current on the dummy Hall plate 110 as this Hall plate is not used for sensing. Only a quarter of the current is applied in the dummy Hall plate (Vbiasref/4). The Hall sensor is configured such that a factor of 1:16 is present between the current through the dummy Hall plate 110 and the current through the sensor Hall plates 120 (in the example there are four sensor Hall plates).

In this example an extra common mode regulator (comprising a third operational amplifier 145 and a fourth transistor 143) is required for the measuring Hall plates to generate the common mode of the measuring Hall plates separately. Since in this example the current through and voltage over the measuring Hall plates is different than the current through and voltage over the dummy resistive structure, an extra regulator is needed to regulate the common mode voltage of the measuring Hall plates separately. The disadvantage of this extra amplifier is that this will increase the total current consumption of the Hall device when the current consumption of this extra amplifier is bigger than the decrease in current in dummy Hall plate 110.

In FIG. 1 the dummy resistor structure 110 and the sensor structure are Hall plate structures with 4 contact Hall plates. For these Hall plates one pair of the contacts may be used as a bias contact pair and one pair of the contacts may be used as a sense contact pair. The number of contacts of the contact Hall plates is, however, not limited to 4. In another exemplary embodiment of the present invention this number may for example be 8. Such an example is shown in FIG. 2. An exemplary biasing and readout scheme for an 8 contact single dummy Hall plate is shown in FIG. 24. An exemplary biasing and readout scheme for an 8 contact single sensor Hall plate is shown in FIG. 25.

In embodiments of the present invention the transistors for driving the current through the at least one dummy Hall plate and/or through the at/least one sensor Hall plate may be configured in a cascode configuration. See for example FIG. 4 with bias transistor 134 in cascode with the first transistor 132 and electrically connected with the bottom node of the dummy resistor structure 110, and with bias transistor 136 in cascode with the third transistor 142 and electrically connected with the top node of the dummy resistor structure 110. Similarly, bias transistors 135 and 137 are connected with the top and bottom nodes of the sensor structure 120.

FIG. 3 also shows two switches 151, and 152 connected to the top and bottom node of the dummy resistor structure and switching circuitry comprising switches 161, 162, 163, 164 for spinning the sense contacts and the bias contacts of the sensor structure 120. These switches and spinning schemes implemented using these switches are further illustrated in FIGS. 26 to 28. These switches are not strictly required. An exemplary embodiment of the present invention may for example be like the configuration in FIG. 3 without the switches (with the bias transistors directly connected to the top and bottom nodes; this is illustrated in FIG. 4). The switches 151, and 152 provide a switch resistance similar to switches 161 and 163. These switches 151, and 152 are in-fact dummy-switches not because they are connected to the dummy plates but because they don't need any switch-functionality in the context of the present invention.

In yet another exemplary embodiment, illustrated in FIG. 5, of the present invention the additional cascode transistors 134, 135, 136, 137 are not present but the switches 151, 152, 161, 162, 163, 164 are.

In FIG. 6, only the spinning switches 161, 162, 163, 164, for spinning the sense contacts and the bias contacts of the sensor structure 120, are present.

This, i.e. the cascode configuration, is especially advantageous for driving the current to assure correct mirroring of the current. In case of only 1 nMOS transistor there would be a larger difference between the drain-source voltages of the dummy plate nMOS and the sensor plate nMOS.

In embodiments of the present invention the cascode transistors may also serve as switches of the hall plate switch matrix to minimize to total amount of transistors needed.

In the exemplary embodiment illustrated in FIG. 7 the biasing voltage Vbiasdum of the dummy plate is m times smaller than the biasing voltage Vbias of the sensor plates wherein m is the predefined scaling factor (this may for example be 2, in the illustrated exemplary embodiment m=4). This will result in dummy hall plate current which is also m times smaller than the current flowing through 1 of the n parallel sensor hall plates or m×n times smaller than the total sensor hall plate current (n is equal to 4 in the exemplary embodiment illustrated in FIG. 7). The goal was to save current consumption however an extra regulator (e.g. the third operational amplifier 145) is needed to regulate the common mode of the sensor hall plates separately. Nevertheless, this implementation is a viable solution as well.

Instead of connecting the gate of the fourth transistor 143 to Vout,B, it must be connected to Vout,C, the output of third operational amplifier 145 which works in a very similar fashion as regulator B, but connects Vcm instead of Vcmdum to its positive input. Vcm is the average of Vp and Vn. It is not necessary to have a seperate average block 146 as the combined functionality of the average block and regulator C can be done by a modified regulator with 2 positive inputs (Vp and Vn) and 1 negative input with double weight (Vcmref) such as for example illustrated in FIG. 16. It is important that the total regulator performs the following function:

Vout,C=Gc*((Vp+Vn)/2−Vcmref)=Gc*(Vcm−Vcmref),

with Gc a high gain (f.e. more than 60 dB).

The fourth transistor 143 and the second transistor 133 are now m×n times bigger than the third transistor 142 and and the first transistor 132 respectively and the intended transfer function of the first operational amplifier 131 is now:

Vout,A=Ga*(Vbiasref/m−(Vtop−Vbot)),

with Ga a high gain (f.e. more than 60 dB). This is because the goal is to regulate Vbiasdum to Vbiasref/4 so that Vbias is still equal to Vbiasref.

In the example illustrated in FIG. 7, Hall plates with 4 contacts are used. The invention is, however, not limited thereto and also Hall plates with more than 4 contacts such as for example 8 contacts may be used such as for example is done in FIG. 2.

In the exemplary embodiment illustrated in FIG. 8, rather that regulating the common mode of the dummy Hall plate and the common mode of the measuring Hall plate separately, the common mode of the dummy Hall plate is regulated to the common mode of the sensing Hall plate. In this implementation the common mode may still be varying and is not fixed to Vcmref.

The exemplary embodiment illustrated in FIG. 8 is a variant of the embodiment illustrated in FIG. 7 where the fourth transistor 143 is removed. The top contacts of the sensor hall plates 120 are now connected directly to Vdd (Hall plates with 4 contacts or with more contacts, such as for example with 8 contacts may be used). Regulator B (i.e. the second operational amplifier 141) now regulates the dummy plate common mode Vcmdum to the common mode voltage of the sensor hall plates Vcm instead of a predefined reference level Vcmref. This is done because Vcm can no longer be regulated and it is important to have the same common mode for the sensor plate and the dummy plate. The common mode in this case will be approximately equal to VDD−Vbiasref/2 and will remain constant (if VDD and Vbiasref remains constant). The common mode voltage is not exactly equal to VDD−Vbiasref/2 due to the bulk source effect, which causes the resistivity of the hall structure to change over applied voltage. The negative input of regulator B (i.e. the second operational amplifier 141) is now connected to Vcm (average of Vp and Vn) instead of a reference Vcmref.

It is not necessary to have a separate average block 144, 146 as the combined functionality of the 2 average blocks and regulator B can be done by a modified regulator with 2 positive inputs (Vpdum and Vndum) and 2 negative inputs (Vp and Vn). It is important that the total regulator performs the following function:

Vout,B=Gb*((Vpdum+Vndum)−(Vp+Vn))/2=Gb*(Vcmdum−Vcm),

with Gb a high gain (f.e. more than 60 dB).

The implementations illustrated in FIGS. 9 to 14 are implementations with 2 dummy hall plates, where the current in 1 of the 2 plates flows with a 90-degree orientation compared to the current in the other plate. In the examples illustrated in these figures the Hall plates are Hall plates with 4 contacts. Hall plates with more than 4 contacts, such as for example 8 contacts are also possible.

The implementation illustrated in FIG. 9 is similar to the implementation in FIG. 1 except with 2 dummy hall plates 110 in parallel (or anti-parallel) instead of just 1 dummy hall plate.

The implementation illustrated in FIG. 10 is similar to the implementation illustrated FIG. 7 except with 2 dummy hail plates 110 in parallel (or anti-parallel) instead of just 1 dummy hall plate.

The implementation illustrated in FIG. 11 is similar to the implementation illustrated in FIG. 8 except with 2 dummy hall plates 110 in parallel (or anti-parallel) instead of just 1 dummy hall plate.

The implementation illustrated in FIG. 12 is similar to implementation illustrated in FIG. 1 except with 2 dummy hall plates 110 in series instead of just 1 dummy hall plate. The intermediate contact is between the two dummy Hall plates. During operation the voltage at this contact is Vmid. Vmid is used as positive input for amplifier 141 instead of Vcmdum.

The implementation illustrated in FIG. 13 is similar to the implementation illustrated in FIG. 7 except with 2 dummy hall plates 110 in series instead of just 1 dummy hall plate.

The implementation illustrated in FIG. 14 is similar to the implementation illustrated in FIG. 8 except with 2 dummy hall plates in series instead of just 1 dummy hall plate.

In the implementations illustrated in FIGS. 9 to 11 the dummy plates are placed in parallel (or anti-parallel) and in the implementations illustrates in FIGS. 12 to 14 the plates are put in series.

It is an advantage of embodiments of the present invention that 2 dummy plates are used in a 90 degree orientation instead of one, because 2 dummy plates in a 90 degree orientation cope better with stresses because of the 90 degree orientation.

In embodiments of the present invention also 4 dummy plates (or any multiple of 2) may be used.

In embodiments of the present invention all or some of the nMOS and pMOS transistors may be swapped. The common mode regulation can be done by a regulator at the bottom and the Vbias regulation by a regulator connected to the top of the Hall plates. This will result in the same functionality.

As already clear from the exemplary embodiments above, in embodiments of the present invention the dummy resistor structure may be a dummy hall plate.

In embodiments of the present invention the dummy resistor structure may be a resistor. This resistor is preferably made of the same material as the hall plate. It is advantageous that this dummy resistor structure behaves like the sensor hall plates (e.g. with respect to resistivity change over temperature and with respect to behavior to stress). Also, in the exemplary embodiments cited above another dummy resistor structure may be used than a dummy Hall plate.

In the exemplary embodiments illustrated in FIG. 1 to FIG. 14 the average block 144 for the common mode regulation is drawn as an entity separate from the second regulator 140. This is, however, not strictly required. In embodiments of the present invention the average block 144 may be integrated in the regulating amplifier 141 of the second regulator. A simple amplifier (illustrated in FIG. 15) can be modified to the amplifier illustrated in FIG. 16.

The second regulator now has 2 positive and 2 negative inputs, the positive inputs are Vpdum and Vndum and the negative inputs are both connected to Vcmref. The amplifier is reacting on the sum (twice the common mode) of 2 inputs.

For the implementations illustrated in FIGS. 1 to 6, 9 and 12 it is also possible to sense the common mode of the sensing hall plates (by averaging Vp and Vn) and use this voltage Vcm as positive input of the second regulator. In this case the common mode of the sensing hall plates is regulated instead of the dummy resistive structure. In some embodiments this might be a preferred solution to simplify the design.

FIG. 17 shows 4 parallel sensing hall plates during 1 phase. The direction of the currents can be different as long as all 4 directions are done in an equal amount. It is also possible to use only 2 of the directions. In this last case it is important that the 2 directions have a 90 degree angle between them and not 180 degrees. For hall plates with more than 4 contacts (such as for example illustrated in FIG. 2) more than 4 directions are possible. In any of the FIGS. 3 to 14 the four contact Hall plate may be replaced by an 8 contact Hall plate.

It is not necessary that the 4 hall plates from for example FIG. 17 are placed in a square (similar with the 8 contact plates, each with 8 contacts of FIG. 21). Instead they can be placed on a line or indeed any location.

In each phase the current direction for each plate changes but is is important that the same directions are used in total (for all plates)

In embodiments of the present invention the plates may be placed fully in parallel. This can for example be applied in the case where each plate sees the same field.

In embodiments of the present invention where f.e. an integrated magnetic concentrator (IMC) is used, the 2 Hall plates on the right could see a field with opposite sign as the 2 Hall plates on the left. In that case the Hall plates are preferably put in an anti-parallel configuration. Which means that sensing terminals 1 of the left plates should be connected to sensing terminals 2 of the right plates.

FIG. 18 shows a single dummy Hall plate with the biasing contacts (voltages Vtop, Vbot) and the sensing contacts (voltages Vndum, Vpdum).

In case of 2 dummy resistor structures (e.g. 2 dummy Hall plates), they can either be placed fully in parallel such as illustrated in FIG. 19 or in anti-parallel such as illustrated in FIG. 20. In FIG. 19 the current in the 2 Hall plates flows in 2 directions with 90° difference. Their sensing nodes are shorted to the corresponding sensing nodes of the other plate. In FIG. 20 the current in the 2 Hall plates flows in 2 directions with 90° difference. Their sensing nodes are shorted to the opposite sensing nodes of the other plate.

The subsequent averaging of Vpdum and Vndum (for Vcmdum) is recommended in both cases however it might not be needed in the case of anti-parallel since in the case of anti-parallel a positive terminal is shortened with a negative terminal causing the nets automatically to be, in an ideal world, the common mode and thus independent of the magnetic field.

FIG. 22 shows a configuration of 4 dummy Hall plates (each with 8 contacts) connected in a parallel configuration. FIG. 23 shows a configuration of 4 dummy Hall plates (each with 8 contacts) connected in an anti-parallel configuration.

In embodiments of the present invention phase spinning may be applied on the sensor Hall plates. Extra spinning switches are needed in this case (see for example the switches 161, 162, 163, and 164 connected with the contacts of the sensor structure in FIGS. 3, 5 and 6). FIG. 26 shows a more detailed schematic drawing of the switching circuitry comprising the switches 161 (connected to Vtop), 162 (connected to Vp), 163 (connected to Vbot), 164 (connected to Vn). Using this switching circuitry, it is possible to spin the sensor structure such that the contacts of the sensor structure are alternatingly bias contacts and sense contacts. In FIG. 27 is illustrated how spatial spinning can be implemented using such switching circuitry, and in FIG. 28 is illustrated how temporal spinning can be implemented using such switching circuitry.

Where in embodiments of the present invention reference is made to the normalized sensitivity of a sensor structure (e.g. a Hall plate), reference is made to the sensitivity of the sensor structure divided by the bias voltage of the sensor structure.

A hall plate, for example, has a certain sensitivity S expressed in mV per Tesla [mV/T]. The Hall plate sensitivity is approximately proportional to the bias voltage Vbias. Meaning that when f.e. Vbias=2V, the sensitivity S is roughly 2 times higher than when Vbias=1V. That is why the normalized sensitivity Sv is used. This is the sensitivity divided by the bias voltage and is expressed in mV per Volt per Tesla (mV/(VT)]. This is roughly constant over Vbias but not fully due to the bulk source effect.

It is normal that a dummy plate has a lower sensitivity as the sensor plate if the voltage over the dummy plate is significantly lower than the bias voltage of the sensor plates. If Vbiasdum is 4× smaller than Vbias, then the sensitivity of the dummy plates is roughly 4× lower than the sensitivity of the sensor plates.

However, the normalized sensitivity Sv is roughly constant. And when the dummy plates and the sensor plates have the same common mode then Sv is the same. This is not the case when the CM is different.

BRIDGE SENSOR WITH DUMMY RESISTOR STRUCTURE

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