Claims
- 1. An apparatus for aligning the phase of digital data with respect to a single phase clock signal, comprising:
- input means for receiving the digital data desired to be aligned;
- M delay means coupled to the input means for providing incremental M delays to the received digital data;
- P registers of N stages each where P=M+1, wherein the P registers are coupled to the M delay means, and wherein at least first stages of each of the P registers are responsive to the signal phase clock signal, and wherein the data are serially coupled through the M delay means and to the P registers arranged so that a first of the P registers has its input coupled to an input of a first of the M delay means, a second register has its input coupled to an input of a second of the M delay means, continuing until a (P-1).sup.th register has its input coupled to an input of an M.sup.th delay means and a P.sup.th register has its input coupled to an output of the M.sup.th delay means;
- means for comprising signals derived from the P registers in adjacent pairs separated at their inputs by one of the M delay means and the P.sup.th register being compared with a signal from the first register, to provide a disagreement signal indicating during which of the delays provided by the M delay means a data transition has occurred; and
- logic means for receiving the disagreement signal and selecting one of at least two data outputs derived from outputs of at least two of the P registers as the aligned data output.
- 2. An apparatus as claimed in claim 1, wherein the at least two of the P registers are separated at their inputs by at least one incremental delay.
- 3. An apparatus as claimed in claim 1, wherein the at least two of the P registers are separated at their inputs by at least two incremental delays.
- 4. An apparatus as claimed in claim 1, wherein M.gtoreq.2 and N.gtoreq.1.
- 5. An apparatus as claimed in claim 4, wherein M.gtoreq.3 and N.gtoreq.3.
- 6. An apparatus as claimed in claim 5, wherein the at least two of the P registers are the first and the third register.
- 7. An apparatus for aligning the phase of digital data with respect to the phase of a clock signal, comprising:
- input means for receiving the digital data desired to be aligned;
- M delay means providing incremental M delays to the received digital data, P registers of N stages each wherein P=M+1, wherein the data are serially coupled through the M delay means and to the P registers arranged so that a first of the P registers has its input coupled to an input of a first of the M delay means, a second register has its input coupled to an input of a second of the M delay means, continuing until a (P-1).sup.th register has its input coupled to an input of an M.sup.th delay means and a P.sup.th register has its input coupled to an output of the M.sup.th delay means;
- means for comparing signals derived from the P registers in adjacent pairs separated at their inputs by one of the M delay means and the P.sup.th register being compared with a signal from the first register, to provide a disagreement signal indicating during which of the delays provided by the M delay means a data transition has occurred;
- logic means for receiving the disagreement signal and selecting one of at least two data outputs derived from outputs of at least two of the P registers as the aligned data output; and
- wherein M=3, and P=4 and there are P means for comparing the signals derived from the registers in adjacent pairs, and wherein the logic means changes the selecting of one of two data outputs (D or DD) from one to the other based on whether inputs of the first through fourth means for comparing the signals are the same (yes) or not (no), where W, X, Y, Z represent binary outputs, respectively, of the first through fourth means for comparing, as follows:
- ______________________________________ Which Output Change OutputComparing Inputs D/DD Currently D/DDmeans Same? Selected? yes/no?______________________________________first yes (W=0) doesn't no matter(W) no (W=1) D yes; select later data no (W=1) DD nosecond yes (X=0) doesn't no matter(X) no (X=1) D no no (X=1) DD yes; select earlier datathird yes (Y=0) doesn't no matter(Y) no (Y=1) D no no (Y=1) DD yes; select later datafourth yes (Z=0) doesn't no matter(Z) no (Z=1) D yes; select earlier data no (Z=1) DD no______________________________________
- 8. An apparatus as claimed in claim 1, wherein M=2 and P=3 and data outputs are derived from the P registers, and further comprising P means for temporarily storing the data outputs from the P registers, and wherein the logic means selects as the aligned data output, data from a P.sub.i means for temporarily storing the data outputs corresponding to a P.sub.i register.
- 9. An apparatus for aligning the phase of a digital signal with respect to the phase of a signal phase clock signal, comprising:
- edge detector means for receiving an input digital signal and the single phase clock signal and providing first and second output digital signals related to the input digital signal at times determined by the signal phase clock signal, and for further providing one or more output disagreement signals indicating whether a transition of the input digital signal and a corresponding transition of a replica of the input digital signal delayed by a second predetermined amount occur in time so as to bracket a transition of the single phase clock signal;
- control logic means for receiving the disagreement signals and providing an output selection signal based thereon; and
- means driven by the single phase clock signal for temporarily storing the first and second output digital signals received from the edge detector means and, under control of the selection signal from the control logic means, providing delayed versions of either the first or second output digital signals as the phase aligned output digital signal.
- 10. An apparatus as claimed in claim 9, wherein the selection signal selects as the phase aligned output digital signal, the one of the first or second output digital signals whose transition occurs furthest in time from a corresponding transition of the single phase clock signal.
- 11. A method for aligning the phase of digital data with respect to the phase of a clock signal, comprising steps of:
- providing input means for receiving the digital data desired to be aligned;
- passing the received digital data sequentially through M incremental delays D.sub.1, D.sub.2 . . . D.sub.M-1, D.sub.M, and to P registers of N stages each where P=M+1 arranged so that a first of the P registers receives the data without any of the M incremental delays, a second register receives the data after a first delay increment D.sub.1, and continuing until a (P-1).sup.th register receives the data after delay increment D.sub.M- 1 and a P.sup.th register receives the data after delay increment D.sub.M ;
- operating the P registers with a single phase clock signal;
- comparing signals derived from the P registers in adjacent pairs which are separated at their inputs by successive delay increments D.sub.1, D.sub.2 . . . D.sub.M-1, D.sub.M and with the P.sup.th register being compared with a signal from the first register, to provide a disagreement signal indicating during which of M+1 time increments a data transition has occurred; and
- selecting one of two data outputs derived from outputs of two of the P registers as aligned output data.
- 12. A method as claimed in claim 11, wherein the step of selecting one of two of the P registers comprises selecting from registers separated at their inputs by at least one incremental delay.
- 13. A method as claimed in claim 12, wherein the step of selecting one of two of the P registers comprises selecting from registers separated at their inputs by at least two incremental delays.
- 14. A method as claimed in claim 11, wherein the passing step comprises passing the data through M incremental delays where M.gtoreq.2 and N stage registers where N.gtoreq.1.
- 15. A method as claimed in claim 11, wherein the passing step comprises passing the data through M incremental delays where M.gtoreq.3 and N stage registers where N.gtoreq.3.
- 16. A method as claimed in claim 11, wherein the step of selecting one of two of the P registers comprises selecting from a first and third registers.
- 17. A method as claimed in claim 11, wherein M=2.
- 18. A method for aligning the phase of input digital data with respect to a clock signal, comprising steps of;
- receiving the input digital data;
- passing the received digital data to an N-stage first shift register and to a first delay means having a predetermined first delay and an output;
- passing data delayed by the first delay to a second shift register and to a second delay means having a predetermined second delay and an output;
- passing the data delayed by the second delay to a third shift register and to a third delay means having a predetermined third delay and an output;
- passing the data delayed by the third delay to a fourth shift register;
- clocking the received digital data and the received and delayed digital data through first stages of the respective shift registers in response to a single phase clock signal;
- identifying which of paired outputs of (i) the first and second shift registers, (ii) the second and third shift registers, (iii) the third and fourth shift registers and (iv) the fourth shift register and an output of the N-1 stage of the first shift register, is different; and then
- selecting as aligned digital data output digital data obtained from the first shift register or another shift register whose output is not different than an adjacent shift register.
- 19. A method as claimed in claim 18, wherein N.gtoreq.2.
- 20. A method as claimed in claim 18, wherein the steps of passing the data to shift registers comprises passing to N-stage shift registers, wherein N.gtoreq.3.
- 21. A method for aligning the phase of input digital data with respect to a single clock signal, comprising steps of:
- providing the input data;
- passing the input data through M.gtoreq.2 delays D.sub.1, . . . D.sub.M ;
- deriving at least two output data streams, one from input data not passing through the M delays and at least another from input data passed through one or more of the M delays, the at least two output data streams being temporarily stored in a corresponding number of output registers coupled by a multiplexer to a data output port; and
- using the single clock signal, selecting among temporarily stored output data streams for delivery to the data output port according to a rule determined by a relative position of a current data transition TR on a phase space representation having M+1 sectors D.sub.1, . . . D.sub.M+1, the temporarily stored output data streams being identified on the phase space representation at boundaries of the M+1 sectors according to which of the temporarily stored output data streams they derive from, wherein the rule comprises:
- (i) determining which output data stream is currently selected;
- (ii) if a currently selected output data stream does not form a boundary of a phase space sector containing data transition TR, do nothing; or
- (iii) if the currently selected output data stream forms a boundary of a phase space sector containing data transition TR, then determine which rotational direction around a phase circle one must move in order to go from a current output data stream location to another output data stream location which does not form a boundary of a phase space sector containing the data transition TR without crossing data transition TR; and
- (iv) if rotation is in a first direction, select earlier data from a temporarily stored another output data stream for delivery to the data output port; or
- (v) if the rotation is in a second opposite rotational direction, select later data from the temporarily stored another output data stream for delivery to the data output port.
Parent Case Info
This application is a continuation of prior application Ser. No. 07/694,175, filed May 1, 1991 now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0168330 |
Jan 1986 |
FRX |
Non-Patent Literature Citations (1)
Entry |
"A 45-Mbit/s CMOS VLSI Digital Phase Aligner", by Rober R. Cordell, IEEE Journal of Solid-State Circuit, vol. 23, No. 2, Apr. 1988 pp. 323-328. |
Continuations (1)
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Number |
Date |
Country |
Parent |
694175 |
May 1991 |
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