Buffer circuit with differential structure for measurement of capacitive charges

Abstract

In a buffer with an operational amplifier having two inputs and two outputs and two feedback capacitances are inserted two other capacitances which in the measurement stage are switched in parallel to the feedback ones with opposite sign in such a manner as to cancel out the effects on the output voltage signal.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a buffer circuit with differential structure for the measurement of capacitive charges.

In many electronic systems it is required to convert a capacitive charge into a corresponding voltage signal through a low-impedance circuit, usually called "buffer".

"Single-ended", i.e. nondifferential, circuits are known which perform said function but they tend to be affected by disturbances in the power supply and consequently to give quite imprecise and unsteady output signals.

Also known are reversed differential circuits which however require zeroing or resetting between one operation and the next. This complicates both the structure and the operation of said circuits.

SUMMARY OF THE INVENTION

The object of the present invention is to achieve a buffer circuit with differential structure which in a structurally and functionally simple manner would allow conversion of a capacitive charge into a steady, precise signal free of every kind of disturbance.

In accordance with the invention said object is achieved by means of a buffer circuit comprising an operational amplifier with two inputs, two outputs and a pair of feedback capacitances between said outputs and the corresponding inputs characterized in that it includes another pair of capacitances the same as said feedback capacitances and commutating devices for connecting alternately each of said other capacitances between a respective amplifier output and a polarization potential or between said amplifier output and the input corresponding to the other output.

BRIEF DESCRIPTION OF THE DRAWING

An example of a practical embodiment of the buffer circuit according to the invention is illustrated for greater clarity in the only FIGURE given in the annexed drawing which shows the circuit diagram thereof.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the drawing, B indicates a buffer circuit including an operational amplifier A equipped with two reversed inputs I.sub.1 and I.sub.2 and two outputs U.sub.1 and U.sub.2 as well as feedback capacitances (the same) C.sub.1 and C.sub.2 connecting the outputs U.sub.1 and U.sub.2 with their repective inputs I.sub.1 and I.sub.2.

The output U.sub.1 may be connected to an input polarization potential V.sub.P2, e.g. to earth, or alternatively to the input I.sub.2 by means of a capacitance C.sub.4 as a function of the state of a commutator S.sub.2 while the output U.sub.2 may be alternatively connected to an input polarization potential V.sub.P1 (the same as V.sub.P2) or to the input I.sub.1 by means of a capacitance C.sub.3 (the same as C.sub.2) as a function of the state of a commutator S.sub.1 synchronized with S.sub.2 or integral with same.

To employ a buffer circuit for the measurement of a capacitive charge such as the one stored in a capacitor C.sub.5 and identical capacitor C.sub.6 after the passage of a current between an input with potential V.sub.i and respectively -V.sub.i and a terminal with potential V.sub.B1 =V.sub.B2 =V.sub.P1 =V.sub.P2, two more pairs of switches S.sub.3, S.sub.4 and S.sub.5, S.sub.6 are provided and synchronized with S.sub.1, S.sub.2 or are integral with it.

In a first stage of operation all the switches S.sub.1 -S.sub.6 are in the position illustrated in a continuous row in the drawing and consequently the capacitors C.sub.5 and C.sub.6 are charged at voltage V.sub.i and -V.sub.i respectively while the capacitors C.sub.1 and C.sub.2 together with C.sub.3 and C.sub.4 hold steady the output voltage V.sub.u and -V.sub.u previously formed at the terminals U.sub.1 and U.sub.2.

In a second stage of operation all the switches S.sub.1 -S.sub.6 are moved to the position illustrated in dot and dash lines so that the capacitors C.sub.5 and C.sub.6, which are now charged at potentials V.sub.i and -V.sub.i, are connected to the buffer circuit B and the capacitors C.sub.4 and C.sub.3 inject an equal charge of opposite sign to the one accumulated into capacitors C.sub.2 and C.sub.1. The result is that voltage signals V.sub.u, .times.V.sub.u are stabilized at the outputs U.sub.1 and U.sub.2, which reflect the charge of the capacitors C.sub.5, C.sub.6, i.e. they are the same as V.sub.i, -V.sub.i.

The precision of the output signals is also ensured by the capacitors C.sub.3 and C.sub.4 which, by injecting an equal charge of opposite sign to the one accumulated in the capacitors C.sub.1 and C.sub.2, cancels out their effects and in particular the phenomenon of division of the charge compared with C.sub.5 and C.sub.6 due to the presence of C.sub.1 and C.sub.2 and to the voltage memorized by them previously, which otherwise would tend to give an output signal not corresponding to the charge of the capacitor being measured. In this case the capacitor C.sub.5, C.sub.6 is connected to the operational amplifier A without any other comparison capacitance so that the output signal is steady, precise and unaffected by the previous operation condition.

It should also be noted that cancellation of the capacitances C.sub.1 and C.sub.2 by C.sub.3 and C.sub.4 allows in the second aforementioned stage connection to the positive input I.sub.1 of one or more capacitors C.sub.7 and to the negative input I.sub.2 one or more capacitors C.sub.8 connected to their respective generators V.sub.x and -V.sub.x each time it is desired to amplify these signals by a certain factor K=-C.sub.7 /C.sub.1 (C.sub.7 =C.sub.8).

This circuit therefore operates simultaneously as a buffer for certain signals and as an amplifier for other signals regardless of their number.

Claims

1. Buffer circuit with differential structure for measurement of capacitive charges comprising an operational amplifier with two inputs, two outputs and a pair of feedback capacitances between said outputs and the corresponding inputs characterized in that it comprises another pair of capacitances the same as said feedback capacitances and commutating devices for connecting alternatively each of said other capacitances between a respective output of the amplifier and a polarization potential or between said amplifier output and the input corresponding to the other output.

2. Buffer circuit according to claim 1 characterized in that it comprises other commutating devices synchronized with the abovementioned ones for connection of a capacitance being measured in parallel with said feedback capacitance simultaneously with connection of said other capacitances between said amplifier output and the input corresponding to the other output.

3. Buffer circuit according to claim 1 characterized in that said polarization potential is equal to the amplifier input polarization potential.