Claims
- 1. A self-referenced timing system having a built-in shutdown mechanism for memory access operations, comprising:wordline control circuitry further including an address decode block operable to generate a wordline start (WLS) signal, a reference cell portion for operating responsive to said WLS signal, a wordline generator block coupled to said reference cell portion for generating a wordline (WL) signal with respect to a memory access operation, and a wordline shutdown feedback block operable to generate a wordline end (WLE) signal that feeds back to said reference cell portion, wherein said reference cell portion is used for controlling the timing of said memory access operation.
- 2. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said reference cell portion is coupled to a bitline start (BLS) control circuit and a bitline end (BLE) control circuit, each operating to provide timing control with respect to said memory access operation.
- 3. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 2, wherein said BLS control circuit includes a BLS read control block.
- 4. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 3, wherein said BLS control circuit includes a BLS write control block.
- 5. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 4, wherein said BLE control circuit includes a BLE read control block.
- 6. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 5, wherein said BLE control circuit includes a BLE write control block.
- 7. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 2, wherein said reference cell portion is disposed within a row decoder of a memory circuit.
- 8. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 7, wherein said BLS control circuit and said BLE control circuit are integrated into a control logic block associated with said memory circuit.
- 9. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said reference cell portion includes a pair of cross-coupled inverters disposed between a pair of access transistors, said cross-coupled inverters operating to support a pair of QT and QB data nodes operable to be accessed by said access transistors.
- 10. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 9, wherein said QB node is operable to drive said wordline generator circuit coupled to said reference cell portion.
- 11. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said memory access operation is effectuated in a static random access memory (SRAM) device.
- 12. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said memory access operation is effectuated in an electrically programmable read-only memory (EPROM) device.
- 13. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said reference cell portion is disposed in proximity with said address decode block and said wordline generator block.
- 14. The self-referenced timing system having a built-in shutdown mechanism for memory access operations as set forth in claim 1, wherein said reference cell portion is provided for each WL of a memory circuit.
- 15. A self-referenced timing system for memory access operations, comprising:means for selecting a particular wordline in a memory circuit for an access operation; and means for deselecting said particular wordline responsive to a shutdown feedback signal derived from said particular wordline.
- 16. The self-referenced timing system for memory access operations as set forth in claim 15, wherein said means for selecting a particular wordline and means for deselecting said particular wordline operate in conjunction with a reference cell portion responsive to a wordline start (WLS) signal and a wordline end (WLE) signal generated thereby.
- 17. The self-referenced timing system for memory access operations as set forth in claim 16, wherein said reference cell portion is coupled to a bitline start (BLS) control circuit and a bitline end (BLE) control circuit, each operating to provide timing control with respect to said memory access operation.
- 18. The self-referenced timing system for memory access operations as set forth in claim 17, wherein said reference cell portion is disposed within a row decoder of said memory circuit.
- 19. The self-referenced timing system for memory access operations as set forth in claim 17, wherein said reference cell portion is disposed in an array portion of said memory circuit.
- 20. A self-referenced access timing methodology for memory access operations, comprising the steps:selecting a particular wordline in a memory circuit for an access operation; and deselecting said particular wordline responsive to a shutdown feedback signal derived from said particular wordline.
- 21. The self-referenced access timing methodology for memory access operations as set forth in claim 20, wherein said steps of selecting a particular wordline and deselecting said particular wordline are performed in conjunction with a reference cell responsive to a wordline start (WLS) signal generated by an address decode block and a wordline end (WLE) signal generated by a wordline shutdown feedback block.
- 22. The self-referenced access timing methodology for memory access operations as set forth in claim 21, further comprising the step of controlling said reference cell's timing based on a bitline start (BLS) signal and a bitline end (BLE) signal.
- 23. A read access operation method in a memory circuit, comprising the steps:generating a bitline start (BLS) control signal responsive to a clock signal provided to said memory circuit; activating a wordline (WL) in said memory circuit based on a plurality of address signals; providing a feedback control signal generated based on said WL signal to a reference cell disposed in a row decoder of said memory circuit; and generating a bitline end (BLE) control signal operable to drive said WL signal LOW when a voltage level on said BLE control signal reaches a particular value, wherein said BLS and BLE control signals are operable to be coupled to a pair of data nodes supported by said reference cell.
- 24. The read access operation method in a memory circuit as set forth in claim 23, wherein said plurality of address signals are decoded to a wordline start (WLS) signal which activates an access transistor operable to couple said BLS control signal to a first one of said data nodes.
- 25. The read access operation method in a memory circuit as set forth in claim 24, wherein said feedback control signal generated based on said WL signal activates an access transistor operable to couple said BLE control signal to a second one of said data nodes.
- 26. The read access operation method in a memory circuit as set forth in claim 25, wherein when said voltage level on said BLE control signal reaches said particular value, a voltage differential operable to trigger a sense amplifier circuit is developed on a pair of bitlines associated with an accessed core cell of said memory circuit.
- 27. A write access operation method in a memory circuit, comprising the steps:generating a bitline start (BLS) control signal associated with a reference cell disposed in a row decoder of said memory circuit and driving a bitline pair associated with a selected core cell responsive to a clock signal provided to said memory circuit; responsive to said BLS control signal, flipping data in said reference cell; activating a wordline (WL) in said memory circuit based on a plurality of address signals; responsive to said WL, writing data into said selected core cell based on voltage levels of said bitline pair; and generating a bitline end (BLE) control signal operable to drive said WL signal LOW by flipping back said reference cell's data, wherein said BLS and BLE control signals are operable to be coupled to a pair of data nodes supported by said reference cell.
- 28. The write access operation method in a memory circuit as set forth in claim 27, wherein said plurality of address signals are decoded to a wordline start (WLS) control signal which activates an access transistor operable to couple said BLS control signal to a first one of said data nodes.
- 29. The write access operation method in a memory circuit as set forth in claim 28, wherein a feedback control signal generated based on said WL signal activates an access transistor operable to couple said BLE control signal to a second one of said data nodes.
- 30. The write access operation method in a memory circuit as set forth in claim 29, wherein said BLE control signal is generated at a slower rate than said bitline pair's rate.
- 31. The write access operation method in a memory circuit as set forth in claim 30, wherein said WL is activated when one of said bitline pair is substantially at near zero potential.
PRIORITY UNDER 35 U.S.C. §119(E) & 37 C.F.R. §1.78
This nonprovisional application claims priority based upon the following prior United States provisional patent application entitled: ROW DECODER WITH PRECISION BUILT-IN SHUTDOWN, Application No.: 60/334,111, filed Nov. 30, 2001, in the name(s) of: Jaroslav Raszka, which is hereby incorporated by reference for all purposes.
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