Address timing or clocking circuits Address control signal generation or management

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CPC
G11C8/18

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C8/00Arrangements for selecting an address in a digital store

Current Industry

G11C8/18Address timing or clocking circuits Address control signal generation or management

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Write leveling circuit applied to memory, and method and apparatus...
- Patent number 12,315,595
- Issue date May 27, 2025
- Zhiqiang Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device, controller and memory system
- Patent number 12,300,355
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Kuiyon Mun
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including a sub-controller and operating method of th...
- Patent number 12,300,341
- Issue date May 13, 2025
- SK Hynix Inc.
- Jong Joo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system
- Patent number 12,300,353
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Seung-Jun Shin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface and semiconductor memory device and semiconductor...
- Patent number 12,293,801
- Issue date May 6, 2025
- Samsung Electronics Co., Ltd.
- Hojun Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty cycle adjuster optimization training algorithm to minimize the...
- Patent number 12,272,426
- Issue date Apr 8, 2025
- Intel Corporation
- Arvind Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Command address control circuit and semiconductor apparatus and sem...
- Patent number 12,272,428
- Issue date Apr 8, 2025
- SK hynix Inc.
- Se Ra Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Row access strobe (RAS) clobber and row hammer failures using a det...
- Patent number 12,265,630
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory core characteristic screening method and system thereof
- Patent number 12,260,930
- Issue date Mar 25, 2025
- Integrated Silicon Solution Inc.
- Jeong Ho Bang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic way-based variable pipeline architecture for on-chip memory
- Patent number 12,249,400
- Issue date Mar 11, 2025
- ARM Limited
- Edward Martin McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic power management for on-chip memory
- Patent number 12,243,622
- Issue date Mar 4, 2025
- ARM Limited
- Edward Martin McCombs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for receiving strobe signal
- Patent number 12,231,100
- Issue date Feb 18, 2025
- Electronics and Telecommunications Research Institute
- Yi-Gyeong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Address signal transmission circuit, address signal transmission me...
- Patent number 12,224,039
- Issue date Feb 11, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kangling Ji
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for supporting command bus training mode and method o...
- Patent number 12,217,823
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with tracking circuitry for reducing active power
- Patent number 12,211,587
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tsung-Hsien Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Read data strobe path having variation compensation and delay lines
- Patent number 12,205,673
- Issue date Jan 21, 2025
- Cadence Design Systems, Inc.
- Hari Anand Ravi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and memory system including the same
- Patent number 12,190,995
- Issue date Jan 7, 2025
- Samsung Electronics Co., Ltd.
- Byunghoon Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and a method for controlling access to a memory m...
- Patent number 12,190,996
- Issue date Jan 7, 2025
- MONTAGE TECHNOLOGY CO., LTD.
- Yi Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for indicating row activation
- Patent number 12,183,421
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel routing for simultaneous switching outputs
- Patent number 12,176,065
- Issue date Dec 24, 2024
- ATI Technologies ULC
- Xuan Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory speed bin compatibility
- Patent number 12,154,654
- Issue date Nov 26, 2024
- Micron Technology, Inc.
- Erik V. Pohlmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal sampling circuit and semiconductor memory device
- Patent number 12,148,461
- Issue date Nov 19, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising programmable command-and-address and/or da...
- Patent number 12,142,348
- Issue date Nov 12, 2024
- RAMBUS INC.
- Ian Shaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extended-burst write training
- Patent number 12,119,080
- Issue date Oct 15, 2024
- Cadence Design Systems, Inc.
- Sreeja Menon
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, memory controller, memory device, memory system, and met...
- Patent number 12,100,475
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Hyungjin Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device, operating method thereof, controller fo...
- Patent number 12,094,552
- Issue date Sep 17, 2024
- Samsung Electronics Co., Ltd.
- Sehwan Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing-drift calibration
- Patent number 12,094,553
- Issue date Sep 17, 2024
- RAMBUS INC.
- Yohan U. Frans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface device
- Patent number 12,087,392
- Issue date Sep 10, 2024
- Electronics and Telecommunications Research Institute
- Young-Deuk Jeon
- G11 - INFORMATION STORAGE
Information Patent Grant
Mediating directed refresh management induced row hammer and row ac...
- Patent number 12,086,270
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY PHYSICAL LAYER INTERFACE, MEMORY APPARATUS AND METHOD THEREOF
- Publication number 20250157515
- Publication date May 15, 2025
- Faraday Technology Corp.
- Sivaramakrishnan Subramanian
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250149076
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
INPUT/OUTPUT INTERFACE CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20250149077
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Sungwoo Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED DECODER CIRCUIT AND METHOD
- Publication number 20250140294
- Publication date May 1, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- XiuLi YANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...
- Publication number 20250131953
- Publication date Apr 24, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250124959
- Publication date Apr 17, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM RELATED TO PERFORMING AN ERROR CHECK SCRUB OPE...
- Publication number 20250125000
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH TRACKING CIRCUITRY FOR REDUCING ACTIVE POWER
- Publication number 20250104753
- Publication date Mar 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tsung-Hsien HUANG
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, SYSTEM ON CHIP USING THE...
- Publication number 20250104752
- Publication date Mar 27, 2025
- Earth Top International Enterprises Ltd.
- TSAI-CHUNG YU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT, INTERFACE CIRCUIT FOR MEMORY CIRCUIT, AND METHOD OF...
- Publication number 20250087259
- Publication date Mar 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Wei LIANG
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUST...
- Publication number 20250061932
- Publication date Feb 20, 2025
- SK HYNIX INC.
- Jae Min SHIM
- G11 - INFORMATION STORAGE
Information Patent Application
TIMING-DRIFT CALIBRATION
- Publication number 20250054561
- Publication date Feb 13, 2025
- Rambus Inc.
- Yohan U. Frans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY
- Publication number 20250046353
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Erik V. Pohlmann
- G11 - INFORMATION STORAGE
Information Patent Application
COLUMN ADDRESS GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLU...
- Publication number 20250037748
- Publication date Jan 30, 2025
- SK HYNIX INC.
- Young Seung YOO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING
- Publication number 20250028660
- Publication date Jan 23, 2025
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR DETECTING A STATE OF A BUS
- Publication number 20240412801
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...
- Publication number 20240404572
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- HYUNGJIN KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES FOR CALIBRATING PHASE OF DIVISION CLOCK
- Publication number 20240404573
- Publication date Dec 5, 2024
- SK HYNIX INC.
- Chang Hyun KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS
- Publication number 20240395297
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Ferdinando Bedeschi
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY
- Publication number 20240395292
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Jeffrey E. KWAK
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for an Internal Clock Tree Structure in a Memor...
- Publication number 20240371421
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND/ADDRESS CHANNEL ERROR DETECTION
- Publication number 20240355407
- Publication date Oct 24, 2024
- Rambus Inc.
- John Eric Linstadt
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY...
- Publication number 20240339137
- Publication date Oct 10, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
DIVIDED CLOCK CONTROL
- Publication number 20240321332
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Jongtae Kwak
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES
- Publication number 20240312978
- Publication date Sep 19, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Fong-Yuan CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID MEMORY SYSTEM WITH INCREASED BANDWIDTH
- Publication number 20240304271
- Publication date Sep 12, 2024
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Application
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
- Publication number 20240303209
- Publication date Sep 12, 2024
- Uniquify, Inc.
- Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PERFORMING SELF-CALIBRATION OF RECEIVER OF...
- Publication number 20240304268
- Publication date Sep 12, 2024
- FARADAY TECHNOLOGY CORP.
- Chih-Hung Wu
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
- Publication number 20240282346
- Publication date Aug 22, 2024
- Samsung Electronics Co., LTD
- Sanghak SHIN
- G11 - INFORMATION STORAGE

Address timing or clocking circuits Address control signal generation or management

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Write leveling circuit applied to memory, and method and apparatus...

Non-volatile memory device, controller and memory system

Memory system including a sub-controller and operating method of th...

Memory device and memory system

Memory interface and semiconductor memory device and semiconductor...

Duty cycle adjuster optimization training algorithm to minimize the...

Command address control circuit and semiconductor apparatus and sem...

Row access strobe (RAS) clobber and row hammer failures using a det...

Memory core characteristic screening method and system thereof

Dynamic way-based variable pipeline architecture for on-chip memory

Dynamic power management for on-chip memory

Apparatus and method for receiving strobe signal

Address signal transmission circuit, address signal transmission me...

Memory device for supporting command bus training mode and method o...

SRAM with tracking circuitry for reducing active power

Read data strobe path having variation compensation and delay lines

Memory device and memory system including the same

Memory controller and a method for controlling access to a memory m...

Shared decoder circuit and method

Techniques for indicating row activation

Channel routing for simultaneous switching outputs

Dynamic random access memory speed bin compatibility

Signal sampling circuit and semiconductor memory device

Memory device comprising programmable command-and-address and/or da...

Extended-burst write training

Apparatus, memory controller, memory device, memory system, and met...

Non-volatile memory device, operating method thereof, controller fo...

Timing-drift calibration

Memory interface device

Mediating directed refresh management induced row hammer and row ac...

Patents Applicationslast 30 patents

MEMORY PHYSICAL LAYER INTERFACE, MEMORY APPARATUS AND METHOD THEREOF

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

INPUT/OUTPUT INTERFACE CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME

SHARED DECODER CIRCUIT AND METHOD

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DA...

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

SEMICONDUCTOR SYSTEM RELATED TO PERFORMING AN ERROR CHECK SCRUB OPE...

SRAM WITH TRACKING CIRCUITRY FOR REDUCING ACTIVE POWER

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, SYSTEM ON CHIP USING THE...

MEMORY CIRCUIT, INTERFACE CIRCUIT FOR MEMORY CIRCUIT, AND METHOD OF...

ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUST...

TIMING-DRIFT CALIBRATION

DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY

COLUMN ADDRESS GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLU...

MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING

TECHNIQUES FOR DETECTING A STATE OF A BUS

APPARATUS, MEMORY CONTROLLER, MEMORY DEVICE, MEMORY SYSTEM, AND MET...

SEMICONDUCTOR DEVICES FOR CALIBRATING PHASE OF DIVISION CLOCK

METHODS AND SYSTEMS FOR IMPROVING READ AND WRITE OF MEMORY CELLS

STORAGE DEVICE BASED ON DAISY CHAIN TOPOLOGY

Systems and Methods for an Internal Clock Tree Structure in a Memor...

COMMAND/ADDRESS CHANNEL ERROR DETECTION

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY...

DIVIDED CLOCK CONTROL

LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES

HYBRID MEMORY SYSTEM WITH INCREASED BANDWIDTH

CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

APPARATUS AND METHOD FOR PERFORMING SELF-CALIBRATION OF RECEIVER OF...

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME