Patent Application
20240035898
The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture.
A power amplifier is an electronic device that can increase the power of a signal (a time-varying voltage or current). An RF amplifier amplifies signal in the radio frequency range between 20 kHz and 300 GHz. High frequency RF power amplifiers require the device to be operated at high current density, biased at peak Gm (e.g., above 77 GHz) or peak Fmax (e.g., >350 GHz). This, in turn, results in high heat generation and, in some instances, over-heating of the device/circuit. For example, the temperature rise of the power amplifier due to heat generated during circuit operations can degrade the power amplifier performance and can even impact circuitry at the proximity of the heat source.
In an aspect of the disclosure, a structure comprises: at least one active gate structure; and a built-in temperature sensor adjacent to and on a same device level as the at least one active gate structure, the built-in temperature sensor further comprises force lines and sensing lines.
In an aspect of the disclosure, a structure comprises: a plurality of adjacent active gate structures; and a built-in temperature sensor comprising a plurality of floating gate structures within source/drain regions of selected active gate structures of the plurality of active gate structures, and further including force lines and sensing lines.
In an aspect of the disclosure, a method comprises: providing a voltage at an input line of a built-in temperature sensor that is adjacent to at least one active gate structure; sensing the voltage at the input line; discharging the voltage at an output line of the built-in temperature sensor; sensing the voltage at the output line; determining a resistance as a difference between the voltage at the input line and the voltage at the output line divided by a current through the built-in temperature sensor; and correlating the resistance to a temperature associated with heat generated by the at least one active gate structure.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. In embodiments, the built-in temperature sensors may be provided in RF/mmW power amplifiers. The RF/mmW power amplifiers may be provided in bulk semiconductor substrate or fully-depleted semiconductor-on-insulator (FDSOI) technologies, in either planar or finFET configurations. For example, the built-in temperature sensors may be built-in floating gate thermal sensors in FDSOI. Advantageously, the built-in temperature sensors can provide in situ temperature monitoring at low cost, e.g., no additional masks needed, with little to no impact on device design.
In embodiments, the built-in temperature sensors monitor the temperature changes at the device level in order to characterize the heating behavior of a power amplifier. The built-in temperature sensors may be used in conjunction with additional temperature detection circuitry for sensing the temperature during circuit operation. The built-in temperature sensors may be, for example, floating gate structures provided in different configurations and/or different locations within the circuitry as described below. For example, the floating gate structures may be in a serpentine configuration surrounding several active gate structures. Also, the floating gate structures may be placed at source and drain regions for relaxed contacted polysilicon pitch (CPP) devices.
The built-in temperature sensors of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the built-in temperature sensors of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the built-in temperature sensors uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material lines as is known in the art.
The active gate structures 12 and optional floating gate structures 22 include source/drain regions 16. The source/drain regions 16 may be provided by epitaxial semiconductor growth processes with an in-situ doping or ion implantation processes as known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure. The active gate structures 12 include gate contacts 14 and the source/drain regions 16 include source/drain contacts 18. The gate contacts 14 and the source/drain contacts 18 may be connected to an upper wiring line depicted at reference numeral 20.
Still referring to
In embodiments, the built-in temperature sensor 24 includes four terminals, e.g., wiring lines 24d, 24e, 24f, 24g, similar to a Kelvin sensing structure. For example, the wiring lines 24e, 24g may be sensing lines; whereas the wiring lines 24d, 24f may be force lines. In this way, the temperature sensor 24 will be in close proximity to heat generating devices, with two terminals (e.g., wiring lines 24e, 24g) capable of sensing a voltage drop through the built-in temperature sensor 24 and two terminals (wiring lines 24d, 240 capable of providing and discharging a current through the built-in temperature sensor 24 as described in more detail herein.
In embodiments, the upper metal wiring lines 24c-24g may be on a same device level as the upper wiring line 20. Also, the upper metal wiring lines 20, 24c-24g may be fabricated during the same fabrication processes using conventional lithography, etching and deposition methods. For example, the metal wiring lines 20, 24c-24g and contacts 14, 18 can be fabricated using single damascene processes or a dual damascene process. In either fabrication process, a resist formed over insulator material is exposed to energy (light) and developed to form a pattern (opening) corresponding to the pattern of the metal wiring lines 20, 24c-24g (and contacts 14, 18). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the resist line to the insulator material. Following the resist removal by a conventional oxygen ashing process or other known stripants, conductive material can be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes. Any residual material on the surface of the insulator material can be removed by conventional chemical mechanical polishing (CMP) processes.
Prior to forming the contacts 14, 18, silicide contacts may be formed on active regions of the device, e.g., active gate structures 12 and source/drain regions 16. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal line, e.g., nickel, cobalt or titanium, over fully formed and patterned semiconductor devices (e.g., doped or ion implanted source and drain regions 16 and respective devices (e.g., active gate structures 12)). After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active regions of the semiconductor device. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.
In operation, a voltage and current can be applied to the built-in temperature sensor 24 to measure resistance (R). The resistance (R), in turn, can be used to calculate local temperature (e.g., heat generation) as shown, for example, in
More specifically, a voltage and current may be applied to wiring line 24d as depicted by F+. The current will remain constant throughout the built-in temperature sensor 24. The voltage may be sensed at wiring line 24e as depicted by S+. The current passes through the floating gate structures 24a, contacts 24b, and wiring lines 24c-24g in the direction of the arrows shown in
The temperature of the device can be determined by calculating the resistance, R, e.g., R=V/I, where voltage is a difference between the input voltage S+ and the output voltage S− and current (I) remains constant. And as shown in
The built-in temperature sensors can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
