1. Technical Field
The present invention relates to doped wells, and more particularly, to doped biasing wells used to reduce threshold voltage variation in semiconductor integrated circuits.
2. Related Art
Fabricating a semiconductor device such that it has a target threshold voltage as designed is difficult. One of the methods for achieving the target threshold voltage as designed is to form a highly-doped well under the channel region of the semiconductor device and use well (voltage) bias as a means of adjusting the threshold voltage to the target. However, the highly-doped biasing well results in leakage current between itself and the source/drain regions of the semiconductor device as well as increased junction capacitance, particularly at the edge of the junctions beneath the channel.
Therefore, there is a need for a novel structure in the semiconductor device to eliminate or reduce such leakage current and such junction capacitance. There is also a need for a method for fabricating such a novel structure.
The present invention provides a semiconductor structure, comprising (a) first and second source/drain regions; (b) a channel region disposed between the first and second source/drain regions; (c) a buried well region in physical contact with the channel region; and (d) a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing leakage current between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
The present invention also provides method for forming a semiconductor structure, the method comprising the steps of (a) providing a semiconductor substrate covered on top with a mandrel layer; (b) etching a trench through the mandrel layer and into the substrate; (c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the substrate and the mandrel layer; (d) forming a buried well region and a channel region in the trench, wherein the channel region is on top of the buried well region; and (e) forming first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, and wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region.
The present invention also provides a method for forming a semiconductor structure, the method comprising the steps of (a) providing a semiconductor substrate covered on top with a mandrel layer; (b) etching a trench through the mandrel layer and into the substrate; (c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the substrate and the mandrel layer; (d) depositing a semiconductor material in the trench so as to form an under-gate region such that the buried barrier region is completely buried in the under-gate region; (e) forming a gate spacer region on side walls of the trench; (f) doping via the trench a portion of the under-gate region which is surrounded by the buried barrier region, wherein the doped portion of the under-gate region comprises a buried well region, and wherein an undoped portion of the under-gate region on top of the buried well region comprises a channel region; (g) forming a gate dielectric layer on top of the channel region; (h) forming a gate region on top of the gate dielectric layer, wherein the gate region is electrically insulated from the channel region by the gate dielectric layer; and (i) forming first and second source/drain regions in the substrate, wherein the channel region is disposed between the first and second source/drain regions, wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region, and wherein the buried barrier region is adapted for preventing leakage current between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
The present invention also provides a method for forming a semiconductor structure, the method comprising the steps of (a) providing a silicon-on-insulator (SOI) substrate covered on top with a mandrel layer, wherein the SOI substrate includes (i) an upper semiconductor layer, (ii) a lower semiconductor layer, and (iii) an electrical insulator layer sandwiched between the upper and lower semiconductor layers; (b) etching a trench through the mandrel layer and into the SOI substrate such that the lower semiconductor layer is exposed to the atmosphere at a bottom wall of the trench; (c) forming a buried barrier region on a side wall of the trench, wherein the buried barrier region is in direct physical contact with both the SOI substrate and the mandrel layer; (d) forming a buried well region and a channel region in the trench, wherein the channel region is on top of the buried well region; and (e) forming first and second source/drain regions, wherein the channel region is disposed between the first and second source/drain regions, wherein the buried barrier region is disposed between the buried well region and the first source/drain region and is disposed between the buried well region and the second source/drain region.
The present invention provides a semiconductor structure with reduced leakage current and reduced capacitance between its doped biasing well and its source/drain regions.
With reference to
With reference to
In one embodiment, the formation of the buried barrier region 120 can start with the formation of a buried barrier layer 120′ (defined by dashed line) on side and bottom walls of the trench 117 by, illustratively, CVD SiO2 (i.e., chemical vapor deposition of silicon dioxide). Then, the buried barrier layer 120′ is etched down in vertical direction 190 (anisotropic etching). As a result, the buried barrier region 120 is formed as shown.
With reference to
With reference to
More specifically, the formation of the gate spacer region 125 can start with the formation of a gate spacer layer 125′ (defined by the dashed line) on side and bottom walls of the trench 117 by, illustratively, CVD SiO2. Then, the gate spacer layer is etched down in vertical direction 190. As a result, the gate spacer region 125 is formed as shown.
After the gate spacer region 125 is formed, in one embodiment, a buried well region 130 surrounded (i.e., circumscribed) by the buried barrier region 120 is doped heavily (1×1019-1×1020 impurity atoms/cm3). In an alternative embodiment, the buried well region 130 is doped before the gate spacer region 125 is formed. The silicon region 132 on top of the buried well region 130 can be referred to as the channel region 132. If the structure 100 is to become an n-channel transistor, the buried well region 130 should be doped heavily with p-type impurities (e.g., Boron, Indium, or Galium). Conversely, if the structure 100 is to become a p-channel transistor, the buried well region 130 should be doped heavily with n-type impurities (e.g., Arsenic, Antimony, or Phosphorous).
With reference to
With reference to
Next, in one embodiment, silicon is epitaxially grown on top of the entire structure 100 until the top surface 112 of the single-crystal silicon substrate 110 rises to a level higher than the gate dielectric layer 135 as shown in
Next, with reference to
Next, in one embodiment, heavily-doped (5×1019-3×1020 impurity atoms/cm3) source/drain regions 150a and 150b are formed at top regions of the substrate 110. More specifically, in one embodiment, the source/drain regions 150a and 150b can be doped by ion implantation using the gate spacer region 145 as a mask. This ion implantation step also implants dopants in the polysilicon gate region 140, but that does not detrimentally affect the functionality of the gate region 140. If the structure 100 is to become an n-channel transistor, the source/drain regions 150a and 150b should be heavily doped with n-type impurities (e.g., arsenic, phosphorous, or antimony).
In summary, with the presence of the heavily-doped buried well region 130 under the channel region 132, a prespecified target threshold voltage of the transistor 100 can be achieved through fabrication within an acceptable tolerance by controlling the doping concentration of the buried well region 130. In addition, with the presence of the buried barrier region 120 which surrounds the buried well region 130 and therefore insulates the buried well region 130 from the source/drain regions 150a and 150b, the leakage current and junction capacitance between the buried well region 130 and the source/drain region 150a and the leakage current and junction capacitance between the buried well region 130 and the source/drain region 150b are eliminated or at least reduced during the operation of the structure 100. In one embodiment, the material of the buried barrier region 120 can be selected so as to maximize the effect of preventing (i.e., essentially eliminating) such leakage current and junction capacitance.
In the embodiments described above, the substrate 110 can be undoped or lightly doped with p-type impurities if the structure 100 is to become an n-channel device or with n-type impurities if the structure 100 is to become a p-channel device. The substrate 110 can comprise any other semiconductor material instead of and/or in combination with silicon.
In an alternative embodiment, the trench 117 (
With reference to
Afterwards, the fabrication steps for forming the semiconductor structure 200 are similar to the fabrication steps for forming the semiconductor structure 100 of
Then, in one embodiment, silicon material is epitaxially grown in the trench 217 to a top surface 224 which is higher than the top surface 222 of the buried barrier region 220. As a result, the substrate region 210c has a new top surface 224 in the trench 217, and the buried barrier region 220 is completely submerged (i.e., buried) in the substrate region 210c.
The remaining steps of the fabrication process of the semiconductor structure 200 is similar to that of the semiconductor structure 100 of
While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
This application is a Divisional of Ser. No. 10/711,450, filed Sep. 20, 2004.
Number | Name | Date | Kind |
---|---|---|---|
4824796 | Chiu et al. | Apr 1989 | A |
4862232 | Lee | Aug 1989 | A |
4885618 | Schubert et al. | Dec 1989 | A |
5290714 | Onozawa | Mar 1994 | A |
5362663 | Bronner et al. | Nov 1994 | A |
5548143 | Lee | Aug 1996 | A |
5789286 | Subbanna | Aug 1998 | A |
5932908 | Noble | Aug 1999 | A |
6001676 | Sawada et al. | Dec 1999 | A |
6074899 | Voldman | Jun 2000 | A |
6469355 | Schneider et al. | Oct 2002 | B1 |
6515319 | Widmann et al. | Feb 2003 | B2 |
6674672 | Forbes et al. | Jan 2004 | B2 |
6867433 | Yeo et al. | Mar 2005 | B2 |
20040046208 | Dennard et al. | Mar 2004 | A1 |
Number | Date | Country | |
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20070293010 A1 | Dec 2007 | US |
Number | Date | Country | |
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Parent | 10711450 | Sep 2004 | US |
Child | 11845244 | US |