Patent Application
20070069309
The present invention relates generally to semiconductor devices and, more particularly, to buried wells for semiconductor devices.
Semiconductor devices such as complementary metal-oxide-semiconductor (CMOS) transistors typically include a gate electrode and a gate dielectric formed on a substrate (usually a silicon semiconductor substrate). Source and drain extension junctions are formed on opposing sides of the gate electrode by implanting N-type or P-type impurities into the substrate. Oxide or nitride spacers are normally formed adjacent to the gate prior to deeper source and drain implants.
A deep well is generally formed in the substrate to provide isolation and an electrical connection between the channel region of the transistor and a well contact. Ideally, the conductive path between the channel region and the well contact is characterized by low resistance to improve latch-up prevention and transistor substrate bounce. This is particularly more important as designs shrink.
Typically, creating a low resistance path between the channel region and the well contact has been done by increasing the dopant concentration in the well. This method involved performing a high-dosage well implant process prior to forming the transistor. However, increasing the dopant concentration causes the depletion region between the source/drain regions and the surrounding well area to become narrow, thereby increasing the junction capacitance between the source/drain regions and the surrounding well area. Because the delay of the transistor is proportional to the capacitance, the delay also increases.
For the dopant concentration needed at the peak of the well implant, the level of dopant at the bottom of the S/D junction is very high after implant. As such, even diffusion-less annealing or the co-implantation of other species to reduce diffusion will not enable lower dopant levels at the junction.
Therefore, what is needed is a method to reduce the junction capacitance while maintaining good conductivity between the channel region and the well contact.
These and other problems are generally reduced, solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention, which provides a buried well for semiconductor devices.
In accordance with an embodiment of the present invention, a substrate having a buried well is provided. The substrate comprises a surface well formed on a first substrate and an epitaxial layer subsequently formed thereon. After forming the epitaxial layer, the surface well becomes a buried well. Because the epitaxial layer is formed after the surface well is formed, the epitaxial layer remains substantially undoped, creating a sharp increase in dopant concentration between the epitaxial layer and the buried well.
In an embodiment, a transistor is formed on the epitaxial layer. In this embodiment a portion of the epitaxial layer positioned between source/drain regions of the transistor and the buried layer may remain undoped, thereby creating a wide depletion region and low junction capacitance.
In another embodiment, the epitaxial layer may be doped to lower the resistance between the channel region of the transistor and a well contact.
In yet another embodiment, a channel implant may be performed in the channel region. In this embodiment, the channel implant extends from a surface of the epitaxial layer to the buried well under the gate electrode of the transistor, but regions of the epitaxial layer between the source/drain regions of the transistor and the buried well remain substantially undoped. The channel implant allows a low resistance path between the channel region and a well contact, while the undoped regions of the epitaxial layer reduce the junction capacitance.
It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
The object and other advantages of this invention are best described in the preferred embodiment with reference to the attached drawings that include:
a is a graph illustrating a doping profile that may be used to form a buried well in accordance with an embodiment of the present invention; and
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
It should also be noted that the following method is equally applicable to NMOS and PMOS devices and that the dopants and processes discussed herein are provided for illustrative purposes only to better explain the present invention. Furthermore, embodiments of the present invention may be used in a variety of circuits, such as memory devices, logic devices, I/O devices, low or high voltage devices, and the like.
Referring first to
The surface well 112 is formed in a top region of the substrate 110 and may be formed by implanting dopants into the top surface of the substrate 110. Preferably, the surface well 112 is of the same conductivity type as a deep well for a specific type of device. For example, a P-type surface well implant may be formed for use with an NMOS device by implanting boron ions, and an N-type surface well implant may be formed for use with a PMOS device by implanting phosphorous ions. In an embodiment the surface well implants are formed using a dose of about 1e12 to about 1e14 atoms/cm2 with an energy such that the dopants are confined to a depth up to about 500 nm.
a, depicts a doping profile that may be used in an embodiment of the present invention. As illustrated, this embodiment utilizes two implants, preferably concentrating dopants along the surface of the substrate 110 and tapering off below the surface. However, it should be noted that the above dopant profile is provided for illustrative purposes only, and that other dopants and dopant profiles may be used. For example, a single implant or three or more implants may be used to create different doping profiles, and other N/P-type dopants, energy levels, and doses may be used.
Referring back to
Referring back to
Preferably, a rapid thermal anneal (RTA) is performed to repair damage done to the surface of the substrate 110 by the implant process. In an embodiment, it has been found that an RTA performed at a temperature of 1100° C. for 10 seconds, however this can also be done between about 700° C. to about 1100° C. for up to 30 minutes, repairs the surface of the substrate 110, thereby creating a smoother surface from which a layer may be grown in subsequent steps. By starting with a smoother surface, the subsequent layer may be more uniform and with fewer defects.
The semiconductor layer 210 provides a substantially undoped semiconductor layer 210 in which NMOS and PMOS devices (e.g., transistors) may be formed. Thus, the surface well 112 of
STIs 212, or some other isolation structures such as field oxide regions or deep trench isolation, are formed in the substrate 110 to isolate active areas on the substrate. The STIs 212 may be formed by etching trenches in the substrate and filling the trenches with a dielectric material, such as silicon dioxide, a high-density plasma (HDP) oxide, or the like. Preferably, the STIs 212 extend through the semiconductor layer 210 over the buried well 214 and contact the buried well 214.
The gate electrode 314 comprises a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped poly-crystalline silicon, other conductive materials, a combination thereof, or the like. In one example, amorphous silicon is deposited and re-crystallized to create poly-crystalline silicon (polysilicon). The polysilicon layer may be formed by depositing doped or undoped polysilicon by low-pressure chemical vapor deposition (LPCVD).
Spacers 316 may be formed by depositing and patterning a dielectric layer. In an embodiment the spacers 316 are formed by depositing, for example, silicon nitride and performing an isotropic or anisotropic etch process to form the spacers 316 as illustrated in
The source/drain regions 318 are shown as comprising a lightly-doped drain (LDD) 320 and a heavily-doped region 322 for illustrative purposes. The transistor may include, for example, halo implants and/or pocket implants.
A well contact 350 having a lightly-doped region 352 and a heavily doped region 354 may also be formed as is known in the art. Generally, the well contact 350 provides an electrical contact to the substrate and the channel region and is typically used to reduce the capacitance of the substrate below the gate electrode and the source/drain regions. The well contact 350 may be formed by performing a P− or N− implant that extends substantially to the buried well 214, thereby forming the lightly-doped region 352. A P+ or N+ implant may then be performed to form the heavily doped region 354. As one of ordinary skill in the art will appreciate, the lightly-doped region 352 and heavily-doped region 354 are typically doped with N-type ions to form a PMOS transistor and doped with P-type ions to form an NMOS transistor.
In the embodiment discussed above, the semiconductor layer 210 below the source/drain regions 318 and the gate electrode 314 are substantially undoped. Accordingly, the depletion region is wide creating a low capacitance junction. However, the semiconductor layer 210 below the gate electrode 314 is also substantially undoped. This undoped region below the gate electrode 314 is generally characterized by high resistance and may reduce the ability of the hot carriers to be conducted to the well contact in some applications.
In an alternative embodiment, the semiconductor layer 210 may be lightly doped (N-/P-type) to achieve greater conductivity between the channel region of the transistor 310 and the well contact 350. This greater conductivity will reduce the hot carrier charges and may be more desirable in some applications. In an embodiment, the semiconductor layer 210 may be doped by implanting an N-type dopant for a PMOS device or a P-type dopant for an NMOS device. In an embodiment, a lightly-doped well is formed such that a peak dopant concentration is at a depth from about 200 nm to about 300 nm. Other depths and/or doping profiles may be used.
After patterning the mask 410, one or more implants may be performed to dope the well contact region 416 and a channel implant region 412. The channel implant region 412 and the well contact region 416 may be doped by performing a P− or N− implant such that the doped regions extend to the buried well and having a peak concentration below the source/drain regions.
Thereafter, a transistor 510 may be formed as described above with reference to the transistor 310 of
As one of ordinary skill in the art will appreciate, this embodiment provides a lower resistance path between the channel region and the well contact 416 by doping the channel region down to the buried well 214, which electrically connects the channel region to the well contact 416. At the same time, the region below the source/drain regions 318 remains relatively undoped. As a result, the depletion region is wide and the junction capacitance between the source/drain regions and the surrounding well area is reduced.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
