Claims
- 1. A bus interface module (“BIM”) connectable to a debug bus comprising a plurality of BIM segments connected in a ring such that an output of each BIM is connected to an input of a next BIM via the debug bus, the BIM comprising:
logic for receiving data from a previous BIM; logic for receiving data from local logic associated with the BIM; and logic for combining the previous BIM data with local logic data and transmitting the combined data to a next BIM.
- 2. The BIM of claim 1 wherein the logic for receiving data from a previous BIM, logic for receiving data from local logic, and logic for combining each comprise a plurality of multiplexers.
- 3. The BIM of claim 1 wherein the data received from a previous BIM and the data received from local logic are logically subdivided into individually-manipulable data blocks.
- 4. The BIM of claim 3 further comprising logic for replicating a selected block of data.
- 5. The BIM of claim 3 further comprising logic for moving data received from the previous BIM in a first block position to a second block position.
- 6. The BIM of claim 5 wherein the logic for moving data comprises N N×1 multiplexors, each input of the N N×1 multiplexors operating to accept one block of the data received from a previous BIM.
- 7. The BIM of claim 6 wherein the value of N is equal to the width of the debug bus divided by the width of each of the data blocks.
- 8. The BIM of claim 5 further comprising circuitry for providing a control signal specifying a block position of each block of data received from the previous BIM to the logic for moving data.
- 9. The BIM of claim 8 wherein the circuitry for providing a control signal comprises a control status register (“CSR”).
- 10. The BIM of claim 5 further comprising logic for transmitting at least a portion of the data received from local logic in the first one of the block positions.
- 11. A debug bus comprising a plurality of logic modules connected in a ring such that an output of each logic module is connected to an input of a next logic module via the debug bus, each logic module comprising:
means for receiving data from a previous logic module; means for receiving data from local logic associated with the logic module; and means for combining the previous logic module data with local logic data and transmitting the combined data to a next logic module.
- 12. The debug bus of claim 11 wherein the means for receiving data from a previous logic module, means for receiving data from local logic, and means for combining each comprise a plurality of multiplexers.
- 13. The debug bus of claim 11 wherein the debug bus is partitioned into a plurality of block positions such that data transmitted via the debug bus is segmented into blocks.
- 14. The debug bus of claim 13 wherein each of the blocks of data is individually manipulable.
- 15. The debug bus of claim 13 wherein each logic module further comprises means for providing a control signal specifying a block position of each of the blocks of data received from the previous logic module to the means for receiving data from a previous logic module.
- 16. The debug bus of claim 15 wherein the means for providing a control signal comprises a control status register (“CSR”).
- 17. The debug bus of claim 15 wherein the debug bus is 80 bits wide and is partitioned into eight 10-bit block positions.
- 18. The debug bus of claim 15 wherein each logic module further comprises means for moving data received from the previous logic module in a first one of the block positions to a second one of the block positions.
- 19. The debug bus of claim 18 wherein the means for moving data comprises N N×1 multiplexors, each input of the N N×1 multiplexors operating to accept one block of the data received from a previous logic module.
- 20. The debug bus of claim 19 wherein the value of N is equal to the width of the debug bus divided by the width of each of the data blocks.
- 21. The debug bus of claim 15 wherein each logic module further comprises means for replicating a selected block of data.
- 22. The debug bus of claim 15 wherein each logic module further comprises means for transmitting at least a portion of the data received from local logic in the first one of the block positions.
- 23. A method of implementing a debug bus including a plurality of logic modules connected in a ring such that an output of each logic module is connected to an input of a next logic module via the debug bus, the method comprising:
receiving, at each module, data from a previous logic module; receiving data from local logic associated with the logic module; and combining the previous logic module data with local logic data and transmitting the combined data to a next logic module.
- 24. The method of claim 23 wherein the receiving data from a previous logic module, receiving data from local logic, and combining are each performed using a plurality of multiplexers.
- 25. The method of claim 23 wherein the debug bus is partitioned into a plurality of block positions such that data transmitted via the debug bus is segmented into blocks.
- 26. The method of claim 25 wherein each of the blocks of data is individually manipulable.
- 27. The method of claim 25 further comprising, at each logic module, providing a control signal specifying a block position of each of the blocks of data received from the previous logic module.
- 28. The method of claim 27 wherein the providing a control signal is implemented using a control status register (“CSR”).
- 29. The method of claim 27 wherein the debug bus is 80 bits wide and is partitioned into eight 10-bit block positions.
- 30. The method of claim 27 further comprising, at each logic module, moving data received from the previous logic module in a first one of the block positions to a second one of the block positions.
- 31. The method of claim 27 wherein the moving of data is effectuated by N N×1 multiplexors, each input of the N N×1 multiplexors operating to accept one block of the data received from a previous logic module.
- 32. The method of claim 31 wherein the value of N is equal to the width of the debug bus divided by the width of each of the data blocks.
- 33. The method of claim 27 further comprising, at each logic module, replicating a selected block of data.
- 34. The method of claim 27 further comprising, at each logic module, transmitting at least a portion of the data received from local logic in the first one of the block positions.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. patent application Ser. No. ______, filed ______ entitled AN INTEGRATED CIRCUIT (Docket No. 200209004-1); U.S. patent application Ser. No. ______, filed ______ entitled SYSTEM AND METHOD FOR USING A DEBUG BUS AS A CAPTURE BUFFER (Docket No. 200208677-1); and U.S. patent application Ser. No. ______, filed ______ entitled SYSTEM AND METHOD FOR VERIFYING HDL EVENTS (Docket No. 200208679-1), all of which are hereby incorporated by reference in their entirety.