Claims
- 1. A cache fabricated on a die with the processor, comprising:
a plurality of cache banks, each containing a plurality of subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache; means for synchronously transmitting output data from the cache banks to the central location in a pipelined manner such that data requested by the processor arrives at the central location at a predetermined time regardless of which of the cache banks is accessed to retrieve the data.
- 2. The cache of claim 1 wherein the means comprises a first data bus to transmit the output data from the cache banks to the central location.
- 3. The cache of claim 2 wherein the means further comprises a second data bus to transmit input data from the central location to the cache banks.
- 4. The cache of claim 2 wherein the physical relationship is such that a first cache bank is located a farthest distance from the central location, and a second cache bank is located a nearer distance to the central location.
- 5. The cache of claim 4 wherein the means further comprises:
N bus repeaters, where N is an integer greater than or equal to one, each of the N bus repeaters operating synchronous with the processor and being spaced on the first bus such that data accessed from the first cache bank, which is sent on the first bus in a first clock cycle by either the first cache bank or a bus repeater, is received at a next repeater or the central location before a next clock cycle.
- 6. The cache of claim 5 wherein the means further comprises:
at least one staging device associated with the second cache bank to provide a synchronous delay to data output on the first bus from the second cache bank.
- 7. The cache of claim 6 wherein the second cache bank comprises a nearest cache bank to the central location, and the synchronous delay comprises N−1 clock cycles.
- 8. The cache of claim 1 wherein the predetermined time comprises a latency that remains constant for each data request of the processor to the cache.
- 9. The cache of claim 1 wherein the cache comprises a third level cache of a cache hierarchy associated with the processor.
- 10. A method of accessing data stored in a cache, comprising:
issuing first and second data requests by a processor core to the cache in a first pair of consecutive clock cycles, the processor core being fabricated on a single die with the cache; accessing first and second locations in the cache responsive to the first and second data requests, respectively, the first and second locations having a physical relationship to the processor core; returning to the processor core in a second pair of consecutive clock cycles data from the first location followed by data from the second location, regardless of the physical relationship.
- 11. The method of claim 10 wherein the first and second locations comprises first and second banks, respectively.
- 12. The method of claim 11 wherein data from the first and second banks is returned to the processor core in a predetermined number of clock cycles.
- 13. The method of claim 12 wherein the predetermined number of clock cycles comprises a function of an operating frequency of the processor and a distance between a nearest and a farthest bank in the cache relative to a central location on the single die that provides a point for information transfer between the processor core and the cache.
- 14. The method of claim 13 wherein the first bank is the farthest bank and the second bank is the nearest bank.
- 15. The method of claim 11 further comprising:
staging the return of data from the second bank using one or more clocked devices.
- 16. The method of claim 15 wherein the one or more clocked devices comprise flip-flops.
- 17. A cache fabricated on a die with a processor comprising:
a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache; a data path to provide synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.
- 18. The cache of claim 17 wherein the data path comprises a first data bus to transmit the output data from the cache banks to the central location.
- 19. The cache of claim 18 wherein the data path further comprises a second data bus to transmit input data from the central location to the cache banks.
- 20. The cache of claim 18 wherein the physical relationship is such that a first cache bank is located a farthest distance from the central location, and a second cache bank is located a nearer distance to the central location.
- 21. The cache of claim 20 wherein the data path further comprises:
N bus repeaters, where N is an integer greater than or equal to one, each of the N bus repeaters operating synchronous with the processor core and being spaced on the first bus such that data accessed from the first cache bank, which is sent on the first bus in a first clock cycle by either the first cache bank or a bus repeater, is received at a next repeater or the central location before a next clock cycle.
- 22. The cache of claim 21 wherein the data path further comprises:
at least one staging device associated with the second cache bank to provide a synchronous delay to data output on the first bus from the second cache bank.
- 23. The cache of claim 22 wherein the second cache bank comprises a nearest cache bank to the central location, and the synchronous delay comprises N−1 clock cycles.
- 24. The cache of claim 17 wherein the predetermined number of clock cycles comprises a latency that remains constant for each data request of the processor core to the cache.
- 25. The cache of claim 17 wherein the cache comprises a third level cache of a cache hierarchy associated with the processor core.
RELATED APPLICATIONS
[0001] This application is related to Ser. No. ______ filed ______, entitled “CACHE ARCHITECTURE WITH REDUNDANT SUB ARRAY” and Ser. No. ______ filed ______, entitled “ON-DIE CACHE MEMORY WITH REPEATERS”, both of which are assigned to the assignee of the present application.