Patent Application
20190065373
The present disclosure relates generally to memory devices, and more particularly, to apparatuses and methods for a cache buffer.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.
Memory is also utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non-volatile memory may be used in, for example, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.
Memory can be part of a memory module (e.g., a dual in-line memory module (DIMM)) used in computing devices. Memory modules can include volatile, such as DRAM, for example, and/or non-volatile memory, such as Flash memory or RRAM, for example. The DIMMs can be using a main memory in computing systems.
The present disclosure includes apparatuses and methods related to a cache buffer. An example apparatus can store data associated with a first request in a particular one of a number of buffers and service a subsequent, second request for data associated with the request using the particular one of the number of buffers.
In a number of embodiments, a number of buffers can be allocated to service requests and/or subsequent requests that are associated with data allocated to a particular buffer. The number of buffers can be searchable by the cache controller, so that data associated with a subsequent request can be located in a buffer and the subsequent request can be serviced using the buffer. Servicing a request using searchable buffers allows the cache line where the data in the buffer was located to not be locked while servicing a request that moves the data from the cache line to the buffer.
Also, buffers that are allocated to service a request can be masked so the masked buffers are not accessible when servicing subsequent requests. Buffers can be masked in response to receiving requests associated with data that is to be written to a cache line from which data was evicted and stored in the buffers that are being masked.
In a number of embodiments, using searchable buffers can allow the number of buffers to service requests to scale along with the size of the cache. Therefore, performance of the cache using searchable buffer is independent of the size of the cache.
In a number of embodiments, a cache controller can store data associated with a first request in a particular one of the number of buffers and service a subsequent (e.g., a second) request for data associated with the first request using the particular one of the number of buffers. The subsequent request is serviced while the first request is being serviced. The requests and/or subsequent request can evict data from the cache, read data from a buffer and/or cache, and/or write data to a buffer and/or cache. The buffers can be searchable, via a search algorithm performed with software, firmware, and/or hardware, to identify a block of number associated with data that is stored in the buffer.
In a number of embodiments, the cache controller can store data associated with an initial request in a first buffer and service a first subsequent request for data using another (e.g., a second) buffer and service a second subsequent request using the second buffer. The first buffer with data associated with the initial buffer can be masked while servicing the first subsequent request and the second subsequent request. The first subsequent request can write data to the cache where the data associated with the initial request was evicted. The second subsequent request can be serviced while the initial request and the first subsequent request are being serviced. Data associated with the second subsequent request can be located in another (e.g., second) buffer, which also includes data associated with the first subsequent request, using a linked list structure.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “X” and “Y”, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices).
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 120 may reference element “20” in
As illustrated in
Host 102 can includes a host controller to communicate with memory system 104. The host 102 can send requests that include commands to the memory system 104 via a channel. The host 102 can communicate with memory system 104 and/or the controller 108 on memory system 104 to read, write, and erase data, among other operations. A physical host interface can provide an interface for passing control, address, data, and other signals between the memory system 104 and host 102 having compatible receptors for the physical host interface. The signals can be communicated between host 102 and memory system 104 on a number of buses, such as a data bus and/or an address bus, for example, via channels.
Controller 108, a host controller, a controller on cache 110, and/or a controller on a memory device can include control circuitry, e.g., hardware, firmware, and/or software. In one or more embodiments, controller 108, a host controller, a controller on cache 110, and/or a controller on a memory device can be an application specific integrated circuit (ASIC) coupled to a printed circuit board including a physical interface. Memory system can include cache controller 120 and cache 110. Cache controller 120 and cache 110 can be used to buffer and/or cache data that is used during execution of read commands and/or write commands.
Cache controller 120 can include a number of buffers 122-1, . . . , 122-Y. Buffers 122-1, . . . , 122-Y can includes a number of arrays of volatile memory (e.g., SRAM). Buffers 122-1, . . . , 122-Y can be configured to store signals, address signals (e.g., read and/or write commands), and/or data (e.g., metadata and/or write data). Buffers 122-1, . . . , 122-Y can temporarily store signals and/or data while commands are executed. Cache 110 can include arrays of memory cells (e.g., DRAM memory cells) that are used as cache and can be configured to store data that is also stored in a memory device. The data stored in cache and in the memory device is addressed by the controller and can located in cache and/or the memory device during execution of a command.
Memory devices 111-1, . . . , 111-X can provide main memory for the memory system or could be used as additional memory or storage throughout the memory system 104. Each memory device 111-1, . . . , 111-X can include one or more arrays of memory cells, e.g., non-volatile and/or volatile memory cells. The arrays can be flash arrays with a NAND architecture, for example. Embodiments are not limited to a particular type of memory device. For instance, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.
The embodiment of
Memory device 211 can include a controller and/or control circuitry (e.g., hardware, firmware, and/or software) which can be used to execute commands on the memory device 211. The control circuitry can receive commands from a memory system controller and or cache controller 220. The control circuitry can be configured to execute commands to read and/or write data in the memory device 211.
The cache controller can receive request 340-2 subsequent to request 340-1 and while request 340-1 is being serviced. Request 340-2 can be serviced while request 340-1 is being serviced via the use of buffer 322 that is searchable by the cache controller. For example, requests for the data 330 that is being evicted from cache 310 while servicing request 340-1 can be serviced via buffer 322.
In a number of embodiments, request 340-2 can be a read command requesting data 330. Request 340-2 can be received by the cache controller while request 340-1 is being serviced and evicted data 330 from cache 310. While servicing request 340-1, buffer 322 can be allocated to data 330, buffer 322 can be searchable by the cache controller, and data 330 can be moved to buffer 322. Request 340-2 can be serviced by the cache controller searching buffers to determine if a buffer with data 330 exists 350. In response to determining that data 330 associated with request 340-2 is in buffer 322, request 340-2 can be serviced by returning data 330 from buffer 322.
The cache controller can receive request 440-2 subsequent to request 440-1 and while request 440-1 is being serviced. Request 440-2 can be serviced while request 440-1 is being serviced via the use of buffer 422-1 that is searchable by the cache controller. For example, request 440-2 can be a write command to write data to the cache line in cache 410 where data 430 is being evicted. The cache controller can determine that buffer 422-1 includes data 430 that is being evicted from the cache line in cache 410 where data associated with request 440-2 will be written 450-1. In response to determining that buffer 422-1 includes data 430 that is being evicted from the cache line in cache 410 where data associated with request 440-2 will be written, buffer 422-1 can be masked so that data 430 in buffer 422-1 cannot be used by subsequent requests.
Request 440-2 can continue to be serviced by allocating buffer 422-2 for data associated with request 440-2 in response to determining that buffer 422-1 includes data 430 that is being evicted from the cache line in cache 410 where data associated with request 440-2 will be written 450-1. Data associated with request 440-2 can be written to buffer 422-2 while request is being serviced, where request 440-2 writes data to the cache line in cache 410.
The cache controller can receive request 440-3 subsequent to request 440-2 and request 440-1 and while request 440-2 and/or request 440-1 are being serviced. Request 440-3 can be serviced while request 440-2 and/or request 440-1 are being serviced via the use of buffer 422-2 that is searchable by the cache controller. In a number of embodiments, request 440-3 can be a read command requesting data associated with request 440-2. Request 440-3 can be received by the cache controller while request 440-2 is being serviced by writing data to cache 410. While servicing request 440-2, buffer 422-2 can be allocated to the data associated with request 440-2. Buffer 422-2 can be searchable by the cache controller and data associated with request 440-2 can be written to buffer 422-2 while servicing request 440-2. Request 440-3 can be serviced by the cache controller searching buffers to determine if a buffer with data associated with request 440-3 exists 450-2. In response to determining that data associated with request 440-3 is in buffer 422-2, request 440-3 can be serviced by returning data from buffer 422-2.
The cache controller can receive request 540-2 subsequent to request 540-1 and while request 540-1 is being serviced. Request 540-2 can be serviced while request 540-1 is being serviced via the use of buffer 522 and linked list structure 560 that is searchable by the cache controller. Request 540-2 can be serviced by determining that buffer allocated to data associated with request 540-2 exists 550. In response to determining that buffer 522 is allocated to data associated with request 540-2, entry 562-2 in linked list structure 560 can indicate that the data in buffer 522 is associated with request 540-2. Therefore, once the data is retrieved from memory device 511 and stored in buffer 522, the entry 562-2 in linked list structure 560 can cause request 540-2 to be serviced by returning the data from buffer 522.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
