Patent Application
20200285584
Portable computing devices (“PCDs”) are becoming necessities for people on personal and professional levels. PCDs may include cellular telephones, portable digital assistants, portable game consoles, palmtop computers, and other portable electronic processing devices.
A PCD may have multiple processors or a multi-core processor. Scheduling techniques may be employed to distribute tasks among the cores in accordance with multi-tasking, multi-threading, and similar schemes. As a result of such distribution or scheduling techniques, one or more cores may be inactive or idle while one or more other cores are active. A core may be put into a low-power mode or “power collapse mode” if it remains idle for a relatively long time. The core remains in the power collapse mode until a wake-up event occurs. Wake-up events are generally asynchronous and unpredictable. A wake-up signal may be provided to a core in the form of an interrupt.
Commonly, once it is determined that a core is to enter a power collapse mode, the core's cache memory is flushed before the power supplied to the core is reduced or collapsed. For example, so-called “dirty” cache lines may be flushed one by one to a memory (which may be a system memory or a higher-level cache). If a wake-up signal (e.g., interrupt) occurs before the cache has completed flushing all of the dirty cache lines, the interrupt is withheld from the core until all dirty cache lines have been flushed. More specifically, before the flush begins, the interrupt interface to the core is disabled, and when the flush is completed the interrupt interface is re-enabled. When the interrupt interface is re-enabled, any pending wake-up interrupt is then delivered to the targeted core. As a cache flush is a time-intensive and power-intensive operation, judicious or intelligent algorithms may be used to determine whether it is beneficial in a particular instance to initiate the power collapse mode in a core.
Systems and method are disclosed for aborting a cache flush in a portable computing device (“PCD”).
An exemplary method for aborting a cache flush in a PCD may include initiating a flush operation. The flush operation may include flushing a plurality of cache lines from a cache memory associated with a processor core that is entering a power collapse mode. A wake-up signal associated with the processor core may be asserted before completion of the flush operation, and the method may further include detecting such a wake-up signal. The method may still further include ceasing the flush operation in response to detecting the wake-up signal. The flush operation ceases before the next cache line is flushed from the cache memory.
An exemplary system for aborting a cache flush in a PCD may include a processor core, a cache memory associated with the processor core, and a flush system. The flush system may be configured to control a flush operation. The flush operation relates to flushing a plurality of cache lines from the cache memory in response to the processor core entering a power collapse mode. A wake-up signal associated with the processor core may be asserted before completion of the flush operation, and the flush system may be further configured to detect such a wake-up signal. The flush system may be still further configured to cease the flush operation in response to detecting the wake-up signal. The flush operation cease before the next cache line is flushed from the cache memory.
Another exemplary system for aborting a cache flush in a PCD may include means for initiating a flush operation. The flush operation may include flushing a plurality of cache lines from a cache memory associated with a processor core that is entering a power collapse mode. A wake-up signal associated with the processor core may be asserted before completion of the flush operation, and the system may further include means for detecting such a wake-up signal. The system may still further include means for ceasing the flush operation in response to detecting the wake-up signal. The flush operation ceases before the next cache line is flushed from the cache memory.
In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102A” or “102B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
The terms “central processing unit” (“CPU”), “digital signal processor” (“DSP”), and “graphics processing unit” (“GPU”) are non-limiting examples of processors that may reside in a PCD. These terms are used interchangeably herein except where otherwise indicated. A component, system, subsystem, module, etc., of the PCD may include and operate under the control of such a processor.
As illustrated in
A display controller 110 and a touchscreen controller 112 may be coupled to the CPU 104. A touchscreen display 114 external to the SoC 102 may be coupled to the display controller 110 and the touchscreen controller 112. The PCD 100 may further include a video decoder 116. The video decoder 116 is coupled to the CPU 104. A video amplifier 118 may be coupled to the video decoder 116 and the touchscreen display 114. A video port 120 may be coupled to the video amplifier 118. A universal serial bus (“USB”) controller 122 may also be coupled to CPU 104, and a USB port 124 may be coupled to the USB controller 122. A subscriber identity module (“SIM”) card 126 may also be coupled to the CPU 104.
One or more memories may be coupled to the CPU 104. The one or more memories may include both volatile and non-volatile memories. Examples of volatile memories include static random access memory (“SRAM”) 128 and dynamic RAMs (“DRAM”s) 130 and 131. Such memories may be external to the SoC 102, such as the DRAM 130, or internal to the SoC 102, such as the DRAM 131. A DRAM controller 132 coupled to the CPU 104 may control the writing of data to, and reading of data from, the DRAMs 130 and 131. In other embodiments, such a DRAM controller may be included within a processor, such as the CPU 104.
A stereo audio CODEC 134 may be coupled to the analog signal processor 108. Further, an audio amplifier 136 may be coupled to the stereo audio CODEC 134. First and second stereo speakers 138 and 140, respectively, may be coupled to the audio amplifier 136. In addition, a microphone amplifier 142 may be coupled to the stereo audio CODEC 134, and a microphone 144 may be coupled to the microphone amplifier 142. A frequency modulation (“FM”) radio tuner 146 may be coupled to the stereo audio CODEC 134. An FM antenna 148 may be coupled to the FM radio tuner 146. Further, stereo headphones 150 may be coupled to the stereo audio CODEC 134. Other devices that may be coupled to the CPU 104 include a digital (e.g., CCD or CMOS) camera 152.
A modem or radio frequency (“RF”) transceiver 154 may be coupled to the analog signal processor 108. An RF switch 156 may be coupled to the RF transceiver 154 and an RF antenna 158. In addition, a keypad 160, a mono headset with a microphone 162, and a vibrator device 164 may be coupled to the analog signal processor 108.
A power supply 166 may be coupled to the SoC 102 via a power management integrated circuit (“PMIC”) 168. The power supply 166 may include a rechargeable battery or a DC power supply that is derived from an AC-to-DC transformer connected to an AC power source.
The SoC 102 may have one or more internal or on-chip thermal sensors 170A and may be coupled to one or more external or off-chip thermal sensors 170B. An analog-to-digital converter (“ADC”) controller 172 may convert voltage drops produced by the thermal sensors 170A and 170B to digital signals.
The touch screen display 114, the video port 120, the USB port 124, the camera 152, the first stereo speaker 138, the second stereo speaker 140, the microphone 144, the FM antenna 148, the stereo headphones 150, the RF switch 156, the RF antenna 158, the keypad 160, the mono headset 162, the vibrator 164, the thermal sensors 170B, the ADC controller 172, the PMIC 168, the power supply 166, the DRAM 130, and the SIM card 126 are external to the SoC 102 in this exemplary or illustrative embodiment. It will be understood, however, that in other embodiments one or more of these devices may be included in such an SoC.
As illustrated in
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As illustrated in
Each core 302 may further include a core flush controller 318 that is configured to control a core-level flush operation. Depending upon operating conditions, and as well understood by one of ordinary skill in the art, such a flush operation may involve flushing information from one or both of the L1 caches 310 and 312 to L2 cache 314 or flushing information from the L2 cache 314 to the L3 cache 316. Each core 302 may further include a core flush abort controller 320 and a core interrupt interface 322. The core interrupt interface 322 interfaces with a corresponding controller interrupt interface 324 of the interrupt controller 304. It should be noted that although for purposes of clarity only the first core 302A is explicitly depicted in
The system 300 also includes an L3 or cluster power controller 326 that is configured to control the power supplied to the L3 cache 316 and associated elements. The system 300 further includes an L3 or cluster flush controller 328 that is configured to control a cluster-level flush operation. Such a cluster-level flush operation may involve flushing information from the L3 cache 316 to a system memory, such as the DRAM 130 or 131 shown in
As illustrated in
In the second state 404 one or both (or portions thereof) of the core interrupt interface 322 or the controller interrupt interface 324 (
In the third state 406 the core flush abort controller 320 may monitor for a wake-up event while the cache memory (e.g., L1 cache 310 or 312, or L2 cache 314) associated with the core 302 entering the power-collapse mode is being flushed in the flush operation. Alternatively, or in addition, the cluster flush abort controller 330 may monitor for a wake-up event while the L3 cache 316 is being flushed in the flush operation. The loop in
In the fourth state 408 the flush operation may be aborted. As described in further detail below, initiating or controlling abortion of the flush operation may include the exchange of an Abort signal and an Abort Done or acknowledgement signal. A transition to a fifth state 410 may occur after the flush operation has been aborted.
In the fifth state 410 the condition preventing the wake-up event from waking up the core 302 is removed. For example, the interrupt interface or portion thereof that was disabled as described above with regard to the second state 404 may be re-enabled so that any wake-up or other interrupt signal from the interrupt controller 304 is allowed to reach the core 302. Then, a transition from the fifth state 410 back to the first state 402 may occur.
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For example, as illustrated in
In
In response to the request for the core 302 to enter the power collapse mode, the core flush controller 318 may initiate a flush operation. However, prior to the dirty data being flushed, the core flush abort controller 320 may (e.g., at a time 606) de-assert an Interrupt Interface Enabled signal 608 that is provided to the controller interrupt interface 324 (
At a time 610, following disabling of the interface function between the controller interrupt interface 324 and the core interrupt interface 322, the core flush controller 318 may begin controlling the flushing of dirty data from the L1 caches 310 and 312 or the L2 cache 314, as indicated by the Flush Active signal 612. In accordance with the flush operation, dirty cache lines may be flushed from the L1 caches 310-312 to the L2 cache 314 or from the L2 cache 314 to the L3 cache 316.
At a time 614, which is before the flush operation has completed, a Wake-Up event signal 616 may be asserted in, for example, the manner described above with regard to
At a time 618, the core flush abort controller 320 may assert an Abort Flush signal 620 in response to the Wake-Up event signal 616. In response to the Abort Flush signal 620, the core flush controller 318 may abort the flush operation, i.e., refrain from flushing the next dirty cache line of the one or more dirty cache lines remaining to be flushed in the current flush operation, as indicated by the transition of the Flush Active signal 612 to the inactive state at time 622.
At a time 624, the core flush controller 318 may assert an Abort Done signal 626 to indicate to the core flush abort controller 320 that the flushing of dirty cache lines has ceased (i.e., before the next dirty cache line has been flushed). Although such an instance is not depicted in
At a time 628, with the flush operation having been aborted, the core flush abort controller 320 may then re-assert the Interrupt Interface Enabled signal 608. The re-enabling of the Interrupt Interface Enabled signal 608 removes the condition that caused the controller interrupt interface 324 to block or otherwise refrain from delivering an interrupt request to the core interrupt interface 322.
At or about the same time 628, and also in response to the flush operation having been aborted, the core flush abort controller 320 may assert a Deny Power Collapse Request signal 630. In response to the Deny Power Collapse Request signal 630, the core power controller 306 may terminate the above-described sequence of actions that is undertaken within the power collapse mode, and which normally (i.e., but for aborting the flush operation) begins with initiating the flush operation and ends with reducing or collapsing the supplied power. Thus, although the flush operation has ceased (as indicated by the de-assertion of the Flush Active signal 612 at time 622), the supplied power is not collapsed as it would have been if the flush operation had been completed. At a time 632, the Power Collapse Request signal 604 may be de-asserted in response to the above-mentioned assertion of the Deny Power Collapse Request signal 630. Note that in an instance (not shown) in which the flush operation is not aborted but rather is completed, the Deny Power Collapse Request signal 630 would not be asserted, and the power supplied to the core 302 would be reduced or collapsed at some time following de-assertion of the Flush Active signal 612.
At a time 634, following the re-enabling of the interrupt interface at time 628, an indication of the wake-up event that had been withheld by the controller interrupt interface 324 is delivered to the core interrupt interface 322 in the form of a (wake-up) Interrupt Request signal 636. That is, the re-enabling of the interrupt interface removed the condition preventing the wake-up event from waking up the core 302 from the power collapse mode sequence.
Referring again to
Also, it should be noted that the wake-up signal associated with any core 302 is provided to the cluster power controller 326 and the cluster flush abort controller 330 via an OR gate 336. In this manner, waking up any one or more of cores 302 also has the effect of aborting any flush of the L3 cache 316 that may be in progress (i.e., not completed) at the time a flush operation of the L1 or L2 caches 310-314 is aborted. The same operations described above with regard to aborting a flush operation involving the L1 or L2 caches 310-314 are applicable to aborting a flush operation involving the L3 cache 316, such as the above-described handshake operation. In the case of aborting a cluster-level flush operation, the handshake would occur between the cluster flush controller 328 and the cluster flush abort controller 330.
Referring again to
As illustrated in
Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.
