Cache memory observation device and method of analyzing processor

Abstract

A cache miss judger judges a cache miss when a cache access is executed. An entry region judger judges which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at least a part of an index for selecting an arbitrary cache line in the cache memory. A cache miss counter counts number of the cache misses judged by the cache miss judger in each of the entry regions that is made to correspond to each of the cache accesses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects as well as advantages of the invention will become clear by the following description of preferred embodiments of the invention. A number of benefits not recited in this specification will come to the attention of those skilled in the art upon the implementation of the present invention.

FIG. 1 is a (first) block diagram showing a constitution of a cache memory observation device according to the present invention.

FIG. 2 is a (second) block diagram showing the constitution of the cache memory observation device according to the present invention.

FIG. 3 is a (third) block diagram showing the constitution of the cache memory observation device according to the present invention.

FIG. 4 is a block diagram showing constitutions of a semiconductor integrated circuit and an analyzing device according to a preferred embodiment 1 of to the present invention.

FIG. 5 is a block diagram showing a constitution of a cache memory observation device according the preferred embodiment 1.

FIG. 6A is a (first) calculation diagram which helps understand an operation of the cache memory observation device according the preferred embodiment 1.

FIG. 6B is a (second) calculation diagram which helps understand the operation of the cache memory observation device according the preferred embodiment 1.

FIG. 7A is a (third) calculation diagram which helps understand the operation of the cache memory observation device according the preferred embodiment 1.

FIG. 7B is a (fourth) calculation diagram which helps understand the operation of the cache memory observation device according the preferred embodiment 1.

FIG. 8 is a block diagram showing a constitution of a cache memory observation device according to a preferred embodiment 2 of the present invention.

FIG. 9 is a block diagram showing a constitution of a cache memory observation device according to a preferred embodiment 3 of the present invention.

FIG. 10 is a block diagram showing constitutions of a semiconductor integrated circuit and an analyzing device according to a conventional technology.

FIG. 11 is a block diagram showing a constitution of a cache memory observation device according to the conventional technology.

Claims

1. A cache memory observation device for observing a cache access executed to a cache memory comprising a plurality of cache entries comprising: a cache miss judger for judging a cache miss when the cache access is executed;an entry region judger for judging which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at least a part of an index for selecting an arbitrary cache line in the cache memory; anda cache miss counter for counting number of the cache misses judged by the cache miss judger in each of the entry regions which is made to correspond to each of the cache accesses by the entry region judger.

2. The cache memory observation device according to claim 1, further comprising a particular address space judger for judging whether or not the cache access is an access to a particular address space previously set by comparing an address of the cache access to a tag address of the cache memory, wherein the cache miss counter counts the number of the cache misses in the cache access judged to be the access to the particular address space through the particular address space judger by each of the entry regions.

3. The cache memory observation device according to claim 2, wherein the particular address judger compares high-order bits of the address of the cache access to high-order bits of the tag address of the cache memory.

4. The cache memory observation device according to claim 2, wherein the particular address space includes one or a plurality of entry regions.

5. The cache memory observation device according to claim 1, further comprising: a cache miss repetition entry judger for judging the entry region where the many cache miss are generated based on a counting result of the cache misses by the cache miss counter; anda complementary cache line allocator for dynamically allocating a complementary cache line to the cache entry constituting the entry region judged to cause repetition of the cache miss by the cache miss repetition entry judger.

6. The cache memory observation device according to claim 1, wherein the cache miss counter comprises: a counter provided with respect to each of divided regions obtained by dividing the entry region into one or a plurality of pieces; anda counter designator for designating an arbitrary counter using the index from the one or the plurality of counters in accordance with the divided region, whereinthe cache miss counter counts the number of the cache misses judged by the cache miss judger by each of the counters designated by the counter designator.

7. The cache memory observation device according to claim 6, wherein the counter designator designates an arbitrary counter from the plurality of counters using a few bits on a highest-order side of the index.

8. The cache memory observation device according to claim 6, wherein the counter designator designates an arbitrary counter from the plurality of counters using a few bits on a lowest-order side of the index.

9. A method of analyzing a processor by observing a cache access executed with respect to a cache memory comprising a plurality of cache entries, comprising: a first step for inputting an execution program to a processor analyzing device;a second step for designating at least a part of an index included in an address for selecting an arbitrary cache line in the cache memory in order to count the cache miss in each of the cache entry regions;a third step for judging which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses in the execution of the program using at least a part of the index designated in the second step;a fourth step for checking a distribution of the cache misses by judging the cache miss and counting number of the cache misses in each of the entry regions corresponding to each of the cache accesses in the execution of the program; anda fifth step for outputting the distribution of the cache misses.

10. The method of analyzing the processor according to claim 9, further comprising: a sixth step for designating a particular address space that is made an investigation target with respect to the distribution of the cache misses is to be investigated; anda seventh step for judging whether or not the cache access is an access to the particular address space designated in the sixth step by comparing an address of the cache access to a tag address of the cache memory, whereinthe number of the cache misses in the cache access judged in the seventh step to be the access to the particular address space designated in the sixth step is counted by each of the cache entry regions in the fourth step.

11. A cache memory comprising a plurality of cache entries, comprising: a cache miss judger for judging a cache miss when a cache access is made to the cache memory;an entry region judger for judging which of a plurality of entry regions constituted with one or a plurality of cache entries in the cache memory is accessed by each of the cache accesses using at least apart of an index included in an address for selecting an arbitrary cache line in the cache memory; anda cache miss counter for counting number of the cache misses judged by the cache miss judger in each of the entry regions which is made to correspond to each of the cache accesses by the entry region judger;a cache miss repetition entry judger for judging the entry region where the many cache miss is caused based on a counting result of the cache misses by the cache miss counter; anda complementary cache line allocator for dynamically allocating a complementary cache line to the cache entry constituting the entry region judged to cause the repetition of the cache miss by the cache miss repetition entry judger.