Patent Application
20080010408
For instance, long cache lines typically perform better with large data structures. Thus, at 104, if it is determined that the application uses large data structures or a large region of allocated memory, the larger cache line configuration, is selected for this application. Data structure layout and sharing pattern may be analyzed on a multiprocessor to determine the optimal coherence granularity if for example a programmer has not performed cache alignment. By varying the coherence granularity the application behavior can be significantly improved. Many operating system data structures are small. Thus, when an operating system is executing, or any other application that uses smaller data structure is executing, the cache may be reconfigured to have smaller cache lines or smaller coherence granularity at 106.
In addition, if it is determined that the application is consuming high power or generating high heat, a part of the cache may be reconfigured to be disabled at 108, so that, for example, the chip will not get too hot. In some applications the critical working set is not the entire cache, so that performance need not be sacrificed to achieve a reduction in power usage or to reduce the temperature. Temperature sensors placed on or near processor cores may be used to determine how much heat an application is generating. A part of the cache may be disabled, for example, by setting enable/disable bit or bits to be associated with cache memory locations. The hardware or software accessing the cache then may read those bits to determine whether that part of the cache may be used or not used.
At 110, cache associativity may be reconfigured based on the type of execution entity. For instance, different types of applications may perform better with certain associativity. Associativity may be reconfigured, for example, by modifying a hashing algorithm or masking-off more or less number of bits in virtual or physical addresses for determining index and tag portions of associative cache memory. Although a higher associativity may mean a power cost and potentially a cycle cost, for applications that can benefit from a higher degree of associativity, there is potentially a considerable performance advantage that outweighs the power and cycle cost. For other applications a lower associativity will still achieve good performance, thus for those applications, the software or operating system can reduce the associativity and save power.
Reconfigurations with respect to other characteristics of cache memory are possible. At 112, cache memory is reconfigured, for instance, based on the determinations made above. The reconfiguration, in one embodiment, may be done by the hardware on the processor. The hardware, for instance, takes the information determined as above from the software and performs the modifications. A register may be set up per cache where the software may provide the hints for reconfiguring the cache memory.
Referring to
In one embodiment, software may provide appropriate granularity information indicating that requested data in a memory region should be fetched with a suggested granularity. For example, software may indicate that, in case of an L1 cache miss on any address in a memory region, only the requested sector to be fetched from the corresponding L2 cache 206. As another example, software may also indicate that, in case of an L1 cache miss on any address in another memory region, the whole cache line, that is, all four sectors should be fetched from the corresponding L2 cache 206. In one embodiment, the granularity information may be maintained in tables such as a TLB (Translation Lookaside Buffer), the page table or the like, for instance, if a memory region is defined as one or more memory pages.
In another embodiment, each L2 cache line maintains a granularity flag (GF) that indicates which one or more sectors of the requested cache line should be supplied to the L1 cache when the L2 cache 206 receives a cache request from the corresponding L1 cache 202.
At the L1 cache side, each L1 cache line maintains an access flag (AF) for each sector, indicating whether the corresponding cache sector has been accessed by the corresponding CPU since the time the data was cached.
Further, when an L1 cache line is replaced, the AF flags can be used to update the corresponding GF flags in the L2 cache. For instance, take for example, the cache line 400 of
Although the above examples were described with respect to L1 cache as a requester and L2 cache as a supplier of data, it should be understood that the scheme explained above may be used between any levels of caches, for instance, between L2 and L3 caches, L3 cache and main memory, L2 cache and main memory, etc.
Splitting a cache line into a plurality of sectors helps in reducing the number of cache misses as well as the number of operations required to maintain cache coherence. For instance, two processors that access the same cache line, but different sectors in the line may perform updates to the respective sectors independently from one another without having to invalidate the other's cache line.
The embodiments described above are illustrative examples and it should not be construed that the present invention is limited to these particular embodiments. Thus, various changes and modifications may be effected by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.
This invention was made with Government support under Contract No.: NBCH020056 (DARPA) awarded by Defense, Advanced Research Projects Agency. The Government has certain rights in this invention.
