Claims
- 1. An apparatus for reducing latency problems in a cache system, comprising:
- a system bus;
- memory coupled to said system bus;
- a processor coupled to said system bus which can access said memory using said system bus;
- a cache system coupled between said processor and said system bus which generates a read allocation request to allocate data into the cache system and snoops addresses presented to its address inputs, wherein said cache system also services requests from said processor when said processor is not using said system bus; and
- means coupled to said cache system for gaining access to said cache system address inputs for snooping purposes immediately after said cache system generates a read allocation request.
- 2. The apparatus of claim 1, further comprising:
- means coupled to said cache system for terminating access to said cache system address inputs when said read allocation is completed.
- 3. The apparatus of claim 2, further comprising:
- a second cache system coupled between said cache system and said system bus; and
- means coupled to said cache system and to said second cache system for terminating access to said cache system address inputs when a read hit occurs to said second cache system.
Parent Case Info
This is a divisional, of application Ser. No. 07/839,853, filed Feb. 21, 1992.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5119485 |
Ledbetter, Jr. et al. |
Jun 1992 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
0090575 |
Oct 1983 |
EPX |
0288649 |
Nov 1988 |
EPX |
Non-Patent Literature Citations (2)
Entry |
Practical Cache Design Techniques for Today's RISC and CISC CPUS, Jim Handy, Electro Conference Record, vol. 16, Apr. 16, 1991, pp. 283-288. |
Futurebus+ Cache Coherence Jay Cantrell, Ire Wescon Convention Record, vol. 34, Nov., 1990, pp. 90-94. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
839853 |
Feb 1992 |
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