The present invention relates generally to memory sense amplifiers, and, more particularly, to a capacitively isolated mismatch compensated sense amplifier.
In dynamic random access memory (DRAM) devices, a sense amplifier is typically utilized to sense the voltage on a common bitline connected to each DRAM storage cell that comprises a storage capacitor and a transistor. The transistor selectively switches the stored capacitor voltage value onto the bitline when that cell is addressed during a read operation. The storage capacitor stores the relatively small voltage value that represents a logical binary “0” or “1” value. As semiconductor device technology continues to evolve towards providing smaller device sizes and more devices per integrated circuit (IC) (and thus smaller voltages utilized within the circuits within the IC), the inherent mismatch in the threshold voltage between the several transistors that typically comprise a sense amplifier becomes increasing difficult and important to properly compensate for.
According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.
Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
Referring to
With respect to the first amplifier stage 102, the bitline 106 connects to both an isolation capacitor 114 and a capacitor shunt switch 116, where the capacitor 114 and the shunt switch 116 are connected in parallel. In accordance with an embodiment of the invention, the value of the capacitor 114 may be approximately ten times larger than the input capacitance of a gated inverter 132. The capacitor shunt switch 116 may include an NFET 118 and a PFET 120 connected in parallel. The gate of the NFET 118 is controlled by a signal, sh, while the gate of the PFET 120 is controlled by a signal, sh_b. The function of the capacitor shunt switch 116 is described hereinafter. The output side of the capacitor 114 and the capacitor shunt switch 116 connect together at a signal node, sn0122. Four transistors 124-130 connect in series between a supply voltage, Vdd and ground. The four transistors 124-130 form the gated inverter 132 of the first amplifier stage 102. The signal node, sn0122, connects to the gate of the transistors 126-128, which function as amplifiers. Thus, the signal node, sn0122, is the input to the gated inverter 132 of the first amplifier stage 102. The other two transistors 124, 130 function as power gates as part of the gated inverter 132. The connection point between the transistors 126-128 forms an output on a line 134 of the first amplifier stage 102. The gate of the transistor 124 is controlled by a signal, set_b0, while the gate of the transistor 130 is controlled by a signal, set0. The first amplifier stage 102 also includes a preset switch or inverter shunt device 136 formed by an NFET 138 and a PFET 140 connected in parallel. An input side of the preset switch 136 connects to the signal node, sn0122, while an output side of the preset switch 136 connects to the output 134 of the first amplifier stage 102. The gate of the NFET 138 is controlled by a signal, pre, while the gate of the PFET 140 is controlled by a signal, pre_b.
As mentioned, the second amplifier stage 104 may be identical to the first amplifier stage 102. The output signal 134 from the first amplifier stage 102 connects at an input of the second amplifier stage 104. The second amplifier stage 104 includes a capacitor 142 and a capacitor shunt switch 144 that comprises an NFET 146 and a PFET 148. A signal node, sn1150, is provided. Four transistors 152-158 connect in series and form a gated inverter 160 of the second amplifier stage 104, the output of which is provided on a line 110. Thus, the signal node, sn1150, is the input to the gated inverter 160 of the second amplifier stage 104. A preset switch or inverter shunt device 162 includes an NFET 164 and a PFET 166. The various gate control signals provided to the various transistors within the second amplifier stage 104 are indicated in
The output signal on the line 110 from the second amplifier stage 104 connects to an input of the write back switch 112, which includes an NFET 170 and a PFET 172 connected in parallel. The gate of the NFET 170 is controlled by a signal, wb, while the gate of the PFET 172 is controlled by a signal, wb_b 172. The output of the write back switch 112 connects back to the bitline 106.
The operation of the sense amplifier circuit arrangement 100 is best understood by a description of the various modes of operation of the first and second amplifier stages 102-104 and the write back switch 112.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Number | Name | Date | Kind |
---|---|---|---|
5168461 | Wu et al. | Dec 1992 | A |
5381364 | Chern et al. | Jan 1995 | A |
5959878 | Kamp | Sep 1999 | A |
6181621 | Lovett | Jan 2001 | B1 |
6191989 | Luk et al. | Feb 2001 | B1 |
6674328 | Uto et al. | Jan 2004 | B2 |
6819600 | Sim | Nov 2004 | B2 |
7123531 | Rho | Oct 2006 | B2 |
7164612 | Eleyan et al. | Jan 2007 | B1 |
7221605 | Forbes | May 2007 | B2 |
7227798 | Gupta et al. | Jun 2007 | B2 |
7286416 | Ooishi et al. | Oct 2007 | B2 |
20030112684 | Barth, Jr. | Jun 2003 | A1 |
20040037138 | Barth, Jr. | Feb 2004 | A1 |
20050237400 | Blerkom et al. | Oct 2005 | A1 |
20060119329 | Jacobs et al. | Jun 2006 | A1 |
20060262622 | Forbes | Nov 2006 | A1 |
20070025170 | Barth, Jr. et al. | Feb 2007 | A1 |
20070097768 | Barth, Jr. | May 2007 | A1 |
20080116966 | Chae et al. | May 2008 | A1 |
Number | Date | Country |
---|---|---|
928056 | Jul 1999 | EP |
Number | Date | Country | |
---|---|---|---|
20100157698 A1 | Jun 2010 | US |