Patent Application
20140033149
The invention relates to circuit design and, more particularly, to systems and methods for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools.
As technology continues to scale into the sub-micron realm, applications move toward higher frequencies and higher levels of integration such that parasitic effects from interconnect wiring significantly affect integrated circuit performance. For example, the parasitic effects from interconnect wiring play an important role in timing, power, gain, matching network, reliability, and noise performance of the integrated circuit such that the parasitic effects from interconnect wiring can no longer be ignored or the integrated circuit may fail.
Specifically, one of the challenges faced by submicron integrated circuit designers is the issue of parasitic effects from the interconnect wiring between a semiconductor die or chip and a chip package, e.g., chip-package coupling. More specifically, the interaction between a semiconductor die or chip when packaged using flip chip technology can cause a significant parasitic coupling effect between the chip and the package due to the fact that the chip and package (solder bumps and the first package metal layer) are located in very close proximity. A chip is semiconductor material, e.g., silicon, in which an integrated circuit is formed, and a chip package is the substrate upon which the chip, or chips, is mounted, e.g., a ceramic laminate package, or printed circuit board. The chip package provides a means of connecting the internal chip components to external circuitry. The chip-package coupling has become a major factor in successfully predicting performance of the integrated circuit on the chip.
In order to take parasitic effects from interconnect wiring into consideration during post layout analysis of an integrated circuit, it is necessary to create electrical models for the physical connections present between the various devices in the integrated circuit design. This process is typically known as parasitic extraction (PEX). However, traditional PEX methodologies only capture chip level couplings and by default assume a mounted package without taking into account mutual coupling effects between the chip and the chip package.
Common practice in order to take into account the chip-package coupling in predicting performance of an integrated circuit includes using an electromagnetic (EM) simulator to model chip package effects and to evaluate the chip-package coupling. However, EM simulation capability is limited by the complexity of interconnect wiring structures. Additionally, package metal routing is commonly modeled by 3-D EM tools, while chip-level parasitics are usually modeled by EDA PEX tools. The integration of an EM model netlist derived from 3-D EM tools and an on chip parasitic netlist derived from EDA PEX tools into simulations is typically a challenge due to different formats from tool vendors, interface restrictions, etc. Furthermore, stand-alone models of chip packages do not take into account mutual coupling effects between the chip and the chip package.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
In a first aspect of the invention, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method comprises compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method further comprises generating a parasitic technology file to include the compiled process technology parameters.
In another aspect of the invention, a method is provided for post-design testing and optimization of an integrated circuit chip. The method comprises completing a design and layout of the integrated circuit chip. The method further comprises initiating a parasitic extraction for the integrated circuit chip, including compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip, and generating a parasitic technology file including the compiled process technology parameters. The method further comprises generating a parasitic extraction result. The method further comprises inputting the parasitic extraction result into a post-layout simulation.
In yet another aspect of the invention, a method is provided that is implemented in a computer-aided design system for generating a functional design model of an integrated circuit chip. The method comprises defining a parasitic technology file containing elements that define at least one metal layer of an integrated circuit chip package. The method further comprises writing process technology parameters that describe electrical behavior for regions of the integrated circuit chip, the integrated circuit chip package, and chip-package coupling into the parasitic technology file.
The present invention is described in the detailed description, which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.
The invention relates to circuit design and, more particularly, to systems and methods for capturing mutual coupling effects between an integrated circuit (IC) chip and chip package using electronic design automation (EDA) tools. More specifically, the present invention provides a methodology for incorporating IC package modeling into an integrated circuit layout parasitic network for a flip chip design.
PEX accuracy and design automation enablement have become more critical with the increase in performance, density, complexity, and levels of integration in submicron designs of integrated circuit, e.g., analog mixed-signal and radio frequency (RF) designs. Accordingly, implementations of the invention provide for methods to generate comprehensive parasitic technology files that account for the coupling effects between the chip and package in the design kit. These methods can be utilized by different process technologies or systems and different EDA tools to effectively and efficiently model the chip package coupling effects and to evaluate the chip-package coupling.
In designing the chip 105 of
In embodiments, the systems and methods of the invention allow for post-layout simulations incorporating chip and chip package interactions simultaneously. Advantageously, implementations of the invention enable modeling of the mutual coupling between on-chip circuits and the chip package. Even more advantageously, implementations of the invention provide a truly comprehensive extraction solution that allows design houses to have reliable parasitic analysis, reduced silicon spins, and accelerated time to market.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program instructions may also be stored in the computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The computing device 314 also includes a processor 320, memory 322A, an I/O interface 324, and a bus 326. The memory 322A can include local memory employed during actual execution of program code, bulk storage, and cache memories, which provide temporary storage of at least some program code, in order to reduce the number of times code should be retrieved from bulk storage during execution. In addition, the computing device includes random access memory (RAM), a read-only memory (ROM), and an operating system (O/S).
The computing device 314 is in communication with the external I/O device/resource 328 and the storage system 322B. For example, the I/O device 328 can comprise any device that enables an individual to interact with the computing device 314 (e.g., user interface) or any device that enables the computing device 314 to communicate with one or more other computing devices using any type of communications link. The external I/O device/resource 328 may be for example, a handheld device, PDA, handset, keyboard, etc.
In general, the processor 320 executes computer program code (e.g., program control 344), which can be stored in the memory 322A and/or storage system 322B. Moreover, in accordance with aspects of the invention, the program control 344 controls EDA tools 350 to perform the processes described herein. The EDA tools 350 can be implemented as one or more program code in the program control 344 stored in memory 322A as separate or combined modules. Additionally, the EDA tools 350 may be implemented as a separate dedicated processor or several processors to provide the function of these tools. While executing the computer program code, the processor 320 can read and/or write data to/from memory 322A, storage system 322B, and/or I/O interface 324. The program code executes the processes of the invention. The bus 326 provides a communications link between each of the components in the computing device 314.
In embodiments, the EDA tools 350 can extract parasitics of an integrated circuit including capturing mutual coupling effects between the integrated circuit chip and the chip package. For example, in accordance with aspects of the invention, the EDA tools 350 can compile process technology parameters for regions of the integrated circuit chip, the chip-packaging coupling, and the chip package, and generate a comprehensive parasitic technology file comprising the compiled process technology parameters.
Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. The software and/or computer program product can be implemented using a computing device. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable storage medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disc-read/write (CD-R/W) and DVD.
In embodiments, the compiled information may include fabrication process parameters of various conductor layers (e.g., metal layers, interconnect wiring layers, or conductors) such as a minimum spacing and minimum width of the conductors, a thickness of the conductor layers, heights of the conductor layers above the semiconductor substrate, the resistivities of the conductor layers, the interlayer dielectric constant and thickness (in embodiments the dielectric constant may be selected as air), the name of a top conductor layer of a via, a bottom conductor layer of the via, contact resistance of the via, the names of wells, etc. The fabrication process parameters (e.g., electrical parameters of the conductor layers) for the chip package may be provided by a package vendor. The chip package and chip-package coupling information including the fabrication process parameters of the various conductor layers are then formatted such that the information can be included in a comprehensive parasitic or interconnect technology file (e.g., written to a configuration file).
At step 410, at least one conductor layer of the chip package is provided in a design kit. In embodiments, the at least one conductor layer is provided in the design kit such that the at least one conductor layer can be used for interconnecting circuit elements of the integrated circuit chip, the chip package, and the chip-package coupling. For example, a design kit may be modified to include at least one conductor layer of the chip package such that a chip designer or an automated program may use the at least one conductor layer defined in the parasitic technology file as a circuit interconnect layer such that the at least one conductor layer and the associated fabrication process parameters become integrated with the chip. Consequently, a parasitic extraction tool (e.g., EDA Tool 350 as described with respect to
At step 415, the parasitic technology file is generated for the integrated circuit such that the file comprises all process technology parameters that describe electrical behavior for regions of the integrated circuit chip, the chip package, and the chip-package coupling. In embodiments, generating the parasitic technology file includes defining at least one conductor layer (e.g., a metal layer or interconnect wiring layer) of the chip package, which has a dominant coupling effect to the integrated circuit chip. Additionally, all process technology parameters that describe electrical behavior for the integrated circuit chip and the compiled information including all process technology parameters that describe electrical behavior for regions of the chip package and the chip-package coupling are written or coded into the parasitic technology file.
In embodiments, a solder ball, the region of the chip-package coupling/connection (e.g., the region from the last on-chip metal layer to the first package metal layer) is treated as a device model in the parasitic technology file and is netlisted like a device in post layout simulations. For example, treating the region of the chip-package coupling as a device model provides for flexibility to insert compact modeling calculations (e.g., Spice models) for the device model of the chip-package coupling and enhanced control of the accuracy and complexity of the chip-package coupling based on different design sensitivities.
At step 420, an effective ground plane reference is defined in the parasitic technology file. In embodiments, the ground plane reference is defined in the parasitic technology file to be sufficiently separated from the chip interconnect wiring layers and active devices such that the ground plane reference does not contribute significant capacitive coupling during simulation (e.g., there may be some parasitics to the ground plane calculated, but the parasitics will be very small relative to other parasitics calculated for the chip-package). Specifically, the ground plane reference may be defined 700 μm from the active devices during simulation. Preferably, the ground plane reference is defined at least 250 μm from the active devices or depends on real ground wafer thickness.
At step 425, a calibration process is performed on the parasitic technology file. In embodiments, this is performed by calibrating a capacitance table to have a parasitic capacitance value matching that of an actual contact/via configuration in an integrated circuit chip as should be understood by one of ordinary skill in the art such that no further explanation is needed.
As described herein, the parasitic technology file typically comprises layer thickness, dielectric constants, metal resistivities, via resistivities, etc. for regions of the chip including the interconnect wiring layers 630 and 635. However, in accordance with aspects of the invention, the parasitic technology file is also generated to comprise layer thicknesses, dielectric constants, metal resistivities, via resistivities, etc. for the region 655 between the top interconnect wiring layer 630 and the top of the chip package 605 in order to include the process parameters of various conductor layers in the chip package 605 and the chip-package coupling 620. Advantageously, implementations of the invention provide a truly comprehensive extraction solution and enable modeling of the mutual coupling between on-chip circuits and the chip package.
Design flow 1300 may vary depending on the type of representation being designed. For example, a design flow 1300 for building an application specific IC (ASIC) may differ from a design flow 1300 for designing a standard component or from a design flow 1300 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 1310 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures to generate a netlist 1380, which may contain design structures such as design structure 1320. Netlist 1380 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 1380 may be synthesized using an iterative process in which netlist 1380 is re-synthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 1380 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.
Design process 1310 may include hardware and software modules for processing a variety of input data structure types including netlist 1380. Such data structure types may reside, for example, within library elements 1330 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 1340, characterization data 1350, verification data 1360, design rules 1370, and test data files 1385 that may include input test patterns, output test results, and other testing information. Design process 1310 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 1310 without deviating from the scope and spirit of the invention. Design process 1310 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 1310 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 1320 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 1390.
Design structure 1390 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 1320, design structure 1390 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more devices. In one embodiment, design structure 1390 may comprise a compiled, executable HDL simulation model that functionally simulates the devices.
Design structure 1390 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 1390 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure. Design structure 1390 may then proceed to a stage 1395 where, for example, design structure 1390: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
