Channel scheduling in optical routers

Abstract

An optical switch network (4) includes optical routers (10), which route information in optical fibers (12). Each fiber carries a plurality of data channels (20), collectively a data channel group (14), and a control channel (16). Data is carried on the data channels in data bursts and control information is carried on the control channel (18) in burst header packets. A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Parallel scheduling at multiple delays may be used for faster scheduling. In one embodiment, unscheduled times and gaps may be processed in a unified memory for more efficient operation.

Description

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0004] Not Applicable

BACKGROUND OF THE INVENTION

[0005] 1. TECHNICAL FIELD

[0006] This invention relates in general to telecommunications and, more particularly, to a method and apparatus for optical switching.

[0007] 2. DESCRIPTION OF THE RELATED ART

[0008] Data traffic over networks, particularly the Internet, has increased dramatically recently, and will continue as the user increase and new services requiring more bandwidth are introduced. The increase in Internet traffic requires a network with high capacity routers capable of routing data packets of variable length. One option is the use of optical networks.

[0009] The emergence of dense-wavelength division multiplexing (DWDM) technology has improved the bandwidth problem by increasing the capacity of an optical fiber. However, the increased capacity creates a serious mismatch with current electronic switching technologies that are capable of switching data rates up to a few gigabits per second, as opposed to the multiple terabit per second capability of DWDM. While emerging ATM switches and IP routers can be used to switch data using the individual channels within a fiber, typically at a few hundred gigabits per second, this approach implies that tens or hundreds of switch interfaces must be used to terminate a single DWDM fiber with a large number of channels. This could lead to a significant loss of statistical multiplexing efficiency when the parallel channels are used simply as a collection of independent links, rather than as a shared resource.

[0010] Different approaches advocating the use of optical technology in place of electronics in switching systems have been proposed; however, the limitations of optical component technology has largely limited optical switching to facility management/control applications. One approach, called optical burst-switched networking, attempts to make the best use of optical and electronic switching technologies. The electronics provides dynamic control of system resources by assigning individual user data bursts to channels of a DWDM fiber, while optical technology is used to switch the user data channels entirely in the optical domain.

[0011] Previous optical networks designed to directly handle end-to-end user data channels have been disappointing.

[0012] Therefore, a need has arisen for a method and apparatus for providing an optical burst-switched network.

BRIEF SUMMARY OF THE INVENTION

[0013] The present invention provides circuitry for scheduling data bursts in an optical burst-switched router. An optical switch routes optical information from an incoming optical transmission medium to one of a plurality of outgoing optical transmission media. A delay buffer coupled to the optical switch provides n different delays for delaying information between the incoming transmission medium and the outgoing transmission media. A scheduling circuit is associated with each outgoing medium; the scheduling circuits each comprise n+1 associative processors. Each associative processor includes circuitry for (1) storing scheduling information for the associated outgoing optical transmission medium relative to a respective one of the n delays and for a zero delay and (2) identifying available time periods relative to the respective delays in which a data burst may be scheduled.

[0014] The present invention provides a fast and efficient method for scheduling bursts in an optical burst-switched router.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0015] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0016] FIG. 1 a is a block diagram of an optical network;

[0017] FIG. 1 b is a block diagram of a core optical router;

[0018] FIG. 2 illustrates a data flow of the scheduling process;

[0019] FIG. 3 illustrates a block diagram of a scheduler;

[0020] FIGS. 4 a and 4b illustrate timing diagrams of the arrival of a burst header packet relative to a data burst;

[0021] FIG. 5 illustrates a block diagram of a DCS module;

[0022] FIG. 6 illustrates a block diagram of the associative memory of PM;

[0023] FIG. 7 illustrates a block diagram of the associative memory of PG;

[0024] FIG. 8 illustrates a flow chart of a LAUC-VF scheduling method;

[0025] FIG. 9 illustrates a block diagram of a CCS module;

[0026] FIG. 10 illustrates a block diagram of the associative memory of PT;

[0027] FIG. 11 illustrates a flow chart of a constrained earliest time method of scheduling the control channel;

[0028] FIG. 12 illustrates a block diagram of the path & channel selector;

[0029] FIG. 13 illustrates a example of a blocked output channel through the recirculation buffer;

[0030] FIG. 14 illustrates a memory configuration for a memory of the BHP transmission module;

[0031] FIG. 15 illustrates a block diagram of an optical router architecture using passive FDL loops;

[0032] FIG. 16 illustrates an example of a path & channel scheduler with multiple PM and PG pairs;

[0033] FIGS. 17 a and 17b illustrate timing diagram of outbound data channels;

[0034] FIG. 18 illustrates clock signals for CLKf and CLKs;

[0035] FIGS. 19 a and 19b illustrate alternative hardware modifications for slotted operation of a router;

[0036] FIG. 20 illustrates a block diagram of an associative processor PM;

[0037] FIG. 21 illustrates a block diagram of an associative processor PG;

[0038] FIG. 22 illustrates a block diagram of an associative processor PMG;

[0039] FIG. 23 illustrates a block diagram of an associative processor P*MG;

[0040] FIG. 24 illustrates a block diagram of an embodiment using multiple associative processors for fast scheduling;

[0041] FIG. 25 illustrates a block diagram of a processor PM-ext for use with multiple channel groups; and

[0042] FIG. 26 illustrates a block diagram of a processor PG-ext for use with multiple channel groups.

DETAILED DESCRIPTION OF THE INVENTION

[0043] The present invention is best understood in relation to FIGS. 1-26 of the drawings, like numerals being used for like elements of the various drawings.

[0044] FIG. 1 a illustrates a general block diagram of an optical burst switched network 4. The optical burst switched (OBS) network 4 includes multiple electronic ingress edge routers 6 and multiple egress edge routers 8. The ingress edge routers 6 and egress edge routers 8 are coupled to multiple core optical routers 10. The connections between ingress edge routers 6, egress edge routers 8 and core routers 10 are made using optical links 12. Each optical fiber can carry multiple channels of optical data.

[0045] In operation, a data burst (or simply “burst”) of optical data is the basic data block to be transferred through the network 4. Ingress edge routers 6 and egress edge routers 8 are responsible for burst assembly and disassembly functions, and serve as legacy interfaces between the optical burst switched network 4 and conventional electronic routers.

[0046] Within the optical burst switched network 4, the basic data block to be transferred is a burst, which is a collection of packets having some common attributes. A burst consists of a burst payload (called “data burst”) and a burst header (called “burst header packet” or BHP). An intrinsic feature of the optical burst switched network is that a data burst and its BHP are transmitted on different channels and switched in optical and electronic domains, respectively, at each network node. The BHP is sent ahead of its associated data burst with an offset time τ (≧0). Its initial value, τ0, is set by the (electronic) ingress edge router 8.

[0047] In this invention, a “channel” is defined as a certain unidirectional transmission capacity (in bits per second) between two adjacent routers. A channel may consist of one wavelength or a portion of a wavelength (e.g., when time-division multiplexing is used). Channels carrying data bursts are called “data channels”, and channels carrying BHPs and other control packets are called “control channels”. A “channel group” is a set of channels with a common type and node adjacency. A link is defined as a total transmission capacity between two routers, which usually consists of a “data channel group” (DCG) and a “control channel group” (CCG) in each direction.

[0048] FIG. 1 b illustrates a block diagram of a core optical router 10. The incoming DCG 14 is separated from the CCG 16 for each fiber 12 by demultiplexer 18. Each DCG 14 is delayed by a fiber delay line (FDL) 19. The delayed DCG is separated into channels 20 by demultiplexer 22. Each channel 20 is input to a respective input node on a non-blocking spatial switch 24. Additional input and output nodes of spatial switch 24 are coupled to a recirculation buffer (RB) 26. Recirculation buffer 26 is controlled by a recirculation switch controller 28. Spatial switch 24 is controlled by a spatial switch controller 30.

[0049] CCGs 14 are coupled to a switch control unit (SCU) 32. SCU includes an optical/electronic transceiver 34 for each CCG 14. The optical/electronic transceiver 34 receives the optical CCG control information and converts the optical information into electronic signals. The electronic CCG information is received by a packet processor 36, which passes information to a forwarder 38. The forwarder for each CCG is coupled to a switch 40. The output nodes of switch 40 are coupled to respective schedulers 42. Schedulers 42 are coupled to a Path & Channel Selector 44 and to respective BHP transmit modules 46. The BHP transmit modules 46 are coupled to electronic/optical transceivers 48. The electronic/optical transceivers produce the output CCG 52 to be combined with the respective output DCG 54 information by multiplexer 50. Path & channel selector 44 is also coupled to RB switch controller 28 and spatial switch controller 30.

[0050] The embodiment shown in FIG. 1b has N input DCG-CCG pairs and N output DCG-CCG pairs 52, where each DCG has K channels and each CCG has only one channel (k=1). A DCG-CCG pair 52 is carried in one fiber. In general, the optical router could be asymmetric, the number of channels k of a CCG 16 could be larger than one, and a DCG-CCG pair 52 could be carried in more than one fiber 12. In the illustrated embodiment, there is one buffer channel group (BCG) 56 with R buffer channels. In general, there could be more than one BCG 56. The optical switching matrix (OSM) consists of a (NK+R)×(NK+R) spatial switch and a R×R switch with WDM (wavelength division multiplexing) FDL buffer serving as recirculation buffer (RB) 26 to resolve data burst contentions on outgoing data channels. The spatial switch is a strictly non-blocking switch, meaning that an arriving data burst on an incoming data channel can be switched to any idle outgoing data channel. The delay Δ introduced by the input FDL 19 should be sufficiently long such that the SCU 32 has enough time to -process a BHP before its associated data burst enters the spatial switch.

[0051] The R×R RB switch is a broadcast-and-select type switch of the type described in P. Gambini, et al., “Transparent Optical Packet Switching Network Architecture and Demonstrators in the KEOPS Project”, IEEE J. Selected Areas in Communications, vol. 16, no. 7, pp. 1245-1259, September 1998. It is assumed that the R×R RB switch has B FDLs with the ith FDL introducing Q1 delay time, 1≦i≦B. It is further assumed without loss of generality that Q1<Q2< . . . <QB and Q0 =0, meaning no FDL buffer is used. Note that the FDL buffer is shared by all N input DCGs and each FDL contains R channels. A data burst entering the RB switch on any incoming channel can be delayed by one of B delay times provided. The recirculation buffer in FIG. 1b can be degenerated to passive FDL loops by removing the function of RB switch, as shown in FIG. 15, wherein different buffer channels may have different delays.

[0052] The SCU is partially based on an electronic router. In FIG. 1b, the SCU has N input control channels and N output control channels. The SCU mainly consists of packet processors (PPs) 36, forwarders 38, a switching fabric 40, schedulers 42, BHP transmission modules 46, a path & channel selector 44, a spatial switch controller 30, and a RB switch controller 28. The packet processor 36, the forwarders 38, and the switching fabric 40 can be found in electronic routers. The other components, especially the scheduler, are new to optical routers. The design of the SCU uses the distributed control as much as possible, except the control to the access of shared FDL buffer which is centralized.

[0053] The packet processor performs layer 1 and layer 2 decapsulation functions and attaches a time-stamp to each arriving BHP, which records the arrival time of the associated data burst to the OSM. The time-stamp is the sum of the BHP arrival time, the burst offset-time τ carried by the BHP and the delay A introduced by input FDL 19. The forwarder mainly performs the forwarding table lookup to decide which outgoing CCG 52 to forward the BHP. The associated data burst will be switched to the corresponding DCG 54. The forwarding can be done in a connectionless or connection-oriented manner.

[0054] There is one scheduler for each DCG-CCG pair 52. The scheduler 42 schedules the switching of the data burst on a data channel of the outgoing DCG 54 based on the information carried by the BHP. If a free data channel is found, the scheduler 42 will then schedule the transmission of the BHP on the outgoing control channel, trying to “resynchronize” the BHP and its associated data burst by keeping the offset time τ (≧0) as close as possible to τ0. After both the data burst and BHP are successfully scheduled, the scheduler 42 will send the configuration information to the spatial switch controller 30 if it is not necessary to provide a delay through the recirculation buffer 26, otherwise it will also send the configuration information to the RB switch controller 28.

[0055] The data flow of scheduling decision process is shown in FIG. 2. In decision block 60, the scheduler 42 determines whether or not there is enough time to schedule an incoming data burst. If so, the scheduler determines whether the data burst can be scheduled, i.e., whether there is an unoccupied space in the specified output DCG 54 for the data burst. In order to schedule the data burst, there must be an available space to accommodate the data burst in the specified output DCG. This space may start within a time window beginning at the point of arrival of the data burst at the spatial switch 24 extending to the maximum delay which can be provided by the recirculation buffer 26. If the data burst can be scheduled, then the scheduler 42 must determine whether there is a space available in the output CCG 52 for the BHP in decision block 64.

[0056] If any of the decisions in decision blocks 60, 62 or 64 are negative, the data burst and BHP are dropped in block 65. If all of the decisions in decision blocks 60, 62 and 64 are positive, the scheduler sends the scheduling information to the path and channel selector 44. The configuration information from scheduler to path & channel selector includes incoming DCG identifier, incoming data channel identifier, outgoing DCG identifier, outgoing data channel identifier, data burst arrival time to the spatial switch, data burst duration, FDL identifier i (Qi delay time is requested, 0≦i≦B).

[0057] If the FDL identifier is 0, meaning no FDL buffer is required, the path & channel selector 44 will simply forward the configuration information to the spatial switch controller 30. Otherwise, the path & channel selector 44 searches for an idle incoming buffer channel to the RB switch 26 in decision block 68. If found, the path and channel selector 44 searches for an idle outgoing buffer channel from the RB switch 26 to carry the data burst reentering the spatial switch after the specified delay inside the RB switch 26 in decision block 70. It is assumed that once the data burst enters the RB switch, it can be delayed for any discrete time from the set {Q1, Q2, . . . , QB }. If this is not the case, the path & channel selector 44 will have to take the RB switch architecture into account. If both idle channels to and from the RB switch 26 are found, the path & channel selector 44 will send configuration information to the spatial switch controller 30 and the RB switch controller 28 and send an ACK (acknowledgement) back to the 42 scheduler. Otherwise, it will send a NACK (negative acknowledgement) back to the scheduler 42 and the BHP and data burst will be discarded in block 65.

[0058] Configuration information from the path & channel selector 44 to the spatial switch controller 30 includes incoming DCG identifier, incoming data channel identifier, outgoing DCG identifier, outgoing data channel identifier, data burst arrival time to the spatial switch, data burst duration, FDL identifier i (Qi delay time is requested, 0≦i≦B). If i>0, the information also includes the incoming BCG identifier (to the RB switch), incoming buffer channel identifier (to the RB switch), outgoing BCG identifier (from the RB switch), and outgoing buffer channel identifier (from the RB switch).

[0059] Configuration information from path & channel selector to RB switch controller includes an incoming BCG identifier (to the RB switch), incoming buffer channel identifier (to the RB switch), outgoing BCG identifier (from the RB switch), outgoing buffer channel identifier (from the RB switch), data burst arrival time to the RB switch, data burst duration, FDL identifier i (Qi delay time is requested, 1≦i≦B).

[0060] The spatial switch controller 30 and the RB switch controller 28 will perform the mapping from the configuration information received to physical components that involved in setting up the internal path(s), and configure the switches just-in-time to let the data burst fly-through the optical router 10. When the FDL identifier is larger than 0, the spatial switch controller will set up two internal paths in the spatial switch, one from the incoming data channel to the incoming recirculation buffer channel when the data burst arrives to the spatial switch, another from the outgoing buffer channel to the outgoing data channel when the data burst reenters the spatial switch. Upon receiving the ACK from the path & channel selector 44, the scheduler 42 will update the state information of selected data and control channels, and is ready to process a new BHP.

[0061] Finally, the BHP transmission module arranges the transmission of BHPs at times specified by the scheduler.

[0062] The above is the general description on how the data burst is scheduled in the optical router. Recirculating data bursts through the R×R recirculation buffer switch more than once could be easily extended from the design principles described below if so desired.

[0063] FIG. 3 illustrates a block diagram of a scheduler 42. The scheduler 42 includes a scheduling queue 80, a BHP processor 82, a data channel scheduling (DCS) module 84, and a control channel scheduling (CCS) module 86. Each scheduler needs only to keep track of the busy/idle periods of its associated outgoing DCG 54 and outgoing CCG 52.

[0064] BHPs arriving from the electronic switch are first stored in the scheduling queue 80. For basic operations, all that is required is one scheduling queue 80, however, virtual scheduling queues 80 may be maintained for different service classes. Each queue 80 could be served according to the arrival order of BHPs or according to the actual arrival order of their associated data bursts. The BHP processor 82 coordinates the data and control channel scheduling process and sends the configuration to the path & channel selector 44. It could trigger the DCS module 84 and the CCS module 82 in sequence or in parallel, depending on how the DCS and CCS modules 84 and 82 are implemented.

[0065] In the case of serial scheduling, the BHP processor 82 first triggers the DCS module 84 for scheduling the data burst (DB) on a data channel in a desired output DCS 54. After determining when the data burst will be sent out, the BHP processor then triggers the CCS module 86 for scheduling the BHP on an associated control channel.

[0066] In the case of parallel scheduling, the BHP processor 82 triggers the DCS module 84 and CCS module 86 simultaneously. Since the CCS module 86 does not know when the data burst will be sent out, it schedules the BHP for all possible departure times of the data burst or its subset. There are in total B+1 possible departure times. Based on the actual data burst departure time reported from the DCS module 84, the BHP processor 86 will pick the right time to send out the BHP.

[0067] Slotted transmission is used in data and control channels between edge and core and between core nodes in the OBS network. A slot is a fixed-length time period. Let Ts be the duration (e.g., in μs) of a time slot in data channels and Tf be the duration of a time slot in control channels. Ts·rd Kbits of information can be sent during a slot if the data channel speed is rd gigabits per second. Similarly, Tf·rc Kbits of information can be sent during a slot if the control channel speed is rc gigabits per second. Two scenarios are considered, (1) rc=rd and (2) rc≠rd. In the latter case, a typical example is that rc=rd/4 (e.g., OC-48 is used in control channels and OC-192 is used in data channels).

[0068] Without loss of generality, it is assumed that Tf is equal to multiples of Ts. Two examples are depicted in FIGS. 4a and 4b (see also, FIG. 18), which illustrates the timestamp and burst offset-time in a slotted transmission system for the cases where Tf=Ts and Tf=4Ts, with the initial offset time τ0=8Ts. To simplify the description, we use timeframe to designate time slot in control channels. It is further assumed without loss of generality that, (1) data bursts are variable length, in multiple of slots, which can only arrive at slot boundaries, and (2) BHPs are also variable length, in, for instance, multiple of bytes. Fixed-length data bursts and BHPs are just special cases. In slotted transmission, there is some overhead in each slot for various purposes like synchronization and error detection. Suppose the frame payload on control channels is Pf bytes, which is less than (Tf·rc)·1000/8 bytes, the total amount of information can be transmitted in a time frame.

[0069] The OSM is configured periodically. For slotted transmission on data channels, a typical example of the configuration period is one slot, although the configuration period could also be a multiple of slots. Here it is assumed that the OSM is configured every slot. The length of a FDL Qi needs also to be a multiple of slots, 1≦i≦B. Due to the slotted transmission and switching, it is suggested to use the time slot as a basic time unit in the SCU for the purpose of data channel scheduling, control channel scheduling and buffer channel scheduling, as well as synchronization between BHPs and their associated data bursts. This will simplify the design of various schedulers.

[0070] The following integer variables are used in connection with FIGS. 4a, 4b and 5:

[0071] tBHP: the beginning of a time frame during which the BHP enters the SCU;

[0072] tDB: the arrival time of a data burst (DB) to the optical switching matrix (OSM);

[0073] lDB: the duration/length of a DB in slots;

[0074] Δ: delay (in slots) introduced by input FDL

[0075] τ: burst offset-time (in slots).

[0076] Each arriving BHP to the SCU is time-stamped at the transceiver interface, right after O/E conversion, recording the beginning of the time frame during which the BHP enters the SCU. For the BHPs received by the SCU in the same time frame, they will have the same timestamp tBHp. For scheduling purpose, the most important variable is tDB, the DB arrival time to the OSM. Suppose a b-bit slot counter is used in the SCU to keep track of time, tDB can be calculated as follows.

t DB =(tBHP·Tf+Δ+τ)mod2b.  (1)

[0077] Timestamp tDB will be carried by the BHP within the SCU 32. Note that the burst offset-time τ is also counted starting from the beginning of the time frame that the BHP arrives as shown in FIGS. 4a-b, where in FIG. 4a, tBHp =9 and τ=6 slots, and in FIG. 4b, tBHP=2 and τ=7 slots. Suppose Δ=100 slots, we have tDB=115, meaning that the DB will arrive at slot boundary 115. In FIGS. 4a-b, 1≦τ≦τ0=8. It is assumed without loss of generality that the switching latency of the spatial switch in FIG. 1b is negligible. So the data burst arrival time tDB to the spatial switch 24 is also its departure time if no FDL buffer is used. Note that even if the switching latency is not negligible, tDB can still be used as the data burst departure time in channel scheduling as the switching latency is compensated at router output ports where data and control channels are resynchronized.

[0078] FIG. 5 illustrates a block diagram of a DCS module 84. In this embodiment, associative processor arrays PM 90 and PG 92 perform parallel searches of unscheduled channel times and gaps between scheduled channel times and update state information. Gaps and unscheduled times are represented in relative times. PM 90 and PG 92 are coupled to control processor CP1 94. In one embodiment, a LAUC-VF (Latest Available Unused Channel with Void Filling) scheduling principle is used to determine a desired scheduling, as described in connection with U.S. Ser. No. 09/689,584, entitled “Hardware Implementation of Channel Scheduling Algorithms of Optical Routers with FDL Buffers” to Zheng et al, filed Oct. 12, 2000, and which is incorporated by reference herein.

[0079] The DCS module 84 uses two b-bit slot counters, C and C1. Counter C keeps track of the time slots, which can be shared with the CCS module 86. Counter C1 records the elapsed time slots since the last BHP is received. Both counters are incremented by every pulse of the slot clock. However, counter C1 is reset to 0 when the DCS module 84 receives a new BHP. Once counter C1 reaches 2b-1, it stops counting, indicating that at least 2b-1 slots have elapsed since the last BHP. The value of b should satisfy 2b≧Ws where Ws is the data channel scheduling window. Ws=τ0+Δ+QB+Lmax−δ, where Lmax is the maximum length of a DB and δ is the minimum delay of a BHP from O/E conversion to the scheduler 42. Assuming that τ0=8, Δ=120, QB=32, Lmax=64, and δ=40, then Ws=184 slots. In this case, b=8 bits.

[0080] Associative processor PM in FIG. 5 is used to store the unscheduled time of each data channel in a DCG. Let ti be the unscheduled time of channel Hi which is stored in ith entry of PM 0≦i≦K−1. Then from slot ti onwards, channel Hi is free, i.e., nothing being scheduled. ti is a relative time, with respect to the time slot that the latest BHP is received by the scheduler. PM has an associative memory of 2K words to store the unscheduled times t, and channel identifiers, respectively. The unscheduled times are stored in descending order. For example, in FIG. 6 we have K=8 and t0≧t1≧t2≧t3≧t4∝t5≧t6≧t7.

[0081] Similarly, associative processor PG in FIG. 5 is used to store the gaps of data channels in a DCG. We use li, and rj to denote the start time and ending time of gap j, 0≦j≦G−1, which are also relative times. This gap is stored in jth entry of PG and its corresponding data channel is H. PG has an associative memory of G words to store the gap start time, gap ending time, and channel identifiers, respectively. Gaps are also stored in the descending order according to their start times lj. For example, FIG. 7 illustrates the associative memory of PG, where l0≧l1≧l2≧ . . . lG−2≧lG−1. G is the total number of gaps that can be stored. If there are more than G gaps, the newest gap with larger start time will push out the gap with the smallest start time, which resides at the bottom of the associative memory. Note that if lJ=0, then there are in total j gaps in the DCG, as lj+1=lj+2= . . . =lG−1=0.

[0082] Upon receiving a request from the BHP processor to schedule a DB with departure time tDB and duration lDB, the control processor (CP1) 94 first records the time slot th during which it receives the request, reads counter C1 (te←C1) and reset C1 to 0. Using tsch as a new reference time, the CP1 then calculates the DB departure time (no FDL buffer) with respect to tsch as

t′ DB =(tDB−tsch+2b)mod2b,  (2)

[0083] In the meantime, CP1 updates PM using

t i =max(0, ti−te), 0≦i≦K−1  (3)

[0084] and updates PG using the following formulas,

lj=max(0, lj−te), 0≦j≦G−1  (4)

[0085] and

r j =max(0, rj−te), 0≦j≦G−1.  (5)

[0086] After the memory update, CP1 94 arranges the search of eligible outgoing data channels to carry the data burst according to the LAUC-VF method, cited above. The flowchart is given in FIG. 8. In block 100, and index i is set to “0”. In block 102, PG finds a gap in which to transmit the data burst t′DB+Qi. In blocks 106, PM finds an unscheduled channel in PM to transmit the data burst at t′DB+Qi. Note that the operations of finding a gap in PG to transmit the DB at time t′DB+Qi and finding an unscheduled time in PM to transmit the DB at time t′DB+Qi are preferably performed in parallel. The operation of finding a gap in PG to transmit the data burst at time t′DB+Q, (block 102) includes parallel comparison of each entry in PG with (t′DB+Qi, t′DB+Qi+lDB) If t′DB+Qi>lj and t′DB+Qi+lDB≦rj, the response bit of entry j returns 1, otherwise it returns 0, 0≦j≦G−1. If at least one entry in PG returns 1, the gap with the smallest index is selected.

[0087] The operation finding an unscheduled time in PM to transmit the DB at time t′DB+Qi (block 106) includes parallel comparison of each entry in PM with t′DB+Qi. If t′DB+Qi≧tj, the response bit of entry j returns 1, otherwise it returns 0, 0≦j≦K−1. If at least one entry in PM returns 1, the entry with the smallest index is selected.

[0088] If the scheduling is successful in decision blocks 104 or 108, then the CP1 will inform the BHP processor 82 of the selected outgoing data channel and the FDL identifier in blocks 105 or 109, respectively. After receiving an ACK from the BHP processor 82, the CP1 94 will update PG 90 or PM 94 or both. If scheduling is not successful, i is incremented in block 110, and PM and PG try to a time to schedule the data burst at a different delay. Once Qi reaches the maximum delay (decision block 112), the processors PM and PG report that the data burst cannot be scheduled in block 114.

[0089] To speed up the scheduling process, the search can be performed in parallel. For example, if B=2 and three identical PM'S and PG'S are used, as shown in FIG. 5, one parallel search will determine whether the data burst can be sent out at times t′DB, t′DB+Q1, and t′DB+Q2. The smallest time is chosen in case that the data burst can be sent out at different times. In another example, if B=5 and three identical PM'S and PG'S are used, at most two parallel searches will determine whether the DB can be scheduled.

[0090] Some simplified versions of the LAUC-VF methods are listed below which could also be used in the implementation. First, an FF-VF (first fit with void filling) method could be used wherein the order of unscheduled times in PM and gaps in PG are not sorted in a given order (either descending or ascending order), and the first eligible data channel found is used to carry the data burst. Second, a LAUC (latest available unscheduled channel) method could be used wherein PG is not used, i.e., no void filling is considered. This will further simplify the design. Third, a FF (first fit) method could be used. FF is a simplified version of FF-VF where no void filling is used.

[0091] The block diagram of the CCS module 86 is shown in FIG. 9. Similar to the DCS module 84, associative processor PT 120 keeps track of the usage of the control channel. Since a maximum of Pf bytes of payload can be transmitted per frame, memory T 121 of PT 120 tracks only the number of bytes available per frame (FIG. 10). Relative time is used here as well. The CCS module 86 has two bi-bit frame counters, Cf and C1f. Cf counts the time frames. C1f records the elapsed frames since the receiving of the last BHP. Upon receiving a BHP with arrival time tDB, CP2 122 timestamps the frame during which this BHP is received, i.e., tschf←Cf. In the meantime, it reads counter C1f (tef←C1f) and reset C1f to 0. It then updates the PT by shifting Bi's down by tef positions, i.e., =Bi, tef≦i≦2b1−1, and Bi=Pf for 2b1−tef≦i≦2b1−1. In the initialization, all the entries in PT are set to Pf Next, CP2 calculates the frame tDBf during which the data burst will depart (assuming FDL Qi is used) using

t DB f (Qi)=└((tDB+Qi)mod2b)/Tf┘, 0≦i≦B.  (6)

[0092] where Tf is the frame length in slots. The relative time frame that the DB will depart is calculated from

t′ DB f (Qi)=(tDBf(Qi)−tschf−2b1 )mod2b1, 0≦i≦2.  (7)

[0093] The parameter bi can be estimated from parameter b1 e.g., 2b1=2b/Tf . When b=8 and Tf=4, b1=6. The following method is used to search for the possible BHP departure time for a given DB departure time t (e.g., t=t′DBf (Q1)). The basic idea is to send the BHP as earlier as possible, but the offset time should be no larger than τ0 (as described in connection with FIGS. 4a and 4b). Let J=└τ0/Tf┘. For example, when τ0=8 slots and Tf=1 slot, J=8. When τ0=8 slots and Tf=4 slots, J=2. Suppose the BHP length is X bytes.

[0094] In the preferred embodiment, a constrained earliest time (CET) method is used for scheduling the control channel, as shown in FIG. 11. In step 130, PT 120 performs a parallel comparison of X (i.e., the length of a BHP) with the contents Bt−j of relevant entries of memory T 121, Et−j, 0≦j≦J−1 and t−j>0. If X≦Bt−j, entry Et−j, returns 1, otherwise it returns 0. In step 132, if at least one entry in PT returns 1, the entry with the smallest index is chosen in step 134. The index is stored and the CCS module 86 reports that a frame to send the BHP has been found. If no entry in PT returns a “1”, then a negative acknowledgement is sent to the BHP processor 82. (step 136)

[0095] The actual frame tf that the BHP will be sent out is (tDBf−j+2b1)mod2b1 if Et−j is chosen. The new burst offset-time is (tDBmod Tf)+j·Tf.

[0096] After running the CET method, the CCS module 86 sends the BHP processor 82 the information on whether the BHP can be scheduled and in which time frame it will be sent. Once it gets an ACK from the BHP processor 82, the CCS module 86 will update PT. For example, if the content in entry y needs to be updated, then By←By−X. If the BHP cannot be scheduled, the CCS module 86 will send a NACK to the BHP processor 82. In the real implementation, the contents in PT do not have to move physically. A pointer can be used to record the entry index associated with the reference time frame 0.

[0097] For parallel scheduling, as discussed below, since the CCS module 86 does not know the actual departure time of the data burst, it schedules the BHP for all possible departure times of the data burst or a subset and reports the results to the BHP processor 82. When B=2, there are three possible data burst departure times, t′DB, t′DB+Q1 and t′DB+Q2 . Like the DCS module 84, if three identical PT's are used, as shown in FIG. 9, one parallel search will determine whether the BHP can be scheduled for the three possible data burst departure times.

[0098] A block diagram of the path & channel selector 44 is shown in FIG. 12. The function of the path & channel selector 44 is to control the access to the R×R RB switch 26 and to instruct the RB switch controller 28 and the spatial switch controller 30 to configure the respective switches 26 and 24. The path & channel selector 44 includes processor 140 coupled to a recirculation-buffer-in scheduling (RBIS) module 142, a recirculation-buffer-out scheduling (RBOS) module 144 and a queue 146. The RBIS module 142 keeps track of the usage of the R incoming channels to the RB switch 26 while the RBOS module 144 keeps track of the usage of the R outgoing channels from the RB switch 26. Any scheduling method can be used in RBIS and RBOS modules 142 and 144, e.g., LAUC-VF, FF-VF, LAUC, FF, etc. Note that RBIS module 142 and RBOS module 144 may use the same or different scheduling methods. From manufacturing viewpoint, it is better that the RBIS and RBOS module use the same scheduling method as the DCS module 84. Without loss of generality, it is assumed here that the LAUC-VF method is used in both RBIS and RBOS modules 142 and 144; thus, the design of DCS module can be reused can be used for these modules.

[0099] Assuming a data burst with duration lDB arrives to the OSM at time tDB and requires a delay time of Qi. The processor 140 triggers the RBIS module 142 and RBOS module 144 simultaneously. It sends the information of tDB and lDB to the RBIS module 142, and the information of time-to-leave the OSM (tDB +Qi) and lDB to the RBOS module 144. The RBIS module 142 searches for incoming channels to the RB switch 26 which are idle for the time period of (tDB , tDB +lDB). If there are two or more eligible incoming channels, the RBIS module will choose one according to LAUC-VF. Similarly, the RBOS module 144 searches for outgoing channels from the RB switch 26 which are idle for the time period of (tDB +Qi, tDB +lDB+Q,). If there are two or more eligible outgoing channels, the RBOS module 144 will choose one according to LAUC-VF. The RBIS (RBOS) module sends either the selected incoming (outgoing) channel identifier or NACK to the processor. If an eligible incoming channel to the RB switch 26 and an eligible outgoing channel from the RB switch 26 are found, the processor will send back ACK to both RBIS and RBOS module which will then update the channel state information. In the meantime, it will send ACK to the scheduler 42 and the configuration information to the two switch controllers 28 and 30. Otherwise, the processor 140 will send NACK to the RBIS and RBOS modules 142 and 144 and a NACK to the scheduler 42.

[0100] The RBOS module 144 is needed because the FDL buffer to be used by a data burst is chosen by the scheduler 42, not determined by the RB switch 26. It is therefore quite possible that a data burst can enter the RB switch 26 but cannot get out of the RB switch 26 due to outgoing channel contention. An example is shown in FIG. 13, where three fixed-length data bursts 148a-c arrive to the 2×2 RB switch 26. The first two data bursts 148a-b will be delayed 2D time while the third DB will be delayed D time. Obviously, these three data bursts will leave the switch at the same time and contend for the two outgoing channels. The third data burst 148c is lost in this example.

[0101] The BHP transmission module 46 is responsible for transmitting the BHP on outgoing control channel 52 in the time frame determined by the BHP processor 82. Since the frame payload is fixed, equal Pf, in slotted transmission, one possible implementation is illustrated in FIG. 14, where the whole memory is divided into Wc segments 150 and BHPs to be transmitted in the same time frame are stored in one segment 150. Wc is the control channel scheduling window, which equals to 2b1 . There is a memory pointer per segment (shown in segment W0, pointing to the memory address where a new BHP can be stored. To distinguish BHPs within a frame, the frame overhead should contain a field indicating the number of BHPs in the frame. Furthermore, each BHP should contain a length field indicating the packet length (e.g., in bytes), from the first byte to the last byte of the BHP.

[0102] Suppose tc is the current time frame during which the BHP is received by the BHP transmission module and pc points to the current memory segment. Given the BHP departure time frame tf, the memory segment to store this BHP is calculated from (pc+(tf−tc+2b1) mod 2b1) mod 2b1.

[0103] FIG. 15 shows the optical router architecture using passive FDL loops 160 as the recirculation buffer, where the number of recirculation channels R=R1+R2+ . . . +RB, with jth channel group introducing Qj delay time, 1≦j≦B. Here the recirculation channels are differentiated while in FIG. 1b all the recirculation channels are equivalent, able to provide B different delays. The potential problem of using the passive FDL loops is the higher block probability .of accessing the shared FDL buffer. For example, suppose B=2, R=4 and R1=2, R2=2, and currently two recirculation channels of R1 are in use. If a new DB needs to be delayed by Q1 time, it may be successfully scheduled in FIG. 1b, as there are still two idle recirculation channels. However, it cannot be scheduled in FIG. 15, since the two channels able to delay Q1 are busy.

[0104] The design of the SCU 32 is almost the same as described previously, except for the following changes: (1) the RBOS module 144 within the path & channel selector 44 (see FIG. 12) is no longer needed, (2) slight modification is required in the RBIS module 142 to distinguish recirculation channels if B>1. To reduce the blocking probability of accessing the FDL buffer when B>1, the scheduler is required to provide more than one delay option for each databurst that needs to be buffered. The impact on the design of scheduler and path & channel selector 44 is addressed below. Without loss of generality, it is assumed in the following discussion that the scheduler 42 has to schedule the databurst and the BHP for B+1 possible delays.

[0105] The design of DCS module 84 shown in FIG. 5 remains valid in this implementation. The search results could be stored in the format shown in Table 1 (assuming B=2), where the indicator (1/0) indicates whether or not an eligible data channel is found for a given delay, say Qi. The memory type (0/1) indicates PM or PG. The entry index gives the location in the memory, which will be used for information update later on. The channel identifier column gives the identifiers of the channels found. The DCS module then passes the indicator column and the channel identifier column (only those with indicator 1) to the BHP processor.

TABLE 1
Stored search results in DCS module (B = 2).
	Indicator	Memory type	Entry Index Max	Channel identifier
	(1 bit)	(1 bit)	(log2 G, log2 K) bits	(log2 K bits)
Q0
Q1
Q2

[0106] The design of CCS module 86 shown in FIG. 9 also remains valid. The search results could be stored in the format shown in Table 2 (assuming B=2), where the indicator (1/0) indicates whether or not the BHP can be scheduled on the control channel for a given DB departure time. The entry index gives the location in the memory, which will be used for information update later on. The “frame to send BHP” column gives the time frames in which the BHP are scheduled to send out. The CCS module then passes the indicator column and the “frame to send BHP” column (only those with indicator 1) to the BHP processor.

TABLE 2
Stored search results in CCS module (B = 2).
	Indicator	Entry Index	Frame to send BHP
	(1 bit)	(b1 bits)	(b1 bits)
	Q0
	Q1
	Q2

[0107] After comparing the indicator columns from the DCS and CCS modules, the BHP processor 82 in FIG. 3 knows whether the data burst and its BHP can be scheduled for a given FDL delay Q1, 1≦i≦B and determines which configuration information will be sent to the path & channel selector 44 in FIG. 12. The three possible scenarios are, (1) the data burst can be scheduled without using FDL buffer, (2) the data burst can be scheduled via using FDL buffer, and (3) the data burst cannot be scheduled.

[0108] In the third case, the data burst and its BHP are simply discarded. In the first case, the following information will be sent to the path & channel selector: incoming DCG identifier, incoming data channel identifier, outgoing DCG identifier, outgoing data channel identifier, data burst arrival time to the spatial switch, data burst duration, FDL identifier 0 (i.e. Q0). The path & channel selector 44 will immediately send back an ACK after receiving the information. In the second case, the following information will be sent to the path & channel selector:

[0109] incoming DCG identifier,

[0110] incoming data channel identifier,

[0111] number of candidate FDL buffer x,

[0112] for (i=1 to x do)

[0113] outgoing DCG identifier,

[0114] outgoing data channel identifier,

[0115] FDL identifier i,

[0116] data burst arrival time to the spatial switch,

[0117] data burst duration.

[0118] In the second scenario, the path & channel selector 44 will search for an idle buffer channel to carry the data burst. The RBIS module 142 is similar to the one described in connection with FIG. 12, except that now it has a PM and PG pair for each group of channels with delay Qi, 1≦i≦B. An example is shown in FIG. 16 for B=2, as an example. With one parallel search, the RBIS module will know whether the data burst can be scheduled. When x=1, the RBIS module 142 performs parallel search on (PM1 90a, PG1 92a) or (PM2 90b, PG2 92b), depending on which FDL buffer is selected by the BHP processor 82. If an idle buffer channel is found, it will inform the processor 140, which in turn sends an ACK to the BHP processor 82. When x=2, both (PM1, PG1) and (PM2, PG2) will be searched. If two idle channels with different delays are found, the channel with delay Q1 is chosen. In this case, an ACK together with the information that Q1 is chosen will be sent to the BHP processor 82. After a successful search, the RBIS module 142 will update the corresponding PM and PG pair.

[0119] FIGS. 17-26 illustrate variations of the LAUC-VF method, cited above. In the LAUC-VF method cited above, two associative processors PM and PG are used to store the status of all channels of the same outbound link. Specifically, PM stores r words, one for each of the r data channels of an outbound link. It is used to record the unscheduled times of these channels. PG contains n superwords, one for an available time interval (a gap) of some data channel. The times stored in PM and PG are relative times. PM and PG support associative search operations, and data movement operations for maintaining the times in a sorted order. Due to parallel processing, PM and PG are used as major components to meet stringent real-time channel scheduling requirement.

[0120] In the embodiment described in FIGS. 22-23, a pair of associative processors PM and PG for the same outbound link are combined into one associative processor PMG. The advantage of using a unified PMG to replace a pair of PM and PG is the simplification of the overall core router implementation. In terms of ASIC implementation, the development cost of a PMG can be much lower than that of a pair of PM and PG. PMG can be used to implement a simpler variation of the LAUC-VF method with faster performance.

[0121] In FIGS. 17a and 17b, two outbound channels Ch1 and Ch2 are shown, with to being the current time. With respect to t0, channel Ch1 has two DBs, DB1 and DB2, scheduled and channel Ch2 has DB3 scheduled. The time between DB1 and DB2 on Ch1, which is a maximal time interval that is not occupied by any DB, is called a gap. The times labeled ti and t2 are the unscheduled time for Ch1 and Ch2, respectively. After t1 and t2, Ch1 and Ch2 are available for transmitting any DB, respectively.

[0122] The LAUC-VF method tries to schedule DBs according to certain priorities. For example, suppose that a new data burst DB4 arrives at time t′. For the situation of FIG. 17a, DB4 can be scheduled within the gap on Ch1, or on Ch2 after the unscheduled time of Ch2. The LAUC-VF method selects Ch1 for DB4, and two gaps are generated from one original gap. For the situation of FIG. 17b, DB4 conflicts with DB1 on Ch1 and conflicts with DB3 on Ch2. But by using FDL buffers, it may be scheduled for transmission without conflicting DBs on Ch1 and/or DBs on Ch2. FIG. 17b shows the scheduling that DB4 is assigned to C2, and a new gap is generated.

[0123] Assuming that an outbound link has r data channels, the status of this link can be characterized by two sets:

[0124] SM{(ti, i) | ti, is the unscheduled time for channel Chi}

[0125] SG{(lj, rj, cj) | lj<rj and the interval [lj, rj] is a gap on channel Chcj}

[0126] In the embodiment of LAUC-VF proposed in U.S. Ser. No. 09/689,584, the two associative processors PM and PG were proposed to represent SM and SG, respectively. Due to fixed memory word length, the times stored in the associative memory M of PM and the associative memory G of PG are relative times. Suppose the current time is to. Then any time value less than to is of no use for scheduling a new DB. Let

S′ M ={(max{ti−t0, 0}, i)|(ti, i)∈SM}

S′ G ={(max{lj−t0, 0}, max{lj−t0, 0}, cj)|(lj, rj, cj)∈SG}

[0127] The times in S′M and S′G are times relative to the current time to, which is used as a reference point 0. Thus, M of PM and G of PG are actually used to store S′M and S′G respectively.

[0128] The channel scheduler proposed in U.S. Ser. No. 09/689,584 assumes that DBs have arbitrary lengths. One possibility is to assume a slot transmission mode. In this mode, DBs are transmitted in units of slots, and BHPs are transmitted as groups, and each group is carried by a slot. A slot clock CLKs is used to determine the slot boundary. The slot transmissions are triggered by pulses of CLKs. Thus, the relative time is represented in terms of number of CLKs cycles. The pulses of CLKs are shown in FIG. 18. In addition to clock CLKs, there is another finer clock CLKf. The period of CLKs is a multiple of the period CLKf. In X the example shown in FIG. 18, one CLKs cycle contains sixteen CLKf cycles. Clock CLKf is used to coordinate operations performed within a period of CLKs.

[0129] In FIGS. 19a and 19b, modifications to the hardware design of PM and PG given in U.S. Ser. No. 09/689,584 are provided for accommodation of slot transmissions. In PM, there is an associative memory M of r words. Each word Mi of M is essentially a register, and it is associated with a subtractor 200. A register MC holds an operand. In the embodiment of FIG. 19a, the value stored in MC is the elapsed time since the last update of M. The value stored in MC is broadcast to all words Mi, 1≦i≦r. Each word Mi does the following: Mj←Mj−MC if Mj>MC; otherwise, Mi←0. This operation is used to update the relative times stored in M. If MC stores the elapsed time since last time parallel subtraction operation is performed, performing this operation again updates these times to the time relative to the time when this new PARALLEL-SUBTRACTION is performed. Another operation is the parallel comparison. In this operation, the value stored in MC is broadcast to all words Mi, 1≦i≦r. Each word Mi does the following: if MC>Mi then MFLAGi=1, otherwise MFLAGi=0. Signals MFLAGi, 1≦i≦r, are transformed into an address by a priority encoder. This address and the word with this address are output to the address and data registers, respectively, of M. This operation is used to find a channel for the transmission of a given DB. Similarly, two subtractors are used for a word, one for each sub-word, of the associative memory G in PG.

[0130] An alternative design, shown in FIG. 19b, is to implement each word Mi in M as a decrement counter with parallel load. The counter is decremented by 1 by every pulse of the system slot clock CLKs. The counting stops when the counter reaches 0, and the counting resumes once the counter is set to a new positive value. Suppose that at time to the counter's value is t′ and at time ti>t0 the counters value is t″. Then t″ is the same time of t′, but relative to ti, i.e. t″=max{t′−(t1−t0), 0}. Note that any negative time (i.e. t′−(ti−t0)<0) with the new reference point ti is not useful in the lookahead channel scheduling. Associated with each word Mi is a comparator 204. It is used for the parallel comparison operation. Similarly, a word of G in PG can be implemented by two decrement counters with two associated comparators.

[0131] The system has a c-bit circular increment counter Cs. The value of Cs is incremented by 1 by every pulse of slot clock CLKs. Let tlatancy (BPHPi) be the time, in terms of number of S′G cycles, between the time BHPi is received by the router and the time BHPi is received by the channel scheduler. The value c is chosen such that: 1$2^c>\lceil \frac{\max t_{\mathrm{latency}}\left({\mathrm{BHP}}_i\right)}{{\mathrm{MAX}}_s}\rceil$

[0132] where MAXs is the number of CLKf cycles within a CLKs cycle. When BHPi is received by the router, BHPi is timestamped by operations timestamprecv(BHPi)←Cs. When BHPi is received by the scheduler of the router, BHPi is timestamped again by timestampsch(BHPi)←CS. Let

D i =(timestamprecv(BHPi)+2c−timestampsch(BHPi))mod2c.

[0133] Then, the relative arrival time (in terms of slot clock CLKs) of DBi at the optical switching matrix of the router is Ti=Δ+τi+Di, where τi is the offset time between BHPi and DBi, and D is the fixed input FDL time. Using the slot time at which timestampsch(BHPi)←Cs is performed as reference point, and the relative times stored in PM and PG, DBi can be correctly scheduled.

[0134] In the hardware implementation of LAUC-VF method, associative processors PM and PG are used to store and process S′M and S′G, respectively. At any time, S′M ={(ti, i)|1≦i≦r} and S′G ={(lj, rj, cj)|lj≧0}. A pair (ti, i) in S′M represents the unscheduled time on channel Chi, and a triple (lj, rj, cj) in S′G represents a time gap (interval) [lj, rj] on channel Chcj. The unscheduled time ti can be considered as a semi-infinite gap (interval) [ti, ∞]. Thus, by including such semi-infinite gaps into S′G, S′M is no longer needed.

[0135] More specifically, let S″M={(ti, ∞, i)|(ti, i)∈S′M}, and define S′MG=S″M∪S′G. The basic idea of combining PM and PG is to build PMG by modifying PG SO that PMG is used to process S′MG. We present the architecture of associative processor PMG for replacing PM and PG. PMG uses an associative memory MG to store pairs in S′M and triples in S′G. As G in PG, each word of MG has two sub-words, with the first one for lj and second one for rj when it is used to store (1j, rj, cj). When a word of MG is used to store a pair (ti, i) of S′M, the first sub-word is used forti, and the second is left unused. The first r words are reserved for S′M, and the remaining words are reserved for S′G. The first r words are maintained in non-increasing order of their first sub-word. The remaining words are also maintained in non-increasing order of their first subword. New operations for PMG are defined.

[0136] Below, the structures and operations of PM and PG are summarized, and the structure and operations of PMG are defined. The differences between PMG include the number of address registers used, the priority encoders, and operations supported. It is shown that PMG can be used to implement the LAUC-VF method without any slow-down, in comparison with the implementation using PM and PG.

[0137] The outbound data channel of a core router has r channels (wavelengths) for data transmission. These channels are denoted by Ch1, Ch2, Chr. Let S={ti|1≦i≦r}, where ti is the unscheduled time for channel Chi. In other words, at any time after ti, channel Ch1 is available for transmission. Given a time T′, PM is an associative processor for fast search of T″=min{ti|ti|ti≧T′}, where T′ is a given time. Suppose that T″=tj, then channel Chj is considered as a candidate data channel for transmitting a DB at time T′.

[0138] For purposes of illustration, the structures of PM and PG are shown in FIGS. 20 and 21 and PMG is shown in FIG. 22.

[0139] An embodiment of PM 210 is shown in FIG. 20. Associative processor PM includes an associative memory M 212 of k words, M1, M2, . . . , Mk, one for each channel of the data channel group. Each word is associated with a simple subtraction circuit for subtraction and compare operations. The words are also connected as a linear array. Comparand register MC 214 holds the operand for comparison. MCH 216 is a memory of k words, MCH1, MCH2, . . . , MCHk, with MCHj corresponding to Mj. The words are connected as a linear array, and they are used to hold the channel numbers. MAR1 218 and MAR2 220 are address registers for holding addresses for accessing M and MCH. MDR 222 and MCHR 224 are data registers used to access M and MCHR along with the MARs.

[0140] Associative processor PM supports the following major operations that are used in the efficient implementation of the LAUC-VF channel scheduling operations:

[0141] RANDOM-READ: Given address x in MAR1, do MDR1←Mx, MCHR←MCHX.

[0142] RANDOM-WRITE: Given address x in MAR1, do Mx←MDR, MCHx ←MCHR.

[0143] PARALLEL-SEARCH: The value of MC is compared with the values of all word M1, M2, . . . , Mk simultaneously (in parallel). Find the smallest j such that Mj<MC, and do MAR1←j, MDR1←Mj, and MCHR←MCH. If there does not exist any word Mj such that Mj<MC, MAR1=0 after this operation.

[0144] SEGMENT-SHIFT-DOWN: Given addresses a in MAR1, and b in MAR2 such that a<b, perform Mj+1←Mj and MCHj←MCHj for all a≦j<b.

[0145] For RANDOM-READ, RANDOM-WRITE and SEGMENT-SHIFT-DOWN operations, each pair (Mj, MCHj) is treated as a superword. The output of PARALLEL-SEARCH consists r binary signals, MFLAG1, 1≦i≦r. MFLAGi1 if and only if Mi≦MC. There is a priority encoder with MFLAGi, 1≦i≦r, as input, and it produces an address j and this value is loaded into MAR1 when PARALLEL-SEARCH operation is completed. RANDOM-READ, RANDOM-WRITE, PARALLEL-SEARCH and SEGMENT-SHIFT-DOWN operations are used to maintain the non-increasing order of values stored in M.

[0146] FIG. 21 illustrates a block diagram of the associative processor PG 92. A PG is used to store unused gaps of all channels of an outbound link of a core router. A gap is represented by a pair (l, r) of integers, where l and r are the beginning and the end of the gap, respectively. Associative processor PG includes associative memory G 93, comparand register GC 230, memory GCH 232, address register GAR 234, data registers GDR 236 and GCHR 238 and working registers GR1 240 and GR2 242.

[0147] G is an associative memory of n words, G1, G2, . . . , Gn, with each Gi consisting of two sub-words Gi,1 and Gi,2. The words are connected as a linear array. GC holds a word of two sub-words, GC1 and GC2. GCH is a memory of n words, GCH1, GCH2, . . . , GCHn with GCHj corresponding to Gj. The words are connected as a linear array, and they are used to hold the channel numbers. GAR is an address register used to hold address for accessing G. GDR, and GCHR are data registers used to access M and MCHR, together with GAR.

[0148] Associative processor PG supports the following major operations that are used in the efficient implementation of the LAUC-VF channel scheduling operations:

[0149] RANDOM-WRITE: Given address x in GAR, do Gx,1←GDR1←Gx,2←GDR2, GCHx←GCHR.

[0150] PARALLEL-DOUBLE-COMPARAND-SEARCH: The value of GC is compared with the values of all word G1,G2, . . . , Gn simultaneously (in parallel). Find the smallest j such that Gj,1<GC1 and Gj,2>GC2. If this operation is successful, then do GDR1←Gj,1, GDR2←Gj,2, GCHR←GCHj, and GAR←j; otherwise, GAR←0.

[0151] PARALLEL-SINGLE-COMPARAND-SEARCH: The value of GC1 is compared with the values of all word G1,G2, . . . ,Gn simultaneously (in parallel). Find the smallest j such that Gj,1>GC1 and j in a register GAR. If this operation is successful, then do GDR1←Gj,1, GDR2←Gj,2, GCHR←GCHj, and GAR←j; otherwise, GAR←0.

[0152] BIPARTITION-SHIFT-UP: Given address a in GAR, shift the content of Gj+1 to Gj←Gj+1, GCHj←GCHj+1, GCHj to GCHj+1 for a ≦j≦n, and Gn,1←0, Gn,2←0.

[0153] BIPARTITION-SHIFT-DOWN: Given address a in GAR, do Gj+1←Gj, GCHj+1←GCHj, a≦j<n.

[0154] In PG, a triple (Gi,1, Gi,2,GCHi) corresponds to a gap with beginning time Gi,1 and ending time Gi,2 on channel GCH1. For RANDOM-WRITE, PARALLEL-DOUBLE-COMPARAND-SEARCH, PARALLEL-SINGLE-COMPARAND-SEARCH, BIPARTITION-SHIFT-UP, and BIPARTITION-SHIFT-DOWN operations, each triple (Gi,1, Gi,2, GCHi) is treated as a superword. The output of PARALLEL-DOUBLE-COMPARAND-SEARCH (resp. PARALLEL-SINGLE-COMPARAND-SEARCH) operation consists n binary signals, GFLAGi, 1≦i≦n, such that GFLAGi=1 if and only if Gi,l≧GC1 and Gi,2≦GC2 (resp. Gi,1≧GC1). There is a priority encoder with GFLAGi=1≦i≦n, as input, and it produces an address j and this value is loaded into GAR1 when the operation is completed. RANDOM-WRITE, PARALLEL-SINGLE-COMPARAND-SEARCH, BIPARTITION-SHIFT-UP, and BIPARTITION-SHIFT-DOWN operations maintain the non-increasing order of values stored in Gi,1s.

[0155] The operations of PM and PG are discussed in greater detail in U.S. Ser. No. 09/689,584.

[0156] FIG. 22 illustrates a block diagram of a processor PMG, which combines the functions of the PM and PG processors described above. PMG includes associative memory MG 248, comparand register MGC 250, memory MGCH 252, address registers MGAR1 254a and MGAR2 254b, and data registers MGDR 256 and MGCHR 258.

[0157] MG is an associative memory of m=r+n words, MG1, MG2, . . . , MGm, with each MGi consisting of two sub-words MGi,1 and MGi,2. The words are also connected as a linear array. MGC is a comparand register that holds a word of two sub-words, MGC1 and MGC2. MGC also holds a word of two sub-words, MGC1 and MGC2. MGCH is a memory of m words, MGCH1, MGCH2,. . . , MGCHm with MGCHj corresponding to MGj. The words are connected as a linear array, and they are used to hold the channel numbers.

[0158] Associative processor PMG supports the following major operations:

[0159] RANDOM-READ: Given address x in MGAR1, do MGDR1 F MGi,1, MGDR2←MGi,2, MCHR←MGCHx.

[0160] RANDOM-WRITE: Given address x in MGAR, do MGXx,1←MGDR1, MGx,2←MGDR2, MGCHx←MGCHR.

[0161] PARALLEL-COMPOUND-SEARCH: In parallel, the value of MGC1 is compared with the values of all superwords MGi, 1≦i≦m, and the values of MGC1 and MGC2 are compared with all super words MGj, r +1≦j≦m, in parallel. (i) If MGC2≠0, then do the following in parallel: Find the smallest j′ such that j′≦r and MGj′, 1<MGC1. If this search is successful, then do MGAR1←j′, otherwise, MGAR1←0. Find the smallest j″ such that r+1≦j″≦m, MGj,1<MGC1 and MGj,2>MGC2. If this search is successful, then do MGAR2←j′ and MGCHR←MGCHi; otherwise MGAR2←0. (ii) If MGC2=0, then find the smallest j′ such that 1≦j′<m and MGj,1<MGC1. MGj,2>MGC2. If this search is successful, then do MGAR1←j″ and MGCHR←MGCHi; otherwise MGAR1←0.

[0162] BIPARTITION-SHIFT-UP: Given address a in MGAR1, do MGj←MGj+1, MGCHj←MGCHj+1, MGCH, to MGCHj+1 for a≦j≦m, and MGn,1←0, MGn,2←0.

[0163] SEGMENT-SHIFT-DOWN: Given addresses a in MGAR1, and b in MGAR2 such that a<b, perform MGj+1←MGj and MGCHj+1←MGCHj for all a≦j<b.

[0164] As in PG, a triple (MGi,1, MGi,2, MGCHi) may correspond to a gap with beginning time MGi,1 and ending time MGi,2 on channel MGCHi. But in such a case, it must be that i>r. If i≦r, then MGi,2 is immaterial, the pair (MGi,1, MGCHi) is interpreted as the unscheduled time MGi,1 on channel MGCHi, and this pair corresponds to a word in PM. For RANDOM-READ, RANDOM-WRITE, PARALLEL-COMPOUND-SEARCH, BIPARTITION-SHIFT-UP and SEGMENT-SHIFT-DOWN operations, each triple (MGi,1, MGi2, . . . , MGCHi) is treated as a superword. The first r superwords are used for storing the unscheduled times of r outbound channels, and the last m−r superwords are used to store information about gaps on all outbound channels.

[0165] The output of PARALLEL-COMPOUND-SEARCH operation consists of binary signals MGFLAGi whose values are defined as follows: (i) if MGC2=0 and MGi,1≧MGC1 then MGFLAGi=1; (ii) if MGC2×0, i≦r, MGi,1≧MGC1 then MGFLAGi=1; (iii) if MGC2×0, i>r, MGi,1 ≧MGC1 and MGi,2≦MGC2 then MGFLAG1=1, or if MGi,1>MGC1 and i≦r then MGFLAGi=1; and (iv) otherwise, MGFLAG1=0.

[0166] There are two encoders. The first one uses MGFLAG1, 1≦i≦r, as its input, and it produces an address in MGAR1 after a PARALLEL-COMPOUND-SEARCH operation is performed if MGC2≠0. The second encoder uses MGFLAGi, r+1≦i≦m, as its input. It produces an address in MGAR2 after a PARALLEL-COMPOUND-SEARCH operation is performed if MGC2≠0. There is a selector with the output of the two encoders as its input. If MGC2=0, the smallest non-zero address produced by the two encoders, if such an address exists, Ys loaded into MGAR1 after a PARALLEL-COMPOUND-SEARCH operation is performed; otherwise, MGAR1 is set to 0 after a PARALLEL-COMPOUND-SEARCH operation is performed; If MGC2≠0 the output of the selector is disabled.

[0167] RANDOM-READ, RANDOM-WRITE, PARALLEL-COMPOUND-SEARCH1, BIPARTITION-SHIFT-UP and SEGMENT-SHIFT-DOWN operations are used to maintain the non-increasing order of values stored in MGi,1 of the first m words, and the non-increasing order of the values stored in MGi,1 of the last m−r words.

[0168] The operations of associative processors PM and PG can be carried out by operations of PMG without any delay when they are used to implement LAUC-VF channel scheduling method. We assume that PMG contains m=r+n superwords. In Table 3 (resp. Table 4), the operations of PM (resp. PG) given in the left column are carried out by operations of PMG given the right column. Instead of searching PM and PG concurrently, using PMG, this step can be carried out by PARALLEL-COMPOUND-SEARCH operation.

TABLE 3
Simulation of PM by PMG
PM              PMG
RANDOM-READ     RANDOM-READ
RANDOM-WRITE    RANDOM-WRITE
PARALLEL-SEARCH PARALLEL-COMPOUND-
                SEARCH
SEGMENT-SHIFT-  SEGMENT-SHIFT-DOWN
DOWN            (with_MGAR2 = m)

[0169]

TABLE 4
Simulation of PM by PMG
PG                         PMG
RANDOM-WRITE               RANDOM-WRITE
PARALLEL-DOUBLE-COMPARAND- PARALLEL-COMPOUND-
SEARCH                     SEARCH
PARALLEL-SINGLE-COMPARAND- PARALLEL-COMPOUND-
SEARCH                     SEARCH (with MGC2 = 0)
BIPARTITE-SHIFT-UP         SEGMENT-SHIFT-UP
                           (with MGAR2 = m)
BIPARTITE-SHIFT-DOWN       SEGMENT-SHIFT-DOWN
                           (with MGAR2 = m − 1)

[0170] In the LAUC-VF method, fitting a given DB into a gap is preferred, even the DB can be scheduled on another channel after its unscheduled time, as shown by the example of FIGS. 17a-b. With separate PM and PG and performing search operations on PM and PG simultaneously, this priority is justifiable. However, the overall circuit for doing so may be considered too complex.

[0171] By combining PM and PG into one associative processor, simpler and faster variations of this LAUC-VF methods are possible. An alternative embodiment is shown in FIG. 23. In this figure, processor P*MG 270 includes an array TYPE 272 with m bits, each bit being associated with a corresponding word in memory MG. If TYPEi=1 then MGi stores an item of S′M otherwise, MG, stores an item of S′G. Further, register TYPER 274 is a one-bit register used to access TYPE, together with MGAR1 and MGAR2.

[0172] Other differences between P*MG and PMG include the priority encoder used and the operations supported. When a new DB is scheduled, MG is searched. The fitting time interval found, regardless if it is a gap or a semi-infinite interval, will be used for the new DB. Once the DB is scheduled, one more gap may be generated. As long as there is sufficient space in MG, the new gap is stored in MG. When MG is full, an item of S′G may be lost. But it is enforced that all items of S′M must be kept.

[0173] Let tsout(DBi) and teout(DBi) be the transmitting time of the first and last slot of DBi at the output of the router, respectively. Then

t s out (DBi)=Ti+Lj

[0174] and

t e out (DBi)=Ti+Lj+length(DBi),

[0175] where Ti is the relative arrival time defined above, Lj is the FDL delay time selected for DBi in the switching matrix and length(DB2) is the length of DBi in terms of number of slots. Assume that there are q+1 FDLs L0, L1, . . . , Lq in the DB switching matrix such that L0=0<L1<L2< . . . <Lq−i<Lq. The new variation of LAUC-VF is sketched as follows:

method CHANNEL-SCHEDULING
begin
success ← 0;
for j = 0 to q do
MGC1 ←Tl+Lj
MGC2 ← Tl + Lj + length(DBi);
perform PARALLEL-COMPOUND-SEARCH using P*MG;
if MGAR1 ≠ 0 then
if MGAR1 ≠ 0 then
begin
output MGCHR as the number of the channel for transmitting DBi
output Lj as the selected FDL delay time for DBi;
update MG of P* MG using the values in MGC1 and MGC2
success ← 1;
exit /* exit the for-Loop */
end
endfor
if success = 0 then drop DBi/* scheduling for DBi is failed */
end

[0176] Once a DB is scheduled, MG is updated. When a gap is to be added into MG, and TYPEm=1, the new gap is ignored. This ensures that no item belonging to S′M is lost.

[0177] Associative processor P*MG supports the following major operations:

[0178] RANDOM-READ: Given address x in MGAR1, do MGDR1←MGi,1, MGDR2←MGi,2, MCHR←MGCHx, TYPER←TYPEx.

[0179] RANDOM-WRITE: Given address x in MGAR1, do MGx,1←MGDR1, MGx,2←MGDR2, MGCHx←MGCHR, TYPEx←TYPER.

[0180] PARALLEL-COMPOUND-SEARCH: The value of MGC1 is compared with the values of all superwords MGi, 1≦i≦m, and MGC2 are compared with all super words MGi, 1≦i≦m, whose TYPEi=0, in parallel. Find the smallest j′ such that TYPEj′=1 and MGj′,1<MGC1, or TYPEj=0, MGj,1<MGC1 and MGj,2>MGC2. If this search is successful, then do MGAR1←j′, TYPER←TYPEj′, MGCH←MGCHj′; otherwise, otherwise MGAR1←0.

[0181] BIPARTITION-SHIFT-UP, SEGMENT-SHIFT-DOWN: same as in PMG.

[0182] In operation, The value of TYPEi indicates the type of information stored in MGi. As in PG, a triple (MGi,1, MGi,2, MGCHi) may correspond to a gap with beginning time MGi,1 and ending time MGi,2 on channel MGCH1. But in such a case, it must be that TYPE1=0. If TYPE1=1, then MGi,2 is immaterial, the pair (MGi,1, MGCHi) is interpreted as the unscheduled time MGi,1 on channel MGCHi and this pair corresponds to a word in PM. For RANDOM-READ, RANDOM-WRITE, PARALLEL-COMPOUND-SEARCH, BIPARTITION-SHIFT-UP and SEGMENT-SHIFT-DOWN operations, each quadruple (MGi,1, MGi,2, TYPEi, MGCHi) is treated as a superword.

[0183] The output of PARALLEL-COMPOUND-SEARCH operation consists of binary signals MGFLAGi whose values are defined as follows. If MGC2≈0, TYPE=0, Gi,1≧GC1 and Gi,2 >GC2 then MGFLAGi=1. If MGC2=0 and Gi,1≧GC, then MGFLAGi=1. Otherwise, MGFLAGi=0. There is a priority encoders. If MGFLAGi, 1≦i≦m, as its input, and it produces an address in MGAR1 after a PARALLEL-COMPOUND-SEARCH operation is performed.

[0184] RANDOM-READ, RANDOM-W7RITE, PARALLEL-COMPOUND-SEARCH, BIPARTITION-SHIFT-UP and SEGMENT-SHIFT-DOWN operations are used to maintain the non-increasing order of values stored in MGi,1s.

[0185] FIG. 24 illustrates the use of multiple associative processors for fast scheduling. Channel scheduling for an OBS core router is very time critical, and multiple associative processors (shown in FIG. 24 as P*MG processors 270), which are parallel processors, are proposed to implement scheduling methods. Suppose that there are q+1 FDLs L0=0, L1, . . . , Lq in the DB switching matrix such that L0 <L1 < . . . <Lq. These FDLs are used, when necessary, to delay DBs and increase the possibility that the DBs can be successfully scheduled. In the implementation of the LAUC-VF method presented in U.S. Ser. No. 09/689,584, the same pair of PM and PG are searched repeatedly using different FDLs until a scheduling solution is found or all FDLs are exhausted. The method CHANNEL-SCHEDULING described above uses the same idea.

[0186] To speed up the scheduling, a scheduler 42 may use q+1 PM/PG pairs, one for each Li. At any time, all q+1 Ms have the same content, all q+1 MCHs have the same content, all q+1 Gs have the same content, and all q+1 GCHs have the same content. Then finding a scheduling solution for all different FDLs can be performed on these PM/PG pairs simultaneously. At most one search result is used for a DB. All PM/PG pairs are updated simultaneously by the same lock-step operations to ensure that they store the same information. Similarly, one may use q+1 PMGS or P*MGS to speed up the scheduling.

[0187] In FIG. 24, a multiple processor system 300 uses q+1 P*MGS 270 implement the method CHANNEL-SCHEDULING described above. Similarly, the LAUC-VF method can be implemented using multiple PM/PG pairs, or multiple PMGS in a similar way to achieve better performance. The multiple P*MGS 270 include q+1 associative memories MG0, MG1, . . . , MGq. Each MGi has m words MGj1, MGj2, . . . , MGjm, with each MGj1 consisting of two sub-words MGji,1 and MGji,2. There are q+1 comparand registers MGC0, MGC1, . . . , MGCq. Each MGCj holds a word of two sub-words, MGCj1, and MGCj2. MGCHs: There are q+1 associative memories MGCH0, MGCH1 . . . , MGCHq. Each MGCHj has m words, MGCHj1, MGCHj2, . . . , MGCHjm. The words in MGCHj are connected as a linear array. There are q+1 linear arrays TYPE0, TYPE1, . . . , TYPEq, where TYPEj has m bits, TYPDj1, TYPEj2 . . . , TYPEjm. MGAR1, MGAR are address registers used to hold address for accessing MG and MGCH. MGDR, TYPER, MGCH are: data registers used to access MGs, TYPEs and MGCHR.

[0188] This multiple processor system 300 supports the following major operations:

[0189] RANDOM-READ: Given address x in MGAR1, do MGDR1←MG0t,1, MGDR2←MG0i,2, MCHR←MGCH0x, TYPER←TYPE0x.

[0190] RANDOM-WRITE: Given address x in MGAR1, do MGjx,1←MGDR1, MGjx,2←MGDR2, MGCHjx←MGCHR, TYPEjx←TYPER, for 0≦j≦q.

[0191] PARALLEL-COMPOUND-SEARCH: For 0≦j≦q, the value of MGCj1 is compared with the values of all superwords MGj1, 1≦i≦m, and MGj2 are compared with all super words MGji, 1≦i≦m, whose TYPEji=0. in parallel. For 0≦j≦q, find the smallest kj, such that TYPEjkj,1=1 and MGjkj,1<MGCj1, or TYPEjkj.=0, MGjkj,1<MGCj1 and MGjkj,2>MGCj2. If this search is successful, let lj=1; otherwise let lj=0. Find FD=min{j|lj=1,0≦j≦q}. If such l exists, then do j←FD, MGAR1←kj, TYPER←TYPDjkj., MGCH←MGCHjkj.; otherwise, otherwise MGAR1←0.

[0192] BIPARTITION-SHIFT-UP: Given address a in MGAR1, for 0≦j≦q, do MGji←MGji+1 MGCHji←MGCHji+1, MGCHji to MGCHji+1, for a≦i<m, and MGjn,1←0, MGjn,2←0.

[0193] SEGMENT-SHIFT-DOWN: Given addresses a in MGAR1, and b in MGAR2 such that a<b, for 0≦j≦q do MGji←MGji+1 and MGCHji+1←MGCHji for all a≦b.

[0194] A RANDOM-READ operation is performed on one copy of P*MG, i.e. MG0, TYPE0, and MG0. RANDOM-WRITE, PARALLEL-COMPOUND-SEARCH, BIPARTITION-SHIFTUP and SEGMENT-SHIFT-DOWN operations are performed on all copes of P*MG. For RANDOM-READ, RANDOM-WRITE, PARALLEL-COMPOUND-SEARCH, BIPARTITION-SHIFT-UP and SEGMENT-SHIFT-DOWN operations, each quadruple (MGi,1, MGi,2, TYPEi, MGCHi) is treated as a superword. When a PARALLEL-COMPOUND-SEARCH operation is performed, the output of all P*MG copies are the input of selectors. The output of one P*MG copy is selected.

[0195] The CHANNEL-SCHEDULING method may be implemented in the multiple processor system as:

method PARALLEL-CHANNEL-SCHEDULING
begin
success ← 0;
for j = 0 to q do in parallel
MGCj1 ← Tl+Lj
MGCj2 ← Tl+Lj+ length(DBi);
endfor
perform PARALLEL-COMPOUND-SEARCH;
if MGAR1 ≠ 0 then
begin
output MGCHR as the number of the channel for transmitting DB2;
output L, as the selected FDL delay time for DBi
k ≦ FD;
for j = 0 to q do in parallel
update MGj, 0 ≦j ≦q, using the values in MGCDRk1 and
MGDRk2
endfor
success ← 1;
end
if success = 0 then drop DBi /* scheduling for DBl is failed */
end

[0196] It may be desirable to be able to partition the r data channels into groups and choose a particular group to schedule DBs. Such situations may occur in several occasions. For example, one may want to test a particular channel. In such a situation, the channel to be tested by itself forms a channel group, and all other channels form another group. Then, channel scheduling is only performed on the 1-channel group. Another occasions is that during the operation of the router, some channels may fail to transmit DBs. Then, the channels of the same outbound link can be partitioned into two groups, the group that contains all failed channels, and the group that contains all normal channels, and only normal channels are to be selected for transmitting DBs. Partitioning data channels also allows channel reservation, which has applications in quality of services. Using reserved channel groups, virtual circuits and virtual networks can be constructed.

[0197] To incorporate group partition feature into channel scheduling associative processors, the basic idea is to associate a group identifier (or gid for short) with each channel. For a link, all the channels share the same gid belong to the same group. The gid of a channel is programmable; i.e. it can be changed dynamically according to need. The gid for a DB can be derived from its BHP and/or some other local information.

[0198] The design of PM and PG to PM-ext and PG-ext may be extended to incorporate multiple channel groups, as shown in FIGS. 25 and 26, respectively. As shown in FIG. 25, associative processor PM-ext 290 includes M, MC, MCH, MAR1, MAR2, MDR, MCHR, as described in connection with FIG. 20. MCIDC 292 is a comparand register that holds the gid for comparison. MGID 294 is a memory of r words, MGID1, MGID2,. ., MGIDr, with MGID1 corresponding to Mj and MCHj. The words are connected as a linear array, and they are used to hold the channel group numbers. MGIDDR 296 is a data register.

[0199] PM-ext is similar to PM with the addition of several components, and modifying operations. The linear array MGID has r locations, MGID1, MGID2. . . , MGIDr; each is used to store an integer gid. MGID, is associated with Mi and MCHi, i.e. a triple (Mi, MCHi, MGIDi) is treated as a superword. Comparand register MGIDC and data register MGIDDR are added.

[0200] Associative processor PM-ext supports the following major operations that are used in the efficient implementation of the LAUC-VF channel scheduling operations.

[0201] RANDOM-READ: Given address x in MAR1, do MDR←Mx, MCHx←MCHR and GIDR←MGIDx.

[0202] RANDOM-WRITE: Given address x in MAR1, do Mx←MDR, MCHx←MCHR and MGIDi←MGIDDR.

[0203] PARALLEL-SEARCH1: Simultaneously, MGIDC is compared with the values of MGID1, MGID2, . . . , MCIDr). Find j such that MGID, =MGIDC, and do MAR1←j, MDR1←Mj, MCHR←MCHj, and MGIDDR←MGID+j.

[0204] PARALLEL-SEARCH2: Simultaneously, (MC, MGIDC) is compared with (M1, MGID1), (M2, MGID2), . . . , (Mr, MGID2) Find the smallest j such that Mj <MC and MGIDJ=GIDC, and do MAR1←j, MDR1←Mj, MCHR←MCHj, and MGIDDR←MGID1. If there does not exist any word (Mj, MGIDj) such that Mj >MC and MGIDj=GIDC, MAR1=0 after this operation.

[0205] SEGMENT-SHIFT-DOWN: Given addresses a in MAR1, and b in MAR2 such that a<b, perform Mj, ←Mj+1←MCHj<MCHj and MGIDj+1←MGIDj. for all a≦j<b.

[0206] For RANDOM-READ, RANDOM-WRITE and SEGMENT-SHIFT-DOWN operations, each triple (Mj, MCHj, MGIDj) is treated as a superword. The output of PARALLEL-SEARCH1 consists r binary signals, MFLAGi, 1≦i≦r. MFLAGi=1 if and only if MGID1=MGIDC. There is a priority encoder with MFLAGi, 1≦i≦r, as input, and it produces an address j and this value is loaded into MAR1 when PARALLEL-SEARCH1 operation is completed. The output of PARALLEL-SEARCH2 consists r binary signals, MFLAGi, 1≦i≦r. MFLAGi=1 if and only if Mi≦MC and MGID1=MGIDC. The same priority encoder used in PARALLEL-SEARCH 1 transforms MFLAGi, 1≦i≦r, into an address j and this value is loaded into MAR1 when PARALLEL-SEARCH operation is completed. RANDOM-READ, RANDOM-WRITE, PARALLEL-SEARCH2 and SEGMENT-SHIFT-DOWN operations are used to maintain the non-increasing order of values stored in M.

[0207] FIG. 26 illustrates a block diagram of PG-ext. PG-ext 300 includes G,GC,GCH,GAR,GDR,GCHR, as described in connection with FIG. 21. GGIDC 302 is a comparand register for holding the gid for comparision. GGID 304 is a memory of r words, GGID1, GGID2, . . . , GGIDr, with GGIDj corresponding to Gj and GCHj. The words are connected as a linear array, and they are used to hold the channel group numbers. GGIDR 306 is a data register.

[0208] Similar to the architecture of PM-ext, a linear array GGID of n words, GGID1, GGID2, . . . , GGID, is added to PG. A quadruple (Gi,1, Gi,2, MCHi, GGIDi) is treated as a superword.

[0209] Associative processor PG-ext supports the following major operations that are used in the efficient implementation of the LAUC-VF channel scheduling operations.

[0210] RANDOM-WRITE: Given address x in GAR, do Gx,←GDR1, Gx,2←GDR2, GCHx←GCHR, GGIDx←GGIDR.

[0211] PARALLEL-DOUBLE-COMPARAND-SEARCH: The value of (GC, GGIDC) is compared with (G1, GGID1), (G2, GGID2), . . . , (Gn, GGIDn) simultaneously (in parallel). Find the smallest j such that Gj,1>GC1, Gj,2>GC2 and GGIDj=GGIDC. If this operation is successful, then do GDR1←Gj,1, GDR2←Gj,2, GCHR←GCHj, GGIDR←GGIDj and GAR←j; otherwise, GAR←0.

[0212] PARALLEL-SINGLE-COMPARAND-SEARCH: (GC1, GGIDC) is compared with (G1,1, GGID1), (G2,1, GGID2), . . . , (Gn,1, GGIDn,) simultaneously (in parallel). Find the smallest j such that Gj,1>GC1 and GGIDj=GGIDC. If this operation is successful, then do GDR1←Gj,1, GDR2←Gj,2, GCHR←GCHj, GGIDR←GGID, and GAR←j; otherwise, GAR←0.

[0213] BIPARTITION-SHIFT-UP: Given address a in GAR, shift the content of Gj+1 to Gj←Gj+1, GCHj←GCHj+1, GCHj to GCHj+1, GGID, to GGIDj+1, for a≦j≦n, and Gn,1←0, Gn,2←0.

[0214] BIPARTITION-SHIFT-DOWN: Given address a in GAR, do Gj+1←Gj, GCHj+1←CCHj, GGIDj+1 ←GCIDj, a≦j≦n.

[0215] A quadruple (Gi,1, Gi,2, GCHi, GGIDi) corresponds to a gap with beginning time GCi,1 and ending time Gi,2 on channel CCHi, whose gid is in GGIDi. For RANDOM-WRITE, PARALLEL-DOUBLE-COMPARAND-SEARCH, PARALLEL-SINGLE-COMPARAND-SEARCH, BIPARTITION-SHIFT-UP, and BIPARTITION-SHIFT-DOWN operations, each quadruple (GCr1, GCr2, GCHZ, GGID1) is treated as a super-word. The output of PARALLEL-DOUBLE-COMPARAND-SEARCH (resp. PARALLEL-SINGLECOMPARAND-SEARCH) operation consists n binary signals, GFLAGi, 1≦i≦n, such that GFLAGi=1 if and only if Gi,1≧GC1 and Gi,2≦GC2 (resp. Gi,1≧GC1), GGIDi=GGIDC. There is a priority encoder with GFLAGi, 1≦i≦n, as input, and it produces an address j and this value is loaded into GAR, when the operation is completed. RANDOM-WRITE, PARALLEL-SINGLE-COMPARAND-SEARCH, BIPARTITION-SHIFT-UP, and BIPARTITION-SHIFT-DOWN operations to maintain the non-increasing order of values stored in Gi,1s.

[0216] Changing the gid of a channel Chj from g1 to g2 is done as follows: find the triple (Mi, MCHi, MGIDi) such that MCHi, =j and store i into MARI and (MDR, MCHR, MGIDDR); MGIDDR←g2, and write back (MDR, MCHR, MGIDDR) using the address i in MARI.

[0217] Given a DB′, tsout(DB), teout(DB′), and a gid g, the scheduling of DB′involves searches in PM-ext and PG-ext. Searching in PM-ext is done as follows: find the smallest i such that M1<tsout(DB) and MGIDi=g. Searching in PG-ext is done as follows: find the smallest i such that Gi,1<tsout (DB′), Gi,2>tsout (DB′), and MGID1=g.

[0218] Similarly, associative processors PG-ext and PG*-ext can be constructed by adding a gid comparand register. MGGIDC, a memory MGGID of m words MGGID1, MGGID2, MGGIDm, and a data register MGGIDDR. PMG-ext is a combination of PM-ext and PG-ext. The operations of PMG-ext can be easily derived from the operations of PM-ext and PG-ext since the PM-ext items and the PG-ext items are separated. In P*MG-ext, the PM-ext items and the PG ext items are mixed. Since the MGi,1 values of these items are in non-decreasing order, finding the PM-ext item corresponding channel Ch1 can be carried out by finding the smallest j such that MGGIDj=i.

[0219] Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.

Claims

1. Circuitry for scheduling data bursts in a optical burst-switched router, comprising: an optical switch for routing optical information from an incoming optical transmission medium to one of a plurality of outgoing optical transmission media; a delay buffer coupled to the optical switch for providing n different delays for delaying information between the incoming transmission medium and the outgoing transmission media; scheduling circuitry associated with each outgoing medium, comprising n+1 associative processors, each associative processor including circuitry for: storing scheduling information for the associated outgoing optical transmission medium relative to a respective one of the n delays and for a zero delay, and identifying available time periods relative to the respective delays in which a data burst may be scheduled.

2. The circuitry of claim 1 wherein the incoming optical transmission medium and the outgoing optical transmission media comprise optical fibers.

3. The circuitry of claim 1 wherein the associative processors identify unscheduled time periods.

4. The circuitry of claim 1 wherein the associative processors identify gaps between scheduled data bursts.

5. The circuitry of claim 4 and further comprising a second set of n+1 associative processors, wherein the second set of associative processors identify unscheduled time periods.

6. The circuitry of claim 1 wherein said delay buffer comprises discrete delay lines each coupled a predetermined input and a predetermined output of said optical switch.

7. The circuitry of claim 1 wherein said delay buffer comprises a matrix of delay lines, where a desired delay line can be coupled between a selected input and selected output of said optical switch.

8. A method of scheduling data bursts in a optical burst-switched router that routes optical information through an optical switch from an incoming optical transmission medium to one of a plurality of outgoing optical transmission media either directly through the optical switch or via one of n different delays of a delay buffer, comprising the steps of; storing scheduling information in n+1 associative processors for the associated outgoing optical transmission medium relative to a respective one of the n delays and for a zero delay, and concurrently identifying available time periods in each of said associative processors in which a data burst may be scheduled, such that available time periods associated with multiple delays can be simultaneously determined.

9. The method of claim 1 wherein the incoming optical transmission medium and the outgoing optical transmission media comprise optical fibers.

10. The method of claim 1 wherein said concurrently identifying step comprises the step of concurrently identifying unscheduled time periods in each of said associative processors.

11. The method of claim 1 wherein said concurrently identifying step comprises the step of concurrently identifying gaps between data bursts in each of said associative processors.

12. The method of claim 11 wherein said concurrently identifying step further comprises the step of concurrently identifying unscheduled time periods in each of said associative processors.

13. The method of claim 1 wherein said delay buffer comprises discrete delay lines each coupled a predetermined input and a predetermined output of said optical switch.

14. The method of claim 1 wherein said delay buffer comprises a matrix of delay lines, where a desired delay line can be coupled between a selected input and selected output of said optical switch.